This document summarizes a research paper that compares different multiplier designs. It discusses array multipliers, Booth multipliers using Radix-2 and Radix-4 algorithms. Simulation results on FPGA show that Booth multipliers consume less power and area than array multipliers. Specifically, a 16x16 Booth multiplier was found to be more efficient in terms of speed and power consumption compared to other designs. The document provides background on multipliers and power optimization in VLSI systems. It also outlines the methodology used to simulate and compare the multipliers in terms of time delays, gate counts and power usage.