The advent of CMOS technology in RF integrated circuits has lead to integration. A practical manifestation of such SoC is DRP, a solution engineered at Texas Instruments Inc. in which digital baseband has been integrated with a RF transceiver all in CMOS technology. A logical step forward in use of such technology is to harness the power of the digital architecture and the baseband in implementing innovative solutions to enhance radio performance over corner conditions and mitigate interferences arising as a result of integration. This research focuses on five practical examples of software solutions for common challenges in DRP.

1. On-Chip Calibration and Compensation Techniques for Wireless SoCs Imran Bashir Nov 5 th , 2008

3. Motivation 1. Variation Due to Corner Conditions 40% Variation over Process & 15% Variation over Temperature

4. Motivation 1. Variation Due to Corner Conditions Without calibration and compensation, the phase error of the transmitter will fail 3GPP GSM specification. GSM 3GPP limit (5 degrees) Measured Simulated Target specification (3 degrees)

19. Mitigation of RF Oscillator Pulling Root Cause: Injection Pulling of DCO Worst case pulling with -60dB aggressor ~10kHz at DCO/5kHz at div-2 output.

22. Mitigation of RF Oscillator Pulling Root Cause: MOSCAP C-V Asymmetry Estimate of pulling with -60dB aggressor MOSCAP model 1 1 From Chih-Ming Hung and process qualification team. Change in capacitance 4.1aF

23. Mitigation of RF Oscillator Pulling Effect of Oscillator Current Increasing victim amplitude will reduce γ and pulling. Increasing victim amplitude reduces the sensitivity of DCO frequency to AM on DCO -> less pulling .

24. Mitigation of RF Oscillator Pulling Effect of Loop bandwidth Increase loop bandwidth improves EVM but degrades spectrum.

32. Calibration of DCO Current Variation of DCO Phase Noise Operating beyond optimum bias setting effects the DCO reliability. 400kHz Offset

33. Calibration of DCO Current Effect on Radio Performance R. Santucci, Waleed Khalil, and Dmitry Petrov, “Accurate Tuning and Calibration of Fractional-N Frequency Synthesizers,” Proc. of IEEE RFIC Symposium, “On-Chip Calibration, Compensation, and Filtering Techniques for Wireless SoCs,” Workshop, Session WSL-2, June 2008. The impact of DCO phase noise on system performance is more severe for dense modulation schemes.

34. Calibration of DCO Current Effect on Radio Performance Excessive DCO phase noise effects RMS Phase Error and spectrum performance of a GSM radio.

36. Calibration of DCO Current Validation of Proposed Solution Optimum DCO current using PHE based estimation PHE based estimation of DCO noise correlates with the measured DCO integrated noise.

40. Mitigation of ΣΔ Noise on DCO Effect of DCO Frequency & Temp For a calibrated delay, a change in DCO frequency or temperature, requires a change in delay code to return to best phase for ΣΔ clock.

48. Predistortion Calibration of DPA Lab Validation Higher DPA Power -> More AM on FREF signal -> Higher the extent of PHE.

49. Predistortion Calibration of DPA Lab Validation

51. Summary