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©	2017	Arm	Limited		
Mvapich	User	Group	Mee:ng,	2017	
Annapolis,	MD	
HPC	Network	
Stack	on	Arm	
Pavel	Shamis/Pasha	
Principal	Research	Engineer
©	2017	Arm	Limited		
Arm	Overview
©	2017	Arm	Limited		3	
An	introduc0on	to	Arm	
Arm	is	the	world's	leading	semiconductor	
intellectual	property	supplier.	
We	license	to	over	350	partners,	are	present	in	95%	of	smart	
phones,	80%	of	digital	cameras,	35%	of	all	electronic	devices,	and	a	
total	of	60	billion	Arm	cores	have	been	shipped	since	1990.	
Our	CPU	business	model:	
License	technology	to	partners,	who	use	it	to	create	their	own	
system-on-chip	(SoC)	products.	
We	may	license	an	instruc:on	set	architecture	(ISA)	such	as	
“ARMv8-A”)	
or	a	specific	implementa:on,	such	as	“Cortex-A72”.	
Partners	who	license	an	ISA	can	create	their	own	implementa:on,	
as	long	as	it	passes	the	compliance	tests.	
	
…and	our	IP	extends	beyond	the	CPU
©	2017	Arm	Limited		4	
A	business	model	that	shares	success	
•  Everyone	in	the	value	chain	benefits	
•  Long	term	sustainability	
Design	once	and	reuse	is	fundamental	
•  Spread	the	cost	amongst	many	partners	
•  Technology	reused	across	mul:ple	applica:ons	
•  Creates	market	for	ecosystem	to	target	
–  Re-use	is	also	fundamental	to	the	ecosystem	
Upfront	license	fee		
•  Covers	the	development	cost	
Ongoing	royal:es	
•  Typically	based	on	a	percentage	of	chip	price	
•  Vested	interest	in	success	of	customers	
A	partnership	business	model	
Approximately	1350	licenses	
Grows	by	~120	every	year		
More	than	440	poten:al	
royalty	payers	
14.8bn+	Arm-powered	chips	in	
2015	
Business	Development	
Licence	fee	
IP	
Provider	
SemiCo	
Partner	
Arm	Licenses		
technology	to	Partner	
Partners		
develop	
chips	
OEM	
Customer	
OEM	sells	
consumer	
products	
Royalty
©	2017	Arm	Limited		5	
Range	of	SoCs	addressing	infrastructure	
Highly	Accelerated		 Massively	Mul:core	
One	size	does	not	fit	all	
QorIQ®
Layerscape
2080A 
©	2017	Arm	Limited		6	
Serious	Arm	HPC	deployments	star0ng	in	2017	
Two	big	announcements	about	Arm	in	HPC	in	Europe:
©	2017	Arm	Limited		7	
Japan	
slides	from	Fujitsu	at	ISC’16
©	2017	Arm	Limited		
Integra0on	with	
Network	Interconnects
©	2017	Arm	Limited		9	
CCIX	
Accelerators	and	Network	(NIC/HCA/etc.)	as	a	first	class	
“ci:zen”	in	the	system	
Seamless	process	and	accelerator	hardware	cache	
coherence	support	
Low-latency	and	high-bandwidth	
Allow	in-line	accelera:on	
•  Bump	in	the	wire	processing	(network	packet	processing,	storage	
accelera:on,	etc.)	
Allows	“off-line”	accelera:on	(co-processor	model)	
Driver-less	/	interrupt-less	usage	model		
hmp://www.ccixconsor:um.com
©	2017	Arm	Limited		10	
Scale-up	server	node	
DMC-620
DMC-620 DMC-620
DMC-620
CoreLink CMN-600
Shared virtual memory system
DMC-620
DMC-620 DMC-620
DMC-620
CoreLink CMN-600
Accelerator	
Smart		
Network	
Persistent	
Memory
©	2017	Arm	Limited		11	
CCIX	mul0chip	connec0vity	and	topologies	
New	class	of	interconnect	providing	high	performance,	low	
latency	for	new	accelerators	use	cases	
•  CCIX	defines	25GT/s	(3x	performance*)		
•  Examining	56GT/s	(7x	performance*)	and	beyond		
•  Enabling	low	latency	via	light	transac:on	layer		
Flexible,	scalable	interconnect	topologies	
•  Flexible	point-to-point,	daisy	chained	and	switched	topologies	
Simplified	deployment	by	leveraging	exis:ng	PCIe	hardware	
and	sopware	infrastructure	
•  Runs	on	exis:ng	PCIe	transport	layer	and	management	stack		
•  Coexist	with	legacy	PCIe	designs	
	
Compute	Node	
Accelerator	
Smart		
Network	
Persistent	
Memory	
Switch	
*	Note:	Based	on	PCIe	Gen3	Performance
©	2017	Arm	Limited		12	
Building	CCIX	devices	
Cadence®	IP	for	CCIX		
•  Built	upon	silicon	proven	PCIe	solu:ons	
IP	products:	
•  Controller	IP	–	Provides	the	CCIX	transac:on	and	data	link	
layers.	
•  PHY	IP	–	Provides	the	high	performance	SERDES	physical	
layer	suppor:ng	speeds	up	to	25Gpbs.	
•  Verifica:on	IP	–	Provides	the	necessary	test	infrastructure	
to	verify	CCIX	designs.	
Cadence	Controller	&	PHY	IP
©	2017	Arm	Limited		13	
Cadence	CCIX	integra0on	
		
PCIe	
Transac:on	
Layer	
CCIX	
Transac:on	
Layer	
Data	Link	Layer	
	PHY	(up	to	25Gpbs)	
16	Lanes	
DMC-620
DMC-620 DMC-620
DMC-620
CoreLink CMN-600 XP	
CML	RNI	
CXS	
AXI	
Cadence	IP	
Example	CMN-600	mesh	design	
Low latency CCIX
transaction layer
Support up to 25Gbps vs
16Gbps PCIe Gen4
CML converts CHI to
CCIX messages
PCIe IP connects to a
CMN IO interface via AXI
©	2017	Arm	Limited		14	
Gen-Z	
All	data	is	accessed	by	some	form	of	a	Read	or	a	Write		
Example	of	reads:	DDR	Row	+	Column	Read,	PCI	DMA	Read,	SCSI	Write,	Socket	Read,	File	
Read,	RDMA	Read		
Example	of	writes:	DDR	Row	+	Column	Write,	PCI	DMA	Write,	SCSI	Read,	Socket	Write,	
File	Write,	RDMA	Write		
The	Goal:	Simplify	world	to	memory	seman:c	Reads	&	Writes
©	2017	Arm	Limited		15	
Gen-Z	Overview	
An	open,	standards-based,	scalable,	system	interconnect	and	protocol.		
Op:mized	to	support	memory	seman:c	communica:ons		
Breaks	Processor-Memory	Interlock	
Split	controller	model		
•  Memory	controller	
–  Ini:ates	high-level	requests—Read,	Write,	Atomic,	Put	/	Get,	etc.		
–  Enforces	ordering,	reliability,	path	selec:on,	etc.		
•  Media	controller		
–  Abstracts	memory	media	
–  Supports	vola:le	/	non-vola:le	/	mixed-media		
–  Performs	media-specific	opera:ons	
–  Executes	requests	and	returns	responses	
–  Enables	data-centric	compu:ng	(accelerator,	compute,	etc.)
©	2017	Arm	Limited		16	
Introducing	the	Scalable	Vector	Extension	(SVE)	
A vector extension to the ARMv8-A architecture with some major new features:
Gather-load	and	scamer-store	
Loads	a	single	register	from	several	non-con:guous	memory	loca:ons.	
Per-lane	predica:on	
Opera:ons	work	on	individual	lanes	under	control	of	a	predicate	register.	
Predicate-driven	loop	control	and	management	
Eliminate	scalar	loop	heads	and	tails	by	processing	par:al	vectors.	
Vector	par::oning	and	sopware-managed	specula:on	
First	Faul:ng	Load	instruc:ons	allow	memory	accesses	to	cross	into	invalid	pages.	
Extended	floa:ng-point	horizontal	reduc:ons	
In-order	and	tree-based	reduc:ons	trade-off	performance	and	repeatability.	
1	 2	 3	 4	
5	 5	 5	 5	
1	 0	 1	 0	
6	 2	 8	 4	
+	
=	
pred	
1	 2	 0	 0	
1	 1	 0	 0	
+	
pred	
1	 2	
1	 2	 3	 4	
1	 2	
+	
3	 4	
3	 7	
n-2	
1	 0	1	 0	CMPLT n
n-1	 n	 n+1	INDEX i
for (i = 0; i < n; ++i)
©	2017	Arm	Limited		17	
What’s	the	vector	length?	
There	is	no	preferred	vector	length	
•  Vector	Length	(VL)	is	the	CPU	
implementor’s	choice,	from	128	to	2048	
bits,	in	increments	of	128	
•  Adop:ng	a	Vector	Length	Agnos:c	(VLA)	
code	genera:on	style	makes	code	portable	
across	all	possible	vector	lengths.	
•  VLA	is	made	possible	by	the	per-lane	
predica:on,	predicate-driven	loop	control,	
vector	par::oning	and	sopware-managed	
specula:on	features	of	SVE.	
•  No	need	to	recompile,	or	to	rewrite	hand-
coded	SVE	assembler	or	C	intrinsics	
VL	
128b	
0	 64	
256b	
0	 128	
384b	
0	 128	 256	
128	
256	
384	
512b	
0	 128	 256	 384	 512
©	2017	Arm	Limited		
SoWware	Eco-system
©	2017	Arm	Limited		19	
Released	
Planned	
Concept	
2016	
Hardware	
Open-Source	
sopware	
Arm	HPC	tools	
Arm HPC ecosystem roadmap
2017	 Future	
Cavium	ThunderX	
Allinea	DDT	and	MAP	
Rogue	Wave	TotalView	
AppliedMicro	X-Gene	1	&	2	
Fujitsu	–	Post	K	(SVE)	
ISV	sopware	
AMD	Seamle	
Altair	PBS	Pro	
Cavium	ThunderX2	
Qualcomm	Centriq	
NAG	Library	&	Compiler	
Arm	Op:mized	Rou:nes	
GCC	(gcc/g++/gfortran)	
LLVM	-	clang	 LLVM	–	Flang	
ISV	sopware	
Arm	Code	Advisor	(Beta)	 Arm	Code	Advisor	(Full	release)	
Arm	Op:mized	Rou:nes	–	vector	versions	
Phy:um	Mars	
OpenHPC	1.3.1	
Arm	Performance	Libraries	
PathScale	ENZO	
Arm	Fortran	Compiler	Arm	C/C++	Compiler	–	ahead	of	LLVM	trunk	
Arm	Instruc:on	Emulator	
	AppliedMicro	X-Gene	3
©	2017	Arm	Limited		20
©	2017	Arm	Limited		21	
Linux	/	FreeBSD	w/	AARCH64	support	
ß	Engaged	with	FreeBSD	founda:on	/	Semi-half	&	Cavium	to	get	FreeBSD	on	ARMv8	
FreeBSD	Beta	version	demo’d	by	Semihalf	–	Nov.	2015	
12.04LTS	&	14.04LTS	
released	
ß	Also	14.10	&	15.04	releases	
Red	Hat	Enterprise	Linux	Server	for	Arm		
7.2		BETA	–	Sept,	2015		
Fedora	22	released	–	May	2015		
Fedora	23	released	–	Nov	2015	
		
CentOS	Linux	7	for	AArch64		
GA	–	August		2015	
OpenSUSE	13.2	–	Nov	2014	 SUSE	Launches	Partner	Program	to	Bring		
SUSE	Linux	Enterprise	12	to	64-bit	Arm		
July	2015	@	ISC	
Debian	8	adds	AARCH64	–	April		2015
©	2017	Arm	Limited		22	
Open	source	and	commercial	compilers	
§  LLVM
§  C, C++, Fortran
§  OpenMP 3.1, (4.0 coming soon)
§  Fortran coming Q1 2017
§  NAG
§  Fortran
§  OpenMP 3.1
§  GCC
§  C, C++, Fortran
§  OpenMP 4.0
§  Arm C/C++/Fortran
Compiler
§  LLVM based
§  Includes SVE
©	2017	Arm	Limited		
RDMA
©	2017	Arm	Limited		24	
RDMA	Networks	
Remote	Direct	Memory	Access	(RDMA)	–	popular	hardware	network	
technology	
•  InfiniBand	–	37%	of	systems	in	TOP500	
	
	
	
hmps://www.top500.org
©	2017	Arm	Limited		25	
VERBs	API	on	Arm	
•  Besides	bug	fixes	not	much	work	was	required	
•  Mellanox	OFED	2.4	and	above	supports	Arm	
•  Linux	Kernel	4.5.0	and	above	(maybe	even	earlier)	
•  Linux	Distribu:on	Support	–	on	going	process	
•  OFED	–	no	ARMv8	support
©	2017	Arm	Limited		26	
OpenUCX	v1.2	
•  The	first	official	release	from	Open	UCX	community	
•  hmps://github.com/openucx/ucx/releases/tag/v1.2.0	
•  Features	
•  Support	for	InfiniBand	and	RoCE	
•  Transports	RC,	UD,	DC		
•  Support	for	Accelerated	Verbs	–	40%	speedup	on	Arm	compared	to	vanilla	Verbs	
•  Support	for	UGNI	API	for	Aries	and	Gemini	
•  Support	for	Shared	Memory:	KNEM,	CMA,	XPMEM,	Posix,	SySV	
•  Support	for	x86,		ARMv8,	Power	
•  Efficient	memory	polling	–	36%	increase	in	efficiency	on	Arm	
•  UCX	interface	is	integrated	with	MPICH,	OpenMPI,	OSHMEM,	ORNL-SHMEM,	etc.	
Pavel	Shamis,	M.	Graham	Lopez,	and	Gilad	Shainer.	“Enabling	One-sided	Communica@on	Seman@cs	on	Arm“,	HIPS	2017
©	2017	Arm	Limited		27	
Programing	models	
MVAPICH	2.3b	–	works	on	ARMv8	!	
Open	MPI	–	works	on	ARMv8	
MPICH	–	compiles	and	runs	on	ARMv8	
OSHMEM	–	compiles	and	runs
©	2017	Arm	Limited		28	
Lessons	Learned	
Memory	Barriers	
•  Mul:thread	environment	
•  Sopware-hardware	interac:on			
•  Examples	hmps://github.com/openucx/ucx/blob/master/src/ucs/arch/aarch64/cpu.h#L25	
•  You	can	“fish”	for	these	bugs	in	MPI	implementa:ons	around	Eager-RDMA	and	shared	memory	
protocols		
	
Write	Payload	
Write	No0fy	
Busy-wait	Read	No0fy	
Read	Payload	
Write	Barrier	 Read	Barrier	
RDMA	
RDMA	
Maranget,	Luc,	Susmit	Sarkar,	and	Peter	Sewell.	"A	tutorial	introduc@on	to	the	Arm	and	POWER	relaxed	memory	models."	DraQ	
available	from	hSp://www.	cl.	cam.	ac.	uk/~	pes20/ppc-supplemental/test7.	pdf	(2012).
©	2017	Arm	Limited		29	
Lessons	Learned	–	con0nued	
Not	all	cache-lines	are	64Byte	!	
•  Implementa:on	dependent		
•  128Byte	and	64Byte	
	
hmp://xeroxnostalgia.com/duplicators/xerox-9200/
©	2017	Arm	Limited		
Preliminary	Results
©	2017	Arm	Limited		31	
Testbed	
•  2	x	Sopiron		Overdrive	3000	servers	with	AMD	Opteron	A1100	/	2GHz	
•  ConnectX-4	IB/VPI	EDR	(PCIe	gen2	x8)	
•  Ubuntu	16.04	
•  MOFED	3.3-1.5.0.0		
•  UCX	[0558b41]		
•  XPMEM	[bdfcc52]		
•  OSHMEM/OPEN-MPI	[fed4849]		
	
Pavel	Shamis,	M.	Graham	Lopez,	and	Gilad	Shainer.	“Enabling	One-sided	Communica@on	Seman@cs	on	Arm“
©	2017	Arm	Limited		32	
Hardware	SoWware	Stack	Overview
©	2017	Arm	Limited		33	
XPMEM	
XPMEM	-	Cross	Memory	Amach	
•  The	code	was	updated	to	compile	and	run	on	ARMv8	(hmps://github.com/hjelmn/xpmem)	
•  3rd	party	kernel	module	based	on	SGI/Cray	XPMEM	and	maintained	by	LANL	
XPMEM	 KNEM	 CMA	 MMAP	
System	Call	 No	 Yes	 Yes	 No	
Low	Latency	 V	 X	 X	 V	
High	Bandwidth		 V	 V	 V	 V	
Any	Virtual	Address	 V	 V	 V	 X	
Open	Source	 V	 V	 V	 V	
Upstream	Linux	 X	 X	 V	 V
©	2017	Arm	Limited		34	
OpenUCX:	XPMEM	
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©	2017	Arm	Limited		35	
OpenUCX	IB:	MLX5	vs	Verbs	
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©	2017	Arm	Limited		36	
SHMEM_WAIT()	
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©	2017	Arm	Limited		37	
OpenSHMEM	SSCA	
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©	2017	Arm	Limited		38	
OpenSHMEM	GUPs	
21%	
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©	2017	Arm	Limited		39	
Developer	website	:	www.arm.com/hpc	
A	HPC-specific	microsite		
This	is	home	to	our	HPC	ecosystem	offering:	
•  technical	reference	material	
•  how-to	guides	
•  latest	news	and	updates	from	partners	
•  downloads	of	HPC	libraries	
•  third-party	sopware	recommenda:ons	
•  web	forum	for	community	discussion	and	help		
	
Par:cipate	and	help	drive	the	community
40	40	 ©	2017	Arm	Limited		
The	Arm	trademarks	featured	in	this	
presenta:on	are	registered	trademarks	or	
trademarks	of	Arm	Limited	(or	its	
subsidiaries)	in	the	US	and/or	elsewhere.		All	
rights	reserved.		All	other	marks	featured	may	
be	trademarks	of	their	respec:ve	owners.	
	
www.arm.com/company/policies/trademarks

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