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Multiple Processor Organization

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



Single instruction, single data stream - SISD
Single instruction, multiple data stream - SIMD
Multiple instruction, single data stream - MISD
Multiple instruction, multiple data stream- MIMD
Single Instruction, Single Data
Stream - SISD





Single processor
Single instruction stream
Data stored in single memory
Uni-processor
Single Instruction, Multiple Data
Stream - SIMD








Single machine instruction
Controls simultaneous execution
Number of processing elements
Lockstep basis
Each processing element has associated data
memory
Each instruction executed on different set of
data by different processors
Vector and array processors
Multiple Instruction, Single Data
Stream - MISD





Sequence of data
Transmitted to set of processors
Each processor executes different instruction
sequence
Never been implemented
Multiple Instruction, Multiple
Data Stream- MIMD





Set of processors
Simultaneously execute different instruction
sequences
Different sets of data
SMPs, clusters and NUMA systems
Taxonomy of Parallel Processor
Architectures
Parallel Organizations - SISD
Parallel Organizations - SIMD
Parallel Organizations - MIMD
Shared Memory
Parallel Organizations - MIMD
Distributed Memory
Symmetric Multiprocessors


A stand alone computer with the following characteristics
 Two or more similar processors of comparable capacity
 Processors share same memory and I/O
 Processors are connected by a bus or other internal connection
 Memory access time is approximately the same for each processor
Continue……
 All processors share access to I/O
○ Either through same channels or different channels giving

paths to same devices
 All processors can perform the same functions (hence

symmetric)
 System controlled by integrated operating system
○ providing interaction between processors
○ Interaction at job, task, file and data element levels
Block Diagram of Tightly Coupled
Multiprocessor
SMP Advantages


Performance
If some work can be done in parallel, then

system with multiple processors yield
greater performance than single processor
of the same type.


Availability
Since all processors can perform the same

functions, failure of a single processor does
not halt the system
SMP Advantages


Incremental growth
User can enhance performance by adding

additional processors


Scaling
Vendors can offer range of products with

different price and performance which are
based on number of processors configured in
the system
Multiprogramming and
Multiprocessing
Organization Classification




Time shared or common bus
Multiport memory
Central control unit
Time Shared Bus




Simplest form
Structure and interface similar to single
processor system
Following features provided
Addressing - distinguish modules on bus
Arbitration - any module can be temporary

master
Time sharing - if one module has the bus, others
must wait and may have to suspend


Now have multiple processors as well as
multiple I/O modules
Symmetric Multiprocessor
Organization
Time Share Bus - Advantages




Simplicity
Flexibility
Reliability
Time Share Bus - Disadvantage



Performance limited by bus cycle time
Each processor should have local cache
Reduce number of bus accesses



Leads to problems with cache coherence
Solved in hardware - see later

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Multi processing

  • 1.
  • 2. Multiple Processor Organization     Single instruction, single data stream - SISD Single instruction, multiple data stream - SIMD Multiple instruction, single data stream - MISD Multiple instruction, multiple data stream- MIMD
  • 3. Single Instruction, Single Data Stream - SISD     Single processor Single instruction stream Data stored in single memory Uni-processor
  • 4. Single Instruction, Multiple Data Stream - SIMD        Single machine instruction Controls simultaneous execution Number of processing elements Lockstep basis Each processing element has associated data memory Each instruction executed on different set of data by different processors Vector and array processors
  • 5. Multiple Instruction, Single Data Stream - MISD     Sequence of data Transmitted to set of processors Each processor executes different instruction sequence Never been implemented
  • 6. Multiple Instruction, Multiple Data Stream- MIMD     Set of processors Simultaneously execute different instruction sequences Different sets of data SMPs, clusters and NUMA systems
  • 7. Taxonomy of Parallel Processor Architectures
  • 10. Parallel Organizations - MIMD Shared Memory
  • 11. Parallel Organizations - MIMD Distributed Memory
  • 12. Symmetric Multiprocessors  A stand alone computer with the following characteristics  Two or more similar processors of comparable capacity  Processors share same memory and I/O  Processors are connected by a bus or other internal connection  Memory access time is approximately the same for each processor
  • 13. Continue……  All processors share access to I/O ○ Either through same channels or different channels giving paths to same devices  All processors can perform the same functions (hence symmetric)  System controlled by integrated operating system ○ providing interaction between processors ○ Interaction at job, task, file and data element levels
  • 14. Block Diagram of Tightly Coupled Multiprocessor
  • 15. SMP Advantages  Performance If some work can be done in parallel, then system with multiple processors yield greater performance than single processor of the same type.  Availability Since all processors can perform the same functions, failure of a single processor does not halt the system
  • 16. SMP Advantages  Incremental growth User can enhance performance by adding additional processors  Scaling Vendors can offer range of products with different price and performance which are based on number of processors configured in the system
  • 18. Organization Classification    Time shared or common bus Multiport memory Central control unit
  • 19. Time Shared Bus    Simplest form Structure and interface similar to single processor system Following features provided Addressing - distinguish modules on bus Arbitration - any module can be temporary master Time sharing - if one module has the bus, others must wait and may have to suspend  Now have multiple processors as well as multiple I/O modules
  • 21. Time Share Bus - Advantages    Simplicity Flexibility Reliability
  • 22. Time Share Bus - Disadvantage   Performance limited by bus cycle time Each processor should have local cache Reduce number of bus accesses  Leads to problems with cache coherence Solved in hardware - see later