2. Key Assignments & Highlights
SPI Controller – implementation in VHDL
ADC interfacing using FPGA
Notch Filter Design & simulation using MATLAB
ATmega169 projects – Atmel Studio tool
ADC configuration program using C-language
USART configuration program using C-language
PIC16f877 projects – Microchip MPLABx tool
ADC configuration program using C-language
USART configuration program using C-language
EEPROM RD/WR program using C-language
VHDL Assignments
8-Bit Counter design and simulation using ModelSim
16-Bit Register design and simulation using ModelSim
4-Bit parallel Adder design and simulation using ModelSim
16-Bit Adder design and simulation using ModelSim
16-Bit Subtraction design and simulation using ModelSim
3. SPI Controller – implementation in VHDL
Object: Implementing the SPI master device in VHDL
Flow chart :
Start Slave
YES Req or NO
T_buf_
Send SCLK ful high
24-bits ? load master
complet YES
buffer with
ed transmit data
Master NO ? Save Rxd
buffer data
empty NO
? Make
T_buf_full bit
YES Select slave, send End
high
MSB bit to MOSI line
Make
T_buf_full bit
low
Left shift Master
buffer
Rising
_edg NO
(clk) Load LSB bit with
? received MISO line
YE
S
4. 16-bit ADC interfacing using FPGA
Object : interfacing 16-bit ADC to FPGA
NO
Flow Chart :
Rising_edg
e (clk)
Start YES ?
Send SCLK
Slave req NO
?
Operate ADC in YES
frame_sync discrete
mode, select sampling
rate 52ksps
YES
Rxd 16-
Select normal operation, bits
and sync mode, enable ?
channel-1 NO
Save received data
Load slave buff with
MISO bit
End
5. Notch Filter Design & simulation using MATLAB
Object: Designing NOTCH filter such that it can stop the 60Hz noise signal
High level block Diagram
60Hz noise
signal
Message Signal
Notch filter
signal + 60Hz
without
60Hz
“filter” is a function in matlab which filters input by taking coefficients and sig
y=filter(b,a,signal);
Filter Magnitude and phase response
6. ATmega169 : ADC configuration program
Object : writing firmware to control internal ADC in Atmega169
Configuring Internal Registers:
Load SREG|=0x80; global interrupt enable ; ADMUX|=0xC0
internal 1.1v reference; ADCSRA|=0x84; AD enable, AD interrupt enable;
ADCSRA|=0x20; positive edge trigger; ADCSRB|=0x40; free running mode;
ADCSRA|=0x40; start conversion
Flow Chart :
Start
Make PORT-B,-C NO
output Conversion
complete
enable AD interrupt, YES
AD conversion ,select
1.1v reference
Load higher byte into
port-b, lower into port-c
Operate in free
running mode, start
conversion
End
7. USART Receiver program using C-language
Object : Writing firmware to control USART receiver
Configuring Internal Registers:
UCSRB|=0xB6; UBRR|=0x67; UCSRC|=0x26 1-stop bit, data size-8bit
Flow chart :
Start
Enable RX complete Receiver
interrupt, usart data reg function
empty interrupt, Rx Start
enable, receive 8-bits
Make PORTB
Select baudrate 9600 at output
16MHz, asyn even parity
1-stop ,data bits-8
Byte NO
Call rx_data()
NO received ?
YES
10 bytes Load Data reg with UDR
received data, post data on to the
? portB
YES
End End
8. USART Transmitter program using C-language
Object : Writing firmware to control USART Transmitter
Configuring Internal Registers:
UCSRB|=0x69;
UBRR|=0x67; baud rate 9600 at f=16MHz
UCSRC|=0x26; aysn, evenparity,1-stopbit, data size 8-bit
Flow chart : Tx_data()
Start Start
Enable TX complete Load byte in UDR
interrupt, usart data reg register
empty interrupt, Tx
enable, Txt 8-bits
Byte NO
transmitted
Select baudrate 9600 at 10
?
16MHz, asyn even parity bytes
NO txd ? YE
1-stop ,data bits-8
S
YES
Make TXC bit zero
Call Tx_data(data[i]) End
End
9. PIC16F877: ADC configuration program
Object: Writing firmware to control internal Analog to Digital convertor in
PIC16F877
Configuring Internal Registers:
ADIE=1; this bit enables ADC interrupt
GIE=1; enables global interrupt
ADCON0=0x00; selecting channel-0 fosc/2;
ADCON1=0x8F; select ing analog AN0 input
ADON=1; start ADC
GODONE=1 start conversion
Start
Conversio
Make port-c,b n NO
output; enable ADC completed
interrupt ?
YES
select AN0 input; Load higher byte on to
Start operating AD; port-B, lower byte on to
port-C
Start conversion
End
10. PIC16F877: USART Receiver program
Object: Writing firmware in C language to control internal USART receiver in
16F877
Configuring Internal Registers:
SPBRG=0b00011111; setting baud rate 9600 at 20MHz
TxSTA=0x04;high speed baud rate
SPEN=1; serial port enable
RCIE=1; receive interrupt enable
PEIE=1; peripheral interrupt enable
Start Rx flag NO
high ?
Baudrate 9600, YE
enable serial port, Load RCREG S data in
receive int, Data reg,
peripheral int. Post data onto
PORTC
Clear CREN; clear
Start receiving
RCIF;
End
11. PIC16F877: USART Transmitter program
Object: Writing firmware in C language to control internal USART transmitter in
16F877
Configuring Internal Registers:
PEIE=1; enabling peripheral interrupt
SPBERG=0x1F; selecting baud rate 9600 at 20MHz
BRGH=1;high speed baud rate
SYNC=0; selecting asynchronous transmission
TxIE=1; transmit interrupt enable
Start
Transmit NO
Enable global interrupt, complete
peripheral interrupt, 9600 ?
baud rate, asyn
transmission, transmit int YE
S
Clear TxEN;
Clear TxIF;
Transmission enable,
Load data into TxREG
End
12. PIC16F877: EEPROM RD/WR program
Object: Writing firmware to control read/write operations in internal EEPROM of
16F877
Configuring Internal Registers:
EEIE=1; EEPROM interrupt enable
RP1=0; RP0=0; selecting Bank-0
EEADR reg stores the Address of EEPROM
EEDATA reg stores the Data to be write or read from EEPROM
EEIF is a EEPROM interrupt flag, used while writing operation
Start
Make PORTD as output, 20 bytes
enable EEPROM interrupt , red
select bank-0 Start writing YES ?
NO
20-byte YES load address,
complete Write NO make rd=1start
d complet reading,
NO ? e
?
Load address into
YE Place data onto
EEADR, enable write ,
S the PORTD;
load data onto the Clear int. Call some delay;
EECON2 reg, flag clear RD
EEDATA=EECON2 End
13. VHDL : 8-Bit Counter design
Object : Designing and simulating 8-bit up counter in modelsim tool.
It is designed with 8 filp-flops .
it can count up to a maximum value of “11111111” (255 in decimal )
when the reset signal is active high the count value set to all zeros that means all
the flip flops are reset
Start
Rising_ NO
edge(cl
NO k)
Reset ?
=„1‟ YES
CLK
Enable NO
8-bits YES pin
Reset high
Count set to
8-bit Up ?
0
Counter YES
Enable Count Increment Cout by
“1”
post Cout value on to
the count line
End
14. VHDL : 16-Bit Register design
Object : Designing and simulating 16-bit Register in modelsim
It is designed with 16- flip flops . Read/write operations can be performed
16-bit data on Reg_in line is loaded into the register when rw signal is active low
16-bit data is loaded onto the Reg_out line when rw signal is active high
16 Reg_in
En 15 14 13 12 --------- 3 2 1
CLK
rw
0
16 Reg_out
Start NO
Rw=0
?
Assign I/O‟s
YES
Load Register Post Register
Rising_ YES with Reg_in data onto the
edge(cl data Reg_out line
k) ?
NO
End
15. VHDL : 4-Bit parallel Adder design
Object: Designing and simulating 4-bit parallel adder in modelsim tool
It is designed using 4 full adders connected in series
The output carry of one fulladder is connected to the carry_in of left fulladder
The final carry is available at the left most fulladder
Block Diagram : A a3 a2 a1 a0
B b3 b2 b1 b0
Full Full Full Full
Adder Adder Adder Adder Cin
Carry_out 3 2 1 0
Sum S3 S2 S1 S0
Flow chart :
Start
Select I/O s S2=xor(a2,b2,c1);
C2=and(a2,b2)or
and(b2,c1) or
S0=xor(a0,b0,cin);
and(c1,a2);
C0=and(a0,b0)or
and(b0,cin) or S3=xor(a3,b3,c2);
and(cin,a0); C3=and(a3,b3)or
and(b3,c2) or
S1=xor(a1,b1,c0);
and(c2,a3);
C1=and(a1,b1)or
and(b1,c0) or
and(c0,a1); End
16. VHDL :16-Bit Adder design
Object: Designing and simulating 16-bit Adder in modelsim
it is designed using 16 full adder
Internal registers tempsum and tempcarry are used to store the sum and carry
After addition is performed the tempsum data is loaded onto the sum line and
tempcarry onto the carry line
A B 16
Block Diagram : 16
En 16-bit
ADDER
16 carry
Flow chart Sum
:
Start
Tempsum(A,B);
Assign I/Os Tempcarry(A,B);
NO Sum=tempsum;
En=1 Carry=tempcarr
? y;
YES End
17. VHDL : 16-Bit Subtraction design
Object : Designing 16-bit subtractor using 16-bit addition
Block Diagram : 2‟s
B compleme
nt sum
16bitAdd
16
C
er
-
NO Result
1 „0‟
? S<=sum
A 6 16
Sum 2‟s
Flow chart : En YES
compleme
nt
Start
Tempsum(A,B); Carry=0
Assign I/Os Tempcarry(A,B); ?
2‟s
NO complement
En=1 Sum=tempsum;
? Carry=tempcarr sum
y;
YES Result=sum
2‟s complement
B
End