Organización/Lugar de trabajo

Ubicación

Ocupación

Sector

Electronics / Computer Hardware

Sitio web

Acerca de

Physical Design : Netlist to GDSII Flow - Worked on 16nm technology in Cadence Encounter - worked on 90nm technology Block implementation in IC compiler - Worked on CLP for 14nm and 16nm - (Netlist - Floor Planning - Placement - Clock-tree Synthesis - Routing -Signoff), EDA TOOLS: First Encounter, Prime Time, IC Validator, Encouter Conformal Low Power