3. What is FPGA
Configurable Logic Blocks (CLBs) contain flexible
Look-Up Tables (LUTs) that implement logic plus storage elements used as
flip-flops or latches. CLBs perform a wide variety of logical functions as well as
store data.
• Input/Output Blocks (IOBs) control the flow of data
between the I/O pins and the internal logic of the device. Each IOB supports
directional data flow plus 3-state operation. Supports a variety of signal
standards, including four high-performance differential standards. Double Data-
Rate (DDR) registers are included.
• Block RAM provides data storage in the form of
18-Kbit dual-port blocks.
Digital Clock Manager (DCM) Blocks provide
self-calibrating, fully digital solutions for distributing, delaying ,
multiplying, dividing, and phase-shifting clock signals.
4.
5. I/O Capabilities
• 3.3V low-voltage TTL (LVTTL)
• Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,
1.5V, or 1.2V
• 3V PCI at 33 MHz, and in some devices, 66 MHz
• HSTL I and III at 1.8V, commonly used in memory
applications
• SSTL I at 1.8V and 2.5V, commonly used for memory
applications
Spartan-3E FPGAs support the following differential standards:
• LVDS
• Bus LVDS
• mini-LVDS
• RSDS
• Differential HSTL (1.8V, Types I and III)
• Differential SSTL (2.5V and 1.8V, Type I)
• 2.5V LVPECL inputs
9. Microcontroller Vs FPGA
Sequential operations
not so flexible
Low power
Less development
time
Easy to solder
Less No of I/O pin
• Parallel or Sequential
operations
• Flexible
• High power
• More development
time
• Complex to solder
• More No of I/O pin
16. Key Feature Set
• 16 byte-wide general-purpose data registers
• 1K instructions of programmable on-chip program
store, automatically
loaded during FPGA configuration
• Byte-wide Arithmetic Logic Unit (ALU) with CARRY
and ZERO
indicator flags
• 64-byte internal scratchpad RAM
• 256 input and 256 output ports for easy expansion
and enhancement
• Automatic 31-location CALL/RETURN stack
• Predictable performance, always two clock cycles per
instruction,
up to 200 MHz or 100 MIPS in a Virtex-4™ FPGA and 88 MHz
or 44 MIPS in a Spartan-3 FPGA
• Fast interrupt response; worst-case 5 clock cycles
• Assembler, instruction-set simulator support
24. Microblaze Overview
Microblaze is a soft core embedded in the bit
stream and is not available until the FPGA has
been configured.
Software-only; updates for Microblaze are
possible without regenerating the bit stream.
Is one of the Fastest soft processor
Virtex- 5 (- 2), 400 MHz
Virtex- II (- 5), 125 MHz
Is supported in the following Devices,
Virtex, VirtexE, VirtexII, Spartan- II, Spartan3
25.
26.
27.
28. Microblaze - Architecture
Thirty-two 32-bit general purpose registers.
Separate 32-bit instruction and data buses OPB (On-chip
Peripheral Bus).
Separate 32-bit instruction and data buses LMB (Local
Memory Bus).
Hardware multipliers (in Virtex-II and subsequent devices).
Three stage pipeline architecture : Fetch, Decode and
Execute.
29. MicroBlaze - Architecure
The Microblaze core is organized as a Harvard architecture
with separate bus interface units for data accesses and
instruction accesses.
Each bus interface unit is further split into a Local Memory
Bus (LMB) and IBM’s On-chip Peripheral Bus (OPB).
The LMB provides single-cycle access to on-chip dual port
block RAM.
The OPB interface provides a connection to both on and
off chip peripherals and memory.
30.
31. Embedded Development
Tool Flow Overview
Data2MEM
Bitstream
Compiler/Linker
(Simulator)
C Code
Debugger
Standard Embedded SW
Development Flow
CPU code in
on-chip
memory
?
CPU code in
off-chip
memory
Download to Board & FPGA
Object Code
Standard FPGA HW
Development Flow
Synthesizer
Place & Route
Simulator
VHDL/Verilog
?
Download to FPGA
32. EDK
The Embedded Development Kit (EDK) consists of
the following:
Xilinx Platform Studio – XPS
Base System Builder – BSB
Creating/Importing IP Wizard
Hardware generation tool – PlatGen
Library generation tool – LibGen
Simulation generation tool – SimGen
GNU software development tools
System verification tool – XMD
Processor IP
Drivers for IP
Documentation
Use the GUI or the shell command tool to run the
EDK tool
33. Microblaze : Area Statistics
Area consumed by Microblaze. For a simple 8-
bit counter written in “C” with the counter
contents being displayed on LEDs,
the details of the FPGA resources consumed
are as follows: -
Device Used SPARTAN II (XC2S100 TQ144 -
5)
Number of BLOCKRAMs 4 out of 10 40%
Number of SLICEs 769 out of 1200
64%
737 SLICES FOR MICROBLAZE
32 SLICES FOR One GPIO
Total 769 SLICES of FPGA
34. MicroBlaze - Benefits
The Complete Solution
Pre-verified and optimized
soft processor Core.
IBM CoreConnectTM bus
Peripherals compatible with
embedded PowerPCTM in
Xilinx next generation
Platform.
Microblaze applications can
range from software based
simple state machines to
complex controllers for
internet appliances or other
embedded applications.
35. MicroBlaze
32 Bit RISC
On Chip Peripheral Bus
BRAM
GPIO
LMB
UART Timer
Interrupt
Controller
OPB
EMAC
10/100
Ethernet Phy
IIC/SPI
MicroBlaze :System Application
36. MicroBlaze - System Diagram
Off-Chip
Memory
0-4GB
Off-Chip
Memory
0-4GB
Machine Status Reg
Program Counter
DataBusController
Register File
32 x 32bit
r0
r1
r3
1Address
side
LMB
CoreConnect
OPB I/F
CoreConnect
OPB I/F
TM TM
Data Side
LMB
UART
Timer /
Counters
Interrupt
Controller
General
Purpose I/O
Watchdog
Timer
Instruction Buffer
InstructionBusController
Control Unit
Multi
ply
Multi
ply
Add /
Subtract
Shift /
Logical Multiply
PROCESSOR
PERIPHERALS
I-LMB
I-OPB D-OPB
D-LMB
37. Soft Processors
Soft processor is an implementation of a microprocessor circuit
using a standard FPGA.
Features:
No dedicated silicon.
Highly flexible.
Advantages
Integration - Less IC’s on your board.
Modifiable / Customizable
Your system in silicon - nothing more, nothing less.
Performance -
Some functions are easier to implement in software.
Processor intensive functions can be Off- Loaded to hardware
integration.
38. Advantages - continued
Soft processor cores can be ‘owned’ by the
customer and used across many projects –
never going obsolete!
No IP / License issues
Peripherals can be added to make up the
required functions
No wastage of peripherals or logic gates!
Code and peripheral ‘banks’ can be built up
and used across many projects over time.