Protocol Aware ATE presentation from 2008 Beijing Advanced Semiconductor Technology Symposium

1. Protocol Aware ATE
Eric Larson
Senior Product Specialist
2008 Beijing Advanced Semiconductor
2009-3-
Technology Symposium
3
1

2. Why Protocol Aware Automatic
Test Equipment (ATE)?
A SMARTER TESTER MAKES TESTING EASIER
• In the end application semiconductor devices communicate with each other
at a high level of abstraction (Protocols), sending information back and
forth much like people having a phone conversation.
• Device designers use these Protocols to create and validate their designs
• ATE today does not quot;speakquot; Protocols so ATE users must interact with
Devices Under Test at a very low level of abstraction (Vectors), very much
like communicating in ASCII Code.
• Making ATE quot;Protocol Awarequot; will allow ATE users to interact with the
device using the same Protocol level of abstraction as designers
• Smarter ATE will make it much easier to interact with the devices during
silicon bring-up and debug on ATE and feed back results to design. Faster
debug means reduced development cycles and faster Time-to-Market
2008 Beijing Advanced Semiconductor Technology Symposium
2009-3-3
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3. Protocol Aware ATE: Outline
• The Impact of Silicon Integration on ATE
Users
• Protocol Aware ATE Applications
– Reduce or Eliminate System Level Test
– Speed up Silicon Bring-up and Debug
• Protocol Aware ATE Architecture
2008 Beijing Advanced Semiconductor Technology Symposium
2009-3-3
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4. Impact of Silicon Integration
on Device and ATE Complexity
In each decade semiconductor device complexity increases by >10x and
Chip
requires a new tester architecture
Complexity
(Transistor Count)
Protocol Aware
- New complex devices have more IP Blocks, more
10,000,000,000
gates, more clock domains.
ity
- IP re-use makes devices easier and faster to
ex
1,000,000,000
design but more difficult and slower to test.
pl
m
Co
100,000,000
unt
r Co
st
isto
Te
ans
Tr Integrated RF
10,000,000
And SERDES
1,000,000
Mixed Signal &
100,000
Memory Test
Per Pin Timing
10,000
Time
2000’s
1980’s 1990’s 2010’s
RF & SERDES IP re-use & DUT Master
Multiple Digital functions Logic, Memory & Analog
High speeds Digital non-determinism
Complex Timing Analog non-determinism
2008 Beijing Advanced Semiconductor Technology Symposium
2009-3-3
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5. IP re-use:
Design Engineer Heaven
Controller IP
DRAM
P
3000 Mbps SATA IP L
DDR
SRAM
L
533 -1600 Mbps
Cache IP
PCI P
5000 Mbps L
Express IP L
PLL
CPU
Controller IP
Core
USB2.0 P
480 Mbps IP x 2
L
DDR
533 -1600 Mbps
IP L
SDIO IP PLL
PLL
Low
JTAG IP Bus Interface
Speed 800 Mbps
IP
SPI IP
- Re-usable design IP allows designers to:
- Tape out full feature designs faster using Asynchronous IP that
speeds design time and chip timing closure
- Work with high level behavioral simulations, simplifying verification
of complex bus protocols
2008 Beijing Advanced Semiconductor Technology Symposium
2009-3-3
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6. IP re-use:
Test Engineer Hell
Controller IP
DRAM
P
3000 Mbps SATA IP L
DDR
SRAM
L
533 -1600 Mbps
Cache IP
PCI P
5000 Mbps L
Express IP L
PLL
CPU
Controller IP
Core
USB2.0 P
480 Mbps IP x 2
L
DDR
533 -1600 Mbps
IP L
SDIO IP PLL
PLL
Low
JTAG IP Bus Interface
Speed 800 Mbps
IP
SPI IP
- Test Engineers do not have re-usable TEST IP
- Protocol level simulations (event based) must be converted to
vectors (time based). Test engineers must debug with low level
vectors - ’01HLX’
- Asynchronous Interfaces cause non-determinism, which test
engineers must try to predict and adjust for in the vectors (may
shift with Process Variation)
6
2008 Beijing Advanced Semiconductor Technology Symposium
2009-3-3
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7. DUT and Tester Misalignment
• I/O buses use many different complex protocols and clocking
schemes
IP Re-use
• Multiple clock domains with no frequency relationship
DRAM
Controller IP
P
SATA IP
3000 Mbps L
SRAM
DDR
L
333/400/533 Mbps
Cache IP
=
PCI P
2500 Mbps L
• Asynchronously linked buses have independent PLLs per clock
Express IP L
CPU PLL
Core
Controller IP
USB2.0 P
480 Mbps L
DDR
IP x 2 333/400/533 Mbps
IP L
domain
SDIO IP PLL PLL
Low JTAG IP Bus Interface
800 Mbps
Speed SPI IP IP
• Behavior changes across Process, Voltage, and Temperature
(PVT) including shifts in timing, insertion of idle cycles, changes in
data order.
+
• Test development time is long because of differences between
Stored Response ATE DUT behavior in design and ATE
• Early silicon yield is reduced because good devices don’t match
ATE pass conditions
= • Test times are long because multiple pattern executions are
required looking for a pass or must capture/post-process
• Fault coverage is inadequate because DUT is not tested in
“Mission Mode” (end application)
2008 Beijing Advanced Semiconductor Technology Symposium
2009-3-3
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8. Protocol Aware ATE Applications
Potential Areas of Interest
Improve
Reduce Pgm
Early
Develop &
Silicon
Debug Time
Yield
Speed Up
Reduce
Silicon
Test Time
Debug
Protocol
Aware
ATE
Reduce Reduce or
Customer Eliminate
Return System
Debug Time Level Test
Improve
Fault Reduce DIB
Coverage Complexity
And DPM
Time to Production
Quality
Market Economics
2008 Beijing Advanced Semiconductor Technology Symposium
2009-3-3
8

9. Protocol Aware ATE Application:
Reduce or Eliminate System Level Test
Improve
Reduce Pgm
Early
Develop &
Silicon
Debug Time
Yield
Speed Up
Reduce
Silicon
Test Time
Debug
Protocol
Aware
ATE
Reduce Reduce or
Customer Eliminate
Return System
Debug Time Level Test
Improve
Fault Reduce DIB
Coverage Complexity
And DPM
Time to Production
Quality
Market Economics
2008 Beijing Advanced Semiconductor Technology Symposium
2009-3-3
9

10. Example of World-Class ASIC
ATE Test Fault Coverage
- At the 2007 VLSI
Test Symposium a
major ASIC vendor
(IBM) described fault
coverage for their
ASICs
- Stuck-at fault
coverage was very
high at >99% (DC-
Start and DC-end)
- Transition fault
coverage was lower at
84-87% (Scan, ASST,
TADT)
- No functional tests
IBM ASIC Fault Coverage – VLSI Test Symposium 2007
were performed
2008 Beijing Advanced Semiconductor Technology Symposium
2009-3-3
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11. Example of ASIC ATE Test Fault
Coverage Issues
- At the same conference a
major ASIC customer (Cisco)
described their experience
with ATE test escapes on
ASIC failures at system test
- Of the ASIC failures
identified at system test 68%
were attributed to ATE test
escapes
- Cisco attributed the high
percentage of ATE test
escapes to:
- Hard to emulate functional
environment with a standalone
chip
- Board functional tests run
Cisco ASIC Fault Coverage – VLSI Test Symposium 2007
different data from ATE ASIC BIST
2008 Beijing Advanced Semiconductor Technology Symposium
2009-3-3
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12. Cycle-based vs Protocol-based
Non-
deterministic
number of
skips and idles
Bench equipment is like programming in
ATE is like coding in machine language
assembly or high-level language
Characteristics of new interfaces
• Asynchronous
• Non-deterministic
• Interactive (needs some sort of handshaking, eg, speed negotiation, because they have to
be backward compatible)
2008 Beijing Advanced Semiconductor Technology Symposium
2009-3-3
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13. PCI Express(PCIE):
System Level Module Test Example
- Semiconductor manufacturer wants to test thru PCI Express port on ATE:
- Send commands to Device Under Test (DUT) through the PCIE port to set up registers
- Write and read back the register values across PCIE interface
- Send commands thru the PCIE port to set up internal loopback thru 1000BaseT ports
- Send data thru the PCIE interface and loop it back
- Check the data to verify that the entire chain is OK
- Instead they have to test in a separate System Level Test (SLT) insertion
- Separate System Level Test (SLT) insertion using 2 PC’s and a customized LAN card
- Throughput is much slower than ATE
- The SLTs are inexpensive but take up a lot of floor space
Customized LAN card
DUT in socket
Cat-5 cable 2nd PC
Processor/PCIE controller
PC motherboard
PCIE slot
2008 Beijing Advanced Semiconductor Technology Symposium
2009-3-3
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14. PCI Express(PCIE):
Desired ATE Setup
Device Internal loopback
DUT
ATE
1000BaseT
PCIE
ATE would need to:
1.Initiate and complete handshake to establish link
2. During subsequent exchange, handle low level link
layer/physical layer functions such as inserting “skips” (and
perhaps resending packets/commands) without user intervention
3. Designer would only need to provide “Payload Data” and the
tester would manage the link, just like CPU/PCIE controller
2008 Beijing Advanced Semiconductor Technology Symposium
2009-3-3
14

15. Protocol Aware ATE Application:
Speed Up Silicon Bring-up and Debug
Improve
Reduce Pgm
Early
Develop &
Silicon
Debug Time
Yield
Speed Up
Reduce
Silicon
Test Time
Debug
Protocol
Aware
ATE
Reduce Reduce or
Customer Eliminate
Return System
Debug Time Level Test
Improve
Fault Reduce DIB
Coverage Complexity
And DPM
Time to Production
Quality
Market Economics
2008 Beijing Advanced Semiconductor Technology Symposium
2009-3-3
15

16. Non-Deterministic DUT Behavior:
Cycle Slipping
SOC
Timing Timing
Ext
Domain Domain
ARM
DDR
Debug Async
Mem
#1 #2
Boundary
PROC I/F Bus
Port
PLL
PLL
Tester starts
Random Phase Alignment
in alignment
ATE T0 Reference
Debug Bus CMD
Tester T0 Ref
DDR Write (early)
DDR Write (nominal)
DDR Write (late)
Results may appear on DDR bus at any of several cycles.
Where do you place your strobe?
2008 Beijing Advanced Semiconductor Technology Symposium
2009-3-3
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17. Non-Deterministic DUT Behavior:
Asynchronous Memory BIST
ADDR
ADDR
BIST
BIST CTL
“Go!” CTL Control
Control Memory Memory
Data
Array Array
Data
ADDR
ADDR
BIST CTL
BIST Control
CTL
Control Memory Memory
Data
Array Array
Fault
Data
Fault
Packet
Packet
Fault Fault Fault Fault
Packet Packet Packet Packet
… … …
BIST Clock
Status
… … …
… … …
Fault Packets
How can you capture only the fault
packets across multiple memories?
2008 Beijing Advanced Semiconductor Technology Symposium
2009-3-3
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18. Silicon Debug:
Direct Register Read and Write
What you want to do! Device
Directly Read & Write device registers using Logic
Block
the same protocol as RTL and bench tests Device
Logic
JTAG
Write.jtag ( ADDR: 04h, DATA: 55h)
Block
Device
Or
Read.jtag (ADDR: 0Ah, DATA read_var) Register
Debug Device
File
IF
What you have to do! Logic
Block
Debug using ATE Patterns at a much Device
lower, bit oriented level: ’01HL’ Logic
Protocol Code Block
Device Protocol Transactions ATE Vectors Compression
- A single line of RTL becomes JTAG 1 74 98.65%
USB2.0 7 392 98.21%
multiple vectors as it is
MDIO 2 78 97.44%
translated into serial machine I2C 4 124 96.77%
cycles PCIE 12 256 95.31%
DDR2 4 20 80.00%
#of Vectors/PA Transactions for 1 x 32 bit register transfer
- ATE vectors are difficult to
debug, difficult to modify,
difficult to communicate to
design engineers
2008 Beijing Advanced Semiconductor Technology Symposium
2009-3-3
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19. Silicon Debug:
Patternless Test Generation
• Interactive sequences of Protocol frames can be strung together.
• Interactive Register Read/Write from Debug Environment
• For some protocols, no patterns are necessary (slower serial: MDIO, JTAG).
• Simulation RTL and bench tests are protocol specific
• Translation to ATE is still protocol specific. Debug occurs in protocol domain.
TheHdw.Protocol.Port.Enable “MDIOport,CLOCKport”
clk.Reset
mdio.Writec22 phy := 28, reg := 2, data := &HB57E ‘ Setup BIST Engine.
mdio.Writec22 phy := 28, reg := 3, data := &H5007
mdio.Writec22 phy := 29, reg := 1, data := &H0001 ‘ Start BIST Engine.
mdio.ReadUntilc22 phy := 20, reg := 8, data := &h0000 ‘ Wait for BIST to Stop (assuming a status word).
Dim result As SiteLong ‘ Read device test status.
result = mdio.Readc22 phy := 20, reg := 7
mdio.Stop
clk.Stop
TheExec.Flow.TestLimit result, lo := 0, hi := &H0030 ‘ Test result.
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2008 Beijing Advanced Semiconductor Technology Symposium
2009-3-3
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20. SOC ATE Digital Instrument:
Existing SOC Architecture
Standard SOC Digital Instrument
DSSC Pin Electronics
Host T
Logic T
Computer DUT
PE
Patgen Timing
Standard SOC Digital Instrument
• Appropriate voltage specs, and data rate
• Logic pattern generator with associated pattern memory
• Digital Signal Source and Capture
• Programmable edge timing
• Microcode control over analog and DC instruments
• Pattern execution controlled by Host Computer
2008 Beijing Advanced Semiconductor Technology Symposium
2009-3-3
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21. SOC ATE Digital Instrument:
Protocol Aware Architecture
Protocol Aware Digital Instrument
DSSC Pin Electronics
Host T
Logic T
Computer DUT
PE
Patgen Timing
Protocol Aware
Channels Select between normal PE
FPGA Based
operation and Protocol Engine
Protocol Aware Digital Instrument = Standard SOC Digital Instrument
PLUS
• Separate FPGA based Protocol Engines
• Separate memory for Protocol transactions
• Patgen and Host handshaking (start/done)
• Transaction execution from Host Computer, Job Program, or Transaction Memory
• Slow Serial Master (JTAG etc)
• RAM Emulation for DDR or Boot PROM
• Master/Slave operation
2008 Beijing Advanced Semiconductor Technology Symposium
2009-3-3
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22. First Generation Protocol Aware
ATE already exists
• Limited Protocol Aware ATE capability is available today
• A first generation Protocol Aware Instrument is the UltraFLEX SB6G
– Designed for at-speed test of High Speed Serial buses like PCI Express and SATA
– SB6G can recognize, manipulate, and compare 8b/10b encoded DUT output data up to 6.4Gbps
DUT Output Data SB6G Timing and Data Alignment Compare
Vector Data
6.4Gb/s Data Rate
Disparity &
Clock 10 bit 20 bit
Compare PRBS
Symbol Map
Data Align Match Auto-seed
RAM
Recovery
Capture for
Out-of Order
Data Compare
DUT output: Time align Data align Data manipulation Data align to - At-speed compare
8b/10b encoded to incoming to specific - Ignore Idles a specific two with stored pattern
data @ up to data 8b/10b - Map +/- disparity symbol - At-speed compare
6.4Gbps Symbol - Re-map symbols sequence
with PRBS pattern
Boundary
Protocol Aware Capability - Capture for later
compare with
Out-of-Order data
2008 Beijing Advanced Semiconductor Technology Symposium
2009-3-3
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23. The Future of ATE is Protocol
Aware
• Over Time ATE will become Protocol Aware, not just stored-response patterns
• Potential Protocol Aware ATE capabilities include:
– Transactional level software so design and test interact with the device at the same high
level of abstraction.
– Low latency DUT<-> ATE handshake to support higher level functions like memory
(RAM/Flash/ROM) emulation.
– Dealing with non-deterministic DUT behavior - timing shifts, idles, & out-of-order data
– Supporting at-speed functional test in device native operating mode (Mission Mode)
• Protocol Aware ATE can:
– Reduce test development time with transactional level ATE software
– Improve early silicon yield because ATE matches device Mission Mode
– Reduce test time by eliminating the need for capture and post-processing
– Increase fault coverage by testing devices in Mission Mode
– Reduce or eliminate the need for System Level Test and DIB Circuitry
2008 Beijing Advanced Semiconductor Technology Symposium
2009-3-3
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24. Protocol Aware ATE
Questions?
2008 Beijing Advanced Semiconductor Technology Symposium
2009-3-3
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