This document is a resume for Mohamed Yousef Abdulghany Elmasry that includes his contact information, objective, education history, related experience working as a senior hardware/logic design engineer and network design engineer, skills including expertise in VHDL, embedded software and hardware design, and recent projects involving designing hardware security cores, communication protocols, and embedded systems.

1. MOHAMED YOUSEF ABDULGHANY ELMASRY
Current: Exit no.9, Riyadh, Saudi Arabia, | Mobile: 00966-0546665027 Email: m.y.abdulghany@gmail.com
Home: T.V. Street, Luxor, Egypt, | Phone: 0020-0952276822
OBJECTIVE
To excel in a digital/hardware design position in which I can extend my knowledge, experience, and
skills.
EDUCATION
Faculty of Engineering, Elminia University, Elminia, Egypt
Bachelor in Electrical Engineering 2004
5 Years Degree in Electronics and Communication Engineering
Graduation Project: Design and Implementation of a Dynamic Instruction Set 16-bit Microprocessor
on FPGA. Grade achieved 198 out of 200.
Last Year Grade: 80.8 (Scale of 100)
Accumulative Grade: 73.96 (Scale of 100)
RELATED EXPERIENCE
ComSpots, Riyadh, KSA
Senior Hardware/Logic Design Engineer. August 2006 – Present
Develop and design embedded systems around FPGAs, soft processors, microcontrollers, and high
performance embedded processors. More information is available upon request.
Network Design Engineer, Telecom Egypt, Luxor City, Egypt
Design Engineer January 2005 – August 2006
Design, installation, and maintenance of telephone networks infrastructures.
Luxor Instruments, Luxor City, Egypt
Design Engineer May 2004 – January 2005
Design, installation, and maintenance of data networks and IT solutions in major tourism companies
and hotels.
SKILLS
Summary
Deep knowledge of microprocessor architecture including: low cost and simple 8-bit
microcontrollers, high performance and integrated 16-bit/32-bit embedded processors, and signal
processing optimized processors (DSPs).
Excellent knowledge and experience in using hardware description language (VHDL). I developed
many working and efficient hardware cores targeting Xilinx FPGAs. The cores list includes
cryptographic accelerators, peripherals like (UART, SPI, I2C, keypad scanners, LCD controllers, etc.),
digital controllers for power electronics applications like (Induction motor speed control, boost/buck
converters, fuzzy controller for solar power system, etc.), filters, and domain conversion processors
(FFT, DCT, etc).
Excellent experience in writing embedded software (Assembly & C). Most of my experience is in
using soft processors like MicroBlaze and PicoBlaze in conjunction with custom hardware cores.
Excellent experience in designing of digital/analog embedded system boards. My pervious designs
include high speed FPGAs, embedded processors, flash memories, SRAMs, DDR memories, USB
interface, Ethernet controllers, LCD, data converters, time keepers, etc. Boards include such
combinations of components need special care and skills in design of power distribution circuits.
Excellent experience in debugging and verification of complex logic designs using simulators and
typical debugging and verification techniques. Complex designs contain soft processors and different
set of peripherals implemented on FPGA requires carful verification and debugging in both RTL and
software.

2. MOHAMED YOUSEF ABDULGHANY ELMASRY PAGE 2
Excellent experience in defining rules and guidelines for high speed digital circuits’ layout and
routing. I used to apply signal integrity analysis using simulation tools and mathematical calculations
to avoid any signal integrity issues early in the design phase.
Hardware
Xilinx FPGAs.
Xilinx CPLDs.
Xilinx MicroBlaze 32-bit soft processor.
Xilinx PicoBlaze 8-bit microcontroller.
TI C2000, C5000 DSPs.
TI MSP430.
Stellaris Cortex-M3 ARM processors.
SPI, I2C, UART, USB, Ethernet, LCDs, Keypads, data converters (A/D, D/A), etc.
Memory interfacing and various memory technologies.
Board design and prototyping.
Switching power circuits design.
Hardware debugging using logic analyzers, scopes, and emulators.
Board testing, debugging, and board bring-up.
Software and Programming Skills
Windows operating systems (all)
Linux (basic skills)
Xilinx ISE, EDK, and ChipScope
Mentor FPGAdv, ModelSim, PadsLogic, HyperLynx
TI Code Composer Studio
Matlab
VHDL
Assembly
C & C++ (For embedded programming).
TCL scripting language
MFC (Microsoft Foundation Classes to build simple test applications)
RECENT PROJECTS (MORE INFORMATION AVAILABLE UPON REQUEST)
A True Hardware Random Number Generator IP for FPGA Designs
Description: The design uses the jitter noise in ring oscillators as a source of high quality and
high speed random numbers (RFC 4086, section 3.3, page 9) for cryptographic applications. The
design is employing several configurable de-skewing techniques including a Von-Neumann
corrector (RFC 4086, section 4.2, page 14). The design is configurable for
quality/performance/cost to fit with different design needs. The design has a simple and
configurable bus interface to be easily integrated into different applications.
Role: I was involved in the whole design process including:
Defining design requirements.
Evaluation of many researches in random number generation and selecting the most realistic
and applicable approach.
Design and implementation of selected approach using VHDL and target device.
Verification of design functionality.
Performing statistical tests on random numbers using NIST Statistical Tests Suit.
Optimization and modifications in the original approach to achieve better randomness
quality.
Design documentation.
High Speed Hardware Random Number Generator on a Small USB Stick
Description: The design uses a pre-designed hardware random number generator IP connected
to 8-bit microcontroller for data formatting and communication with host side, both
implemented on Xilinx FPGA. The design interfaced to host computer using a full-speed USB
controller. The design is low cost, high speed, and high quality solution for PKI systems,

3. MOHAMED YOUSEF ABDULGHANY ELMASRY PAGE 3
cryptographic software applications, and secure communications. This design stills one of core
products in the company.
Role: I was involved in the whole design process including:
 Defining design requirements.
 Design of board prototype.
 Design RTL coding using VHDL and target device.
 Verification of design functionality.
 Performing statistical tests on random numbers using NIST Statistical Tests Suit.
 Components selection and board design.
 Supervision of PCB design and manufacturing.
 Defining board verification methodology and implementing self-test design.
 Design of ISP tool.
 Help and supervision of host (PC) software design.
 Design documentation.
Tiny and FPGA Optimized Advanced Encryption Standard Core
Description: The target was to implement a small AES core (128-bit txt, and 256-bit key) to fit in
a small FPGA and complaint with NIST FIPS PUB 197 specifications. The design has a memory like
interface so it can be easily mapped to 8-bit, 16-bit, and 32-bit microcontrollers memory map.
Role: I was involved in the whole design process including:
 Defining design requirements.
 Evaluation of many researches in AES implementation using FPGA.
 Design of a target optimized architecture.
 Design and implementation of AES core using VHDL and target device.
 Verification of design functionality.
 Optimization and modifications to achieve better performance and less resources
requirements.
 Design documentation.
Tiny and FPGA Optimized Secure Hash Algorithm (SHA-512) Core
Description: The target was to implement a small SHA-512 core to fit in a small FPGA device and
provide a performance of tens of Mbits per second. The design is complaint with NIST FIPS PUB
180-2 specifications. The design has a memory like interface so it can be easily mapped to 8-bit,
16-bit, and 32-bit microcontrollers memory map.
Role: I was involved in the whole design process including:
 Defining design requirements.
 Evaluation of many researches in SHA implementation using FPGA.
 Design of a target optimized architecture.
 Design and implementation of SHA core using VHDL and target device.
 Verification of design functionality.
 Optimization and modifications to achieve better performance and less resources
requirements.
 Design documentation.
Multi-core Architecture for FPGA Designs
Description: The target of this design is to implement an efficient inter-processors architecture
and communication scheme to allow multi-cores design on FPGA. This design was the
cornerstone of subsequent designs. An example of this design is provided at the following link:
http://forums.xilinx.com/xlnx/board/message?board.id=PicoBlaze&thread.id=332.
Role: I was involved in the whole design process including:
 Defining design requirements.
 Implementation of design prototype.
 Design of system architecture.
 RTL design using VHDL.
 Verification of design functionality.
 Design documentation.

4. MOHAMED YOUSEF ABDULGHANY ELMASRY PAGE 4
Securing BRAM Content on Xilinx FPGA Designs
Description: A simple, reliable, and zero-cost approach to secure contents of BRAMs memory
inside Xilinx FPGA designs. An example of this design is provided at the following link:
http://forums.xilinx.com/xlnx/board/message?board.id=PicoBlaze&thread.id=344.
Role: I was involved in the whole design process including:
 Defining design requirements.
 Implementation of design prototype.
 Design of system architecture.
 RTL design using VHDL.
 Verification of design functionality.
 Design documentation.
Security Token
Description: This design implements a cryptographic library on a small USB stick. Tiny and
performance optimized cryptographic cores developed to fit in a small FPGA device and in very
small package. The design provide long list of services and features competing most of available
solutions in the market. The performance and security level of this design set a new standard in
security tokens designs. The interface to this design was done using a full speed USB controller.
The design integrates a set of pre-designed cryptographic IP cores together with a set of low
cost 8-bit microcontrollers in a single FPGA chip. The integration is done using a simple and
effective inter-processors communication scheme using mail boxes, interrupts, and control
flags. User data stored in SPI flash memory securely by storing the data encrypted using a
complex encryption algorithm. The host/device communication was secured using a customized
SSL technique. This device provides an excellent platform for software security, digital right
management, and PKI applications. This design stills one of core products in the company.
Role: I was involved in the whole design process including:
 Defining design requirements.
 Design of board prototype.
 Designing of modular system architecture.
 Design of inter-processor architecture which provide scalability, simplicity, modularity, and
efficiency.
 Writing, verification and optimization of RTL of inter-processor architecture.
 Design and verification of a unified and efficient inter-processor communication scheme
using assembly language.
 Design and verification of host/device communication protocol and frame format using
assembly language.
 Design and verification of each system function independently based on modularity,
simplicity and efficiency of inter-processor and design architecture. The design was done
using VHDL and/or assembly language.
 Design and verification of on-board security function.
 Design and verification of mutual (hardware/software) device authentication to prevent
design cloning.
 Design and verification of host/device communication SSL.
 Verification of design functionality.
 Components selection and board design.
 Supervision of PCB design and manufacturing.
 Defining board verification methodology and implementing self-test design.
 Design of ISP tool.
 Documenting host/device communication protocol, frame format, commands, responses,
error management and failure recovery.
 Help and supervision of host (PC) software design.
 Design documentation.
HF Radio Voice Scrambler
Description: An analog voice scrambler for public safety HF handheld radios. The scrambling was
done in analog domain based on AES encryption algorithm. An advanced terminals
synchronization technique adopted. The whole design was implemented using couple of low
cost AVR microcontrollers attached to special analog circuit.

5. MOHAMED YOUSEF ABDULGHANY ELMASRY PAGE 5
Role: I was involved in modeling of voice scrambling technique using Matlab and provide an
efficient model to be implemented using low cost 8-bit microcontroller and op-amps. Different
engineers involved in coding and board design.
AC Induction Motor Speed Control
Description: A closed loop controller implemented on FPGA to control the speed of AC induction
motor online using PWM techniques. LCD used to display various system parameters while in
operation.
Role: This was a research activity and not a commercial product. I was involved in the whole
design process including:
 Defining design requirements.
 Design and implementation of control system using assembly, VHDL and target device.
 Design and implementation of prototype board.
 Verification of design functionality.
 Design documentation.
A Fuzzy Logic Controller for Solar Power System
Description: This design implements FPGA hardware based FUZZY controller which controls the
operation of PV power system to work under the maximum power point operation conditions.
An equivalent software implementation written in C to allow comparison between
hardware/software implementation of the same logic in FPGA. The software implementation
runs on Xilinx MicroBlaze soft processor.
Role: This was a research activity and not a commercial product. I was involved in the whole
design process including:
 Defining design requirements.
 Design and implementation of control system using VHDL and target device.
 Design and implementation of control system using C and target device.
 Design and implementation of prototype board.
 Verification of design functionality.
 Performing performance and resources comparison between software and hardware
implementation.
 Design documentation.
Design of a General Purpose FPGA System Board
Description: The design objectives were to provide a general purpose Xilinx FPGA system board
with enough amounts of memory resources and IOs to work as the processing board in different
applications. The board designed with care to avoid any signal integrity problems due to fast
edges in FPGA signals. The board provides a wide number of FPGA configuration schemes to fit
with different designs needs. A couple of edge mounted high speed connectors used to expand
the board with sufficient number of IOs. The on-board RAM and flash memory sizes selected to
provide the enough code and data storage for MicroBlaze processor to operate well in future
planned designs. The board generates all needed voltage levels for proper FPGA operation using
on-board DC-DC regulators. A well designed power distribution circuit provided to achieve a
stable system over different operation conditions. The board designed to draw its power from a
wide range of input voltages to allow an easy integration with different systems. The on-board
regulators provide more than the enough current to operate the board in most demanding
applications, and to supply more than 2 A @ 3.3V through IOs connectors for external systems.
FPGA and memory subsystem designed in such a way to allow migration between multiple
devices in the same PCB layout and devices footprints.
Role: I was involved in the whole design process including:
 Defining design requirements.
 Selecting design components.
 Design of power conversion circuits.
 Design of FPGA and FPGA configuration subsystem.
 Design of memory and IOs subsystems.
 Defining and identification of high speed signals and associated parts/signals
placement/routing rules.
 Integration and optimization of design subsystems.

6. MOHAMED YOUSEF ABDULGHANY ELMASRY PAGE 6
 Drawing final design schematics.
 Sourcing of design components.
 Supervision of PCB design and manufacturing.
 Writing self test firmware for board diagnostics and troubleshooting.
Design of ISP tool.
 Help and supervision of host (PC) software design.
 Design documentation.
A Combined Modem Driver
Description: A set of high level APIs written in C to allow an easy integration of embedded
modems into Xilinx MicroBlaze designs. Xilinx provides a UART and GPIO components within
Xilinx EDK. In this driver a higher level layer implemented above and using Xilinx UART and GPIO
drivers. The layer combines the two drivers into a single driver with a set of advanced features.
A hardware/software flow control implemented in the new driver to allow smooth and robust
data streaming between MicroBlaze and embedded modem. Software queues provided to allow
bulk data transfer in interrupts driven systems. To allow the hardware flow control, a
modification introduced into the original Xilinx UART IP. The modification allow the software to
enable/disable UART receiver/transmitter which not possible in the original IP version.
Role: I was involved in the whole design process including:
 Defining design requirements.
Building design prototype.
 Modification to original Xilinx UART core and associated C driver.
 Writing and verification of combined modem driver in C.
 Doxygen compatible documentation of source code.
 Design documentation.
Configurable True Hardware Random Number Generator Core with PLB v4.6 Interface
Description: The design attaches a pre-designed true hardware random number generator
(TRNG) to a PLB v4.6 bus interface. The design targets MicroBlaze and/or PPC processors
implementations on Xilinx FPGAs. A set of configurable parameters made available to core user
through Xilinx EDK GUI. The design allows a configurable number of generated bits, de-skewing
techniques, and an integrated FIFO.
Role: I was involved in the whole design process including:
 Defining design requirements.
 Design RTL coding using VHDL and target device.
 Design of software driver in C language.
 Driver configuration scripts in TCL.
 Verification of design functionality.
 Doxygen compatible documentation of source code.
 Design documentation.
Configurable Advanced Encryption Standard Core with PLB v4.6 Interface
Description: The design attaches a pre-designed hardware advanced encryption standard (AES)
core complaint with NIST FIPS PUB 197 specifications to a PLB v4.6 bus interface. The design
targets MicroBlaze and/or PPC processors implementations on Xilinx FPGAs. A set of
configurable parameters made available to core user through Xilinx EDK GUI. The design allows
a configurable number of AES cores to be attached in parallel to a single PLB bus interface. This
allows higher performance through parallel processing in parallel hardware instances.
Role: I was involved in the whole design process including:
 Defining design requirements.
 Design RTL coding using VHDL and target device.
 Design of software driver in C language.
 Driver configuration scripts in TCL.
 Verification of design functionality.
 Doxygen compatible documentation of source code
 Design documentation.

7. MOHAMED YOUSEF ABDULGHANY ELMASRY PAGE 7
Configurable 512-bit Secure Hash Standard Core with PLB v4.6 Interface
Description: The design attaches a pre-designed hardware 512-bit secure hash standard (SHA-
512) core complaint with NIST FIPS PUB 182-2 specifications to a PLB v4.6 bus interface. The
design targets MicroBlaze and/or PPC processors implementations on Xilinx FPGAs. A set of
configurable parameters made available to core user through Xilinx EDK GUI. The design allows
a configurable number of SHA-512 cores to be attached in parallel to a single PLB bus interface.
This allows higher performance through parallel processing in parallel hardware instances.
Role: I was involved in the whole design process including:
 Defining design requirements.
 Design RTL coding using VHDL and target device.
 Design of software driver in C language.
 Driver configuration scripts in TCL.
 Verification of design functionality.
 Doxygen compatible documentation of source code
 Design documentation.
In-line FAX/Data Encryptor
Description: This project targets an end-to-end encryption module for FAX and Data
transmission over dial-up lines. The board includes two embedded FAX/Data modems with
many analog circuits around. The system controller was implemented on Xilinx FPGA device
(XC3S1400AN). A MicroBlaze soft processor used to handle all logical and transmission tasks
while some of PicoBlaze soft processors used to interface with keypad, LCD, RS232, and smart
card readers. An accessory interface could be used to connect the module with customer
property encryption algorithm implemented on a plug-in board.
Role: I was involved in the whole design process including:
Defining design requirements.
 Designing of modular system architecture.
 Building design prototype.
 RTL design using VHDL.
 Design of C/assembly firmware.
 Hardware/software verification.
 Board design.
 Defining and identification of high speed signals and associated parts/signals
placement/routing rules.
 Integration and optimization of design subsystems.
 Drawing final design schematics.
 Sourcing of design components.
 Supervision of PCB design and manufacturing.
 Writing self test firmware for board diagnostics and troubleshooting.
 Doxygen compatible documentation of source code.
Encrypted GSM/Dialup Phone
Description: This design provides a secure communication unit over GSM/dialup network. A
Xilinx FPGA device provides all needed control and processing functions. A soft processor (Xilinx
MicroBlaze) runs the main loop software and provides the intelligent behavior of the system.
On-board VOCODER chip from DVSI and a voice CODEC from TI used to compress digital voice
samples down to 2400~8000bps. The compressed voice encrypted using a hard AES IP (PLB v4.6
bus system used to attach all peripherals to system processor). Encrypted data sent to the other
party using GSM(CSD)/dialup data call, this is done using an embedded GSM/dialup modem. The
received data decrypted, passed to VOCODER for decoding and the decoded voice played back
using the CODEC chip. The system incorporates a number of well designed IP cores to interface
to VOCODER, MODEM, etc. Key exchange is done using a public key algorithm (RSA) and a true
hardware random number generator implemented on FPGA. The system has flexible user
configurable settings using KEYPAD and/or a USB interface. The system uses on-board chips IDs
to provide a robust design validation and authentication. The system designed on one base
board with the possibility to integrate a GSM modem or dialup modem to provide two different
possibilities of communication (only one can be integrated on the board). To minimize power
consumption a small Atmel AVR low power processor used for system power management. The

8. MOHAMED YOUSEF ABDULGHANY ELMASRY PAGE 8
unit can run from the battery (GSM mode) with standby time of 3 days and talk time (secure) of
up-to 8 hours.
Role: I was involved in the whole design process including:
 Defining design requirements.
 Building design prototype.
 Design of hardware interface between FPGA and VOCODER chip using VHDL. The interface to
the main processor done using a PLB v4.6 slave attachment.
 Writing and verification of VOCODER interface driver in C.
Memory subsystem interface and handling. This includes FPGA cores for memory interface
and firmware/drivers design in C.
User data management and security. This includes firmware and algorithms design in C.
Public key management system including FPGA accelerators, firmware/drivers in C, and
algorithms implementation in C.
 Doxygen compatible documentation of C source code.
Charger and power management circuits design. One adaptable power management circuit
designed for both modes (GSM or dialup).
 Design documentation.
Customization of Traffic Encryption Layer in a Radio Network
Description: This is a huge project in co-operation with many third parties including government
sectors, local contractors and multinational famous companies/vendors. Detailed information
associated with this project is subject to NDA and cannot be revealed.
Configurable Big-Integers Math Accelerator with PLB Interface Support
Description: This core provides on-chip accelerator for big integers (any bit size) math
operations ADD, SUB, MULTIPLY, and MOD. The core has very small footprint and excellent
performance and specially designed for constrained systems that require such acceleration for
public key cryptography applications. The core is configurable in terms of arguments size
(arguments for the math operations) and word size which used to access the core and it’s the
same as the internal data bus size used by the core. Increasing the word width will increase the
system performance and target resources consumption as well; however it’s an advantage for
resources rich platforms. The arguments size controls the storage (RAM) to be used by the core
to hold the arguments. Increasing arguments size has less effect on logic cells utilization but
increases the storage required by the core to hold the arguments while executing the math
operation. The design was optimized for embedded resources on Xilinx FPGAs (embedded
BRAMs, DSP slices, multipliers, etc.). The core has a PLB interface option to be used within Xilinx
EDK projects.
Role: I was involved in the whole design process including:
Optimum and efficient algorithms developing.
 Code optimized to be excellently mapped by the complier to on-chip embedded resources in
Xilinx FPGAs. Other vendors devices are supported with minor or no modifications.
 Configurable math arguments size and internal word size to tolerate for performance driven
or cost driven applications.
 Small footprint. Less than 300-slices, 1 multiplier (or 1 DSP slice) and only 2 BRAMs on a
Spartan-3 FPGA support 2048-bit add, sub, and multiply (multiply result 4096-bits)
operations plus 4096-bit MOD operation. Core is configured for 16-bit word size. The core
also supports automatic MOD after any of math operations without external intervention.
 With above configuration, the core may perform about 5000 multiplications in one second
@50MHz clock speed.
 Fully synchronize design able to work at speed behind 90 MHz on low cost Spartan-3 devices
(core configured with above configuration).
 Simplified RAM interface to external logic with 1 RST, 4 control, and 2 status signals.
 Optional input pointers to internal core memory to construct the core to operate on any
data stored inside the memory and return the result in any location inside the memory. This
enables application to perform more complex math operations using primitive operations
provided by the core with less arguments read/write from application side. As an example
one can add the arguments and multiply the result by one of the arguments without
intermediate read and write for the addition result.

9. MOHAMED YOUSEF ABDULGHANY ELMASRY PAGE 9
 Support to any input size between 0-bit and the configured maximum input size. As an
example, the core maybe configured for maximum input size of 2048-bits but it can operate
on 512-bits without the need to zero the most-significant 1536-bits of the inputs. In this case
the core consumes less cycles because it only operates on the least significant 512-bits and
ignores most significant bits.
 Support to non-equal arguments size. As an example, the core can perform 2048-bit by 130-
bit multiplication. By this the core consumes less cycles than considering full-size inputs and
zero most significant bits of the arguments.
 Smart MOD operation detects input arguments size and decreases the operation time by
performing less iterations for smaller arguments size. The MOD accelerator automatically
detects divide by ZERO (modules is 0) and generates an error output signal. Barrett
reduction employed to speed-up MOD operations for bigger input size.
 Xilinx EDK projects support with an optional PLB interface with highly configurable options
using a GUI based configuration appears in the same quality as GUI configuration for Xilinx
standard list of IPs.
 High level and advanced C driver for Xilinx EDK projects integration. The driver is very
modular and automatically configures itself according to hardware configurations. Special
TCL scripts written to do this static and automatic driver configuration in the system build
time.
 Full hardware documentation for internal core design and PLB bus interface.
 Full documentation for driver APIs. The driver documentation written in the same quality
and interface as documentation of standard Xilinx drivers and available from EDK GUI.
RSA Encryption Engine
Description: Based on advanced and optimized big-integers math accelerators, this core
provides on-chip RSA encryption-decryption (modular exponentiation). The core performs 2048-
bits RSA public key encryption in less than 2 seconds providing 1-kbps RSA speed supported by
custom accelerators and 1k instructions software running on 8-bit processor. The engine stores
all encryption keys in secure and encrypted memory (on-board). The design has a very small
footprint and consumes few logic resources. The design is able to work in autonomous mode
where it consumes the same amount of power and runs a fixed period regardless the weight of
encryption keys. This protects the design from possible power and time analysis attacks at the
expense of power consumption and performance. The whole design integrated as a part of
cryptographic processor implemented on a Xilinx FPGA device.
Role: I was involved in the whole design process including.
Remote Data Acquisition System
Description: Using an embedded GSM modem and a Cortex-M3 device, this design is an
advanced data acquisition system to be used in harsh environments. The design is highly
modular in terms of system configurability. The design consists of a stack of three boards, one
analog front-end board, one processing board, and one communication board. The roadmap for
this design is to alternate and design new analog and/or communication boards per system
requirements. The processing board consists of Stellaris Cortex-M3 processing running at 80
MHz as a core processor, Spartan-3A FPGA as IO expander and system cross-bar, 128-512Mbit
parallel NOR flash, USB interface, SPI flash for firmware and settings storage, keypad interface,
graphical LCD interface, RTC, temperature sensor, DC-DC converters for front-end power and
board level power. The analog board has Spartan-3A FPGA, differential and instrumentation
amplifiers, programmable gain amplifiers, solid state relays, optical isolators, 12-bit SAR analog
to digital converters, isolated/non-isolated DC-DC converters for board level power. The analog
board will be application dependent and new analog boards will be designed for future
expansions and applications. The communication interface for first design is an embedded GSM
modem with GPRS support. The design should log information to remote application server
using TCP/IP channel. SMS and CSD are optional or backup communication methods. Ethernet,
unlicensed RF, and FOC are planned.
Role: I was involved in the whole design process including.

10. MOHAMED YOUSEF ABDULGHANY ELMASRY PAGE 10
PUBLICATIONS AND PAPERS
"A Novel Digital Implementation of AC Voltage Controller for Speed Control of Induction Motor"
International Conference on Power Electronics and Power Engineering, Paris, France, June 24-26,
2009. 2009
"A Novel Digital Implementation of AC Voltage Controller for Speed Control of Induction Motor"
Int. J. Power and Energy Conversion, Vol. 2, No. 1, 2010. 2010
"Digital implementation of general purpose fuzzy logic controller for photovoltaic maximum power point tracker"
20th International Symposium on Power Electronics, Electrical Drives, Automation and Motion, 2010,
Italy. 2010
LANGUAGES
Arabic – native language
English – speak fluently and read/write with high proficiency (TOEFL iBT Score 90) 2009
REFRENCES
Available upon request.
PERSONAL INFORMATION
Nationality: Egyptian
Date of birth: 1/1/1982
Gender: Male
Marital Status: Single
Military Status: Exempted
SUMMARY OF QUALIFICATIONS
Self-starter, team player and have excellent leadership. Organizational, communication, analytical, and problem solving skills.