10. 10
FPGAっていつ有用なの?
10G if
DRAM
Network
adapter
FPGA
Network stack Memcached
x86 DRAM
motherboard
Hash table Value store
図は https://www.usenix.org/sites/default/files/conference/protected-files/blott_hotcloud13_slides.pdf より
データはどうせ移動させる
移動途中で副次的に処理できる
✔ Memcached部分はデータフローアーキテクチャ
✔ レイテンシ = 481Cycles@156MHz
38. 38
Synthesijer でのHDL生成: 例題
package blink_led;
public class BlinkLED {
public boolean led;
public void run(){
while(true){
led = true;
for(int i = 0; i < 5000000; i++) ;
led = false;
for(int i = 0; i < 5000000; i++) ;
}
}
}
39. 39
Synthesijer でのHDL生成: 大枠
class
entity blink_led_BlinkLED is
port (
clk : in std_logic;
reset : in std_logic;
field_led_output : out std_logic;
field_led_input : in std_logic;
field_led_input_we : in std_logic;
run_req : in std_logic;
run_busy : out std_logic
);
end blink_led_BlinkLED;
class BlinkLED {
public boolean led;
public void run(){
while(true){
…
}
}
}
module
クラス毎にHWモジュールを生成
43. 43
Synthesijer でのHDL生成: 状態遷移
状態遷移機械に相当するステートマシンをベタに作る
always @(posedge clk) begin
if(reset == 1'b1) begin
run_method <= run_method_IDLE;
run_method_delay <= 32'h0;
end else begin
case (run_method)
run_method_IDLE : begin
run_method <= run_method_S_0000;
end
run_method_S_0000 : begin
run_method <= run_method_S_0001;
run_method <= run_method_S_0001;
end
run_method_S_0001 : begin
if (run_req_flag == 1'b1) begin
run_method <= run_method_S_0002;
end
end
run_method_S_0002 : begin
if (tmp_0003 == 1'b1) begin
run_method <= run_method_S_0004;
end else if (tmp_0004 == 1'b1) begin
run_method <= run_method_S_0003;
end
end
run_method_S_0003 : begin
...
47. 47
たとえば
public void test(){
boolean success = false;
int a = 10;
int b = 20;
int c = 0;
int d = 40;
int e = 50;
int f = 0;
int g = 70;
int h = 80;
int i = 0;
int j = 100;
int k = 110;
int l = 0;
c = a + b;
f = d + e;
i = g + h;
l = j + k;
c = c + f;
l = l + i;
c = c + l;
if(c == 10+20+40+50+70+80+100+110) success = true;
boolean success2 = check(c);
}