02 architecture

Microprocessor
8086 Architecture

Eng. Mustafa H. Salah
Mechatronics Engineering
University for Electronic Technology

Bus interface

Microprocessor 8086 Architecture
Unit BIU
Execution Unit Fetches
EU Opcodes, Read
Operands, Write
Data

-

-

BIU Bus interface Unit •

"EU« (Execution Unit ) •

Data Bus •
Address Bus •
Control signals Bus • -

Bus Interface Unit

BIU

Segment registers •
Address Adder •
Instruction Queue •

-

Execution Unit

ALU •

Flag or Statues Register •
General Purpose Registers •
Temporary Registers •
EU control System •

-

EU
EU

EU
BIU
EU
BIU

-

Bus
DATA BUS •
bit

ADDRESS BUS •

bit

CONTROL BUS •

-

Data Bus BIU •

Control Bus Address Bus

BIU •

Instruction queue

First In

FIFO first Out -

BIU

BIU
EU

EU
CPU

•
•

-


Registers

CSR,DSR,SSR,ESR •

SI,DI,BP,SP •
AX,BX,CX,DX •
IP •

-

Segment Registers
2 Bytes 16 bit

Code Segment Register CSR .1

Data Segment Register DSR .2

-

Stack Segment Register SSR .3

Extra Segment Register ESR .4

-

00000h

15 0
CS
CS
DS

64 KB
DS
SS
ES SS

ES -

FFFFFh

DS
Source Index Register SI

-


Destination Index Register DI

ES

DI

-

Stack Pointer Register SP

SP

SP SS

-

SS
Base Pointer BP

-


AX Accumulator

BX Base

CX Count

DX Data
-

AL

BH
H,L
X

L

H

-


-


IP
Instruction Pointer IP

BIU

-


Status (Flags) Register

11 10 9 8 7 6 4 2 0
OF DF IF TF SF ZF AF PF CF

CF, PF, AF, ZF, SF, OF

DF, IF, TF -

Reset
Set

Carry Flag (CF)

-


7

CF=1
CF=1

-


1
7
CF=1

-


Parity Flag (PF)

PF

-


Auxiliary Flag (AF)

AF=0
AF=1

-


7
AF=0

-


Zero Flag (ZF)

-


Sign Flag (SF)

Reset
Set

SF
SF
SF

-


OF
Overflow Flag (OF)

-


CF

ZF=1

-


Trap Flag (TF)

Interrupt Flag (IF)

-

Direction Flag (DF)

-


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