Vivado/SDAccel Design Contest Seminar
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The document announces a Vivado/SDAccel design contest to be held on January 11th. Teams of up to two members can enter. Winners will be selected to attend conferences in Dublin in September 2018 and San Francisco in May 2022. The document also provides information on heterogeneous complex systems using FPGAs from Amazon, IBM, Microsoft and others. It discusses the basic components of FPGAs, including configurable logic blocks, lookup tables, I/O blocks and interconnections. Finally, it covers the evolution of FPGA design environments and tools over time towards higher levels of abstraction and automation.
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Vivado/SDAccel Design Contest Seminar
- 1. Vivado/SDAccel Design Contest 11 Jan, 2018 Seminar Room @ DEIB Marco D. Santambrogio <marco.santambrogio@polimi.it> Politecnico di Milano
- 3. Project Example: Vivado/SDAccel Design Contest • Team: up to 2 members per entry/participation • Opening: 1.3 • Closing: 3.4 • Winners will be selected for – attending FPL@Dublin(Sept 2018) – (Joining NECST Group Conference @ San Francisco (22.5-2.6)) 3
- 4. Heterogeneous Complex Systems • Amazon EC2 F1 Instances – Xilinx UltraScale Plus FPGA – https://aws.amazon.com/about-aws/whats-new/2017/04/amazon-ec2-f1- instances-customizable-fpgas-for-hardware-acceleration-are-now-generally- available/ • IBM Power8 – Introducing the Coherent Accelerator Processor Interface (CAPI) port that is layered on top of PCI Express 3.0 – http://www-304.ibm.com/webapp/set2/sas/f/capi/home.html • OpenPower Foundation – http://openpowerfoundation.org/ • Microsoft Catapult – Stratix V (Arria 10 FPGA) – http://research.microsoft.com/en-us/projects/catapult/ • Ryft ONE – Big Data infrastructure due to an FPGA-accelerated architecture – http://www.ryft.com/ 4
- 6. Field-Programmable Gate Arrays • Configurable Logic Blocks – to implement combinational and sequential logic 6 CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB
- 7. LookUp Tables: LUTs • LUT contains Memory Cells to implement small logic functions • Each cell holds ‘0’ or ‘1’ . • Programmed with outputs of Truth Table • Inputs select content of one of the cells as output 7 O = f(D, C, B, A) OMUX BACD LUT 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
- 8. Field-Programmable Gate Arrays • Configurable Logic Blocks – to implement combinational and sequential logic • I/O blocks – special logic blocks at periphery of device for external connections 8 CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB
- 9. Field-Programmable Gate Arrays 9 • Configurable Logic Blocks – to implement combinational and sequential logic • I/O blocks – special logic blocks at periphery of device for external connections • Interconnections – wires to connect Inputs/Outputs to configurable logic blocks CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB
- 10. Xilinx FPGA and Configuration Memory 10 FPGA
- 11. Xilinx FPGA and Configuration Memory 11 Configuration Memory FPGA
- 12. Xilinx FPGA and Configuration Memory 12 Configuration Interfaces Configuration Memory FPGA
- 13. Xilinx FPGA and Configuration Memory 13 Configuration Interfaces Configuration bitstream Configuration Memory FPGA
- 15. Reconfiguration in everyday life Football (Complete – Static) 15
- 17. Reconfiguration in everyday life Soccer Football (Complete – Static) (Partial – Static) 17
- 19. Reconfiguration in everyday life Soccer Football (Complete – Static) (Partial – Static) 19
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