1. Storage Interfaces
SATA

2. 2
Where ATA Resides in the PC Architecture
CD
HD
SATA
SATA

3. 3
History of Parallel ATA
Generation Standard Year Speed Key features
IDE 1986 Pre-standard
ATA 1994
PIO modes 0-2, multiword
DMA 0
EIDE ATA-2 1996 16 MB/sec
PIO modes 3-4, multiword
DMA modes 1-2, LBAs
ATA-3 1997 16 MB/sec SMART
ATA/ATAPI-4 1998 33 MB/sec
Ultra DMA modes 0- 2,
CRC, overlap, queuing, 80-
wire
Ultra DMA 66 ATA/ATAPI-5 2000 66 MB/sec Ultra DMA mode 3-4
Ultra DMA 100 ATA/ATAPI-6 2002 100 MB/sec
Ultra DMA mode 5,
48-bit LBA
Ultra DMA 133 ATA/ATAPI-7 2003 133 MB/sec Ultra DMA mode 6

4. 4
• Bandwidth limited to 133 MB/s
• Cyclic Redundancy Checking (CRC) for data but not commands
• Support attachment of 2 devices per cable
• Small switch or jumper for drive selection
• High pin count on signaling interface adds cost to cables,
connectors and components
• Wide cables are cumbersome and inhibit airflow making cooling
more difficult and expensive
• Connectors hard to insert and remove
• Prone to bent pins
Limitations of Parallel ATA

5. 5
Benefits of Serial Based Storage
• Frame-based transaction protocol (OSI model)
– Small, inexpensive connectors and cables
• Legacy support - ATA stack in SATA
• Ease of integration – cabling, jumpers
• Point-to-point connections (expanders, port multipliers)
• Pathway to higher data rates; 6 Gb/s is on the roadmap
• Improve bandwidth
– Wide ports permit several simultaneous connections,
allowing for link aggregation (SAS)
• Lower cost

6. 6
PATA and SATA Comparisons
Source: SATA Working
Group

7. 7
History of serial ATA
Generation Standard Year Speed Key features
Serial ATA ATA/ATAPI-7 2002 150 MB/sec
Serial ATA II ATA/ATAPI-8 2005 300 MB/sec Native Command
Queuing
Serial ATA III ATA/ATAPI-9? ? 600 MB/sec

8. 8
SATA Technology Today
• SATA has been the most successful recent new storage interface
– It has been a multi billion dollar market for several years
– In 2006 over 300 million hard disk drives will have SATA interfaces
• 400 Million Shipped in 2005 (source: Gartner)
– Market Leader – Seagate 40% share
– SATA has also made its appearance in solid state disks, DVD drives and
tape drives
• In Desktop, notebooks, Consumer Products - DVR
• In the Enterprise! (thanks to STP)
– Challenges SAS in the enterprise
– Non-critical data
– Near-line and offline storage
– FC, SAS, and SATA will co-exist offering consumers with a choice of
flexible storage options at varying price-points

9. 9
SATA Layer Architecture

10. 10
SATA Layer Architecture

11. Connectivity
• Serial ATA is point-to-point topology
– Hosts can support multiple devices but requires
multiple links
– 100% available link bandwidth
– Failure of one device or link does not affect other
links

12. Link Characteristics
• SATA uses full-duplex links
– Protocol only permits frame transfer in one
direction at a time
– Each link consists of a transmit and a receive pair
• SATA uses low voltage levels
– Nominal voltage +/-250mV differential

13. Power Management
• SATA has
– Phy Ready – Capable of sending and receiving data. Main
phase locked loop are on and active
– Partial – Physical layer is powered but in a reduced state.
Must be able to return to Phy Ready within 10 us.
– Slumber – Physical layer is powered but in a reduced state.
Must be able to return to Phy Ready within 10 ms.
• ATA also defines IDLE, STANDBY, and SLEEP
• Necessary for newer laptop & mobile devices

14. SATA Architectural Model
Device Control Software
Buffer Memory
DMA management
Serial digital transport control
Serial digital link control
Serial physical interface
Device Layers
Host Control Software
Buffer Memory
DMA management
Host Layers
Serial digital transport
control
Serial digital link control
Serial physical interface
Application
Transport
Link
Physical

15. 15
Physical Layer - Summary
• Defines the connectors and cabling used to
transmit and receive SATA signaling and data
information

16. 16
Physical Layer - SATA Device Connector
Serial ATA
signal
connector
(pin S1)
Appearance of Serial ATA Connectors
(Drawing courtesy of Molex)
parallel ATA signals 4-pin power
3.5”
Parallel
power signal
2.5"
Serial
Device connector sizes and locations
Device plug
connector
Host receptacle
connector
power signal
3.5”
Serial
Legacy Power
(vendor specific)
Serial ATA
power
connector
(pin P1)
(5.25” form factor also defined for
devices like tape drives and DVDs)
in comparison…
Graphics courtesy of the SCSI Trade Association
and HP

17. 17
Physical Layer - SATA Cabling
Graphics courtesy of
Molex
SATA to SATA
(1), CO, ST
The most
common
internal for
SATA (and
SAS); 1 meter
maximum
length
SATA Power
To provide
legacy power
support
eSATA Power
(2m)
External SATA;
designed for
use with
external
storage
products;
bypasses the
USB route

18. 18
Physical Layer - Summary
• OOB (Out of Band) Signaling
• Speed Negotiations
• Byte/dword synchronization

19. 19
Phy Layer - (OOB)
• Most primitive level of communication is OOB
• They are pattern of idle times and burst times, distinguished
by length of time between idles
– Idle time (and negation time) are when there are voltage levels
• Also known as DC idle
– Burst time is during the transmission of the ALIGN primitives
– Since byte sync has not occurred yet, the actual bits sent are not
relevant – 40 bits will always been detected and consider an ALIGN

20. 20
Phy Layer - (OOB)
• COMINIT/COMRESET and COMWAKE are bursts of 6 ALIGN (0) separated by
IDLEs
• Length of the idle time determines the type of OOB signal
• Senders sends 6 – receiver only need to detect 4 (per spec)
• COMRESET are sent by hosts
• COMINIT are sent by devices
OOB Signal Idle Time Negation Time
COMWAKE 55 to 175 ns > 175 ns
COMINIT/COMRESET 175 to 525 ns > 525 ns

21. 21
Phy Layer - OOB COMWAKE

22. 22
Phy Layer - OOB COMINIT/COMRESET
Electrically, COMINIT and COMRESET appear exactly the same, the only
difference is the direction in which the ALIGN patterns are being sent. Host to
device: COMRESET; device to host: COMINIT

23. 23
SATA Power-On Initialization
• Starts with the assertion of hardware reset
• Begins Out-Of-Band (OOB) signaling
• Allows host and device to initialize link
communications
• Ends with successful transmission of ALIGN
primitives
• Then speed negotiations

24. 24
Power-On Initialization Process
Host Device

25. 25
SATA Power-On Initialization

26. 26
Error Situation
Example: Host and Device are unable to establish a
connection. Continuous transmission errors are seen from
both the Host and Device.
No COMINITs present. Indicates problem with
Device connection

27. 27
Primitive Handshaking
Sender Receiver
X_RDY
R_RDY
SOF
Frame
.
.
.
EOF
R_IP
R_OK
WTRM

28. 28
Primitive Handshaking
Example: Host sends commands but commands
are not completed
Trace indicates that Host is not properly handling
primitive handshaking and is not receiving frames

29. 29
SATA Speed Negotiation
• Fast to slow progression
– SATA target device sends ALIGN primitives at the
fastest supported rate
– Waits for host to reply with ALIGNs
– If no reply after sending 2048 (i.e., the host
doesn’t support this speed), step down to next
slower speed and try again

30. 30
SATA Speed Negotiation
• When host replies with ALIGNs, it has locked at the current
frequency and negotiation is complete
Speed Negotiation

31. Out of Band
• Part of normal power on sequence
• Allows host to issue a device hard reset
• Allows device to request a hard reset
• Brings device out of low power state

32. Out of Band Signals (cont.)
• COMWAKE
– Can be originated by either host or device
– Used as final phase of OOB initialization
– Used to bring out of low power & test states
• Exit Partial
• Exit Slumber
• Exit BIST

33. Out of Band Signal Forms
COMRESET / COMINIT
COMWAKE
106.7 ns
106.7 ns 106.7 ns
320 ns

34. Out of Band Signaling Protocol
Host Device

35. SATA Port Model
Clock & Data
Recovery
Serializer
Deserializer
AnalogFrontEnd
OOB Detect
COMRESET /
COMINIT
COMWAKE
Data Out
RX Clock
Port Control
Logic
Tx Clock
Align Generator
Data In
Phy Reset
Phy Ready
Slumber
Partial
SPD Mode
System Clock
SPD Select
Tx +
Tx -
Rx -
Rx +

36. SATA Architectural Model
Device Control Software
Buffer Memory
DMA management
Serial digital transport control
Serial digital link control
Serial physical interface
Device Layers
Host Control Software
Buffer Memory
DMA management
Host Layers
Serial digital transport
control
Serial digital link control
Serial physical interface
Application
Transport
Link
Physical

37. Link Layer
• 8b / 10b encoding
• Scrambles and descrambles data and control
words
• Converts data from transport layer into frames
• Conduct CRC generation and checking
• Provides frame flow control

38. Encoding Concepts
• All 32 bit Dwords are encoded for SATA
– 32 bits data = 40 bits of transmission
• Provides sufficient transition density
– Guarantees transition (0s and 1s) even if data is
0x00 or 0xFF
• Provides an easy way to detect transmission
error

39. Current Running Disparity (CRD)
• As each character is encoded a count is maintained
of the number of 0’s and 1’s being transmitted
– More 1’s than 0’s give positive disparity
– More 0’s than 1’s gives negative disparity
– Same number gives neutral disparity
• Only valid values of CRD are -1 and 1
– Any other value indicates that a transmission error has
occurred

40. CRD+ & CRD- Encoded Characters
0 0 1 1 1 1 1 1
1 0 1 0 1 1 1 0 0 1 0 1 0 1 0 0 1 0 0 1
8b Character 0x3F
This 10b Character transmitted when
CRD negative
This 10b Character transmitted when
CRD positive
This character
6 ones
4 zeros
Disparity +2
This character
4 ones
6 zeros
Disparity -2

41. SATA Primitives
• Convey real-time state information
• Control transfer of information between host
and device
• Provide host/device coordination

42. SATA Primitives
• ALIGN – Speed negotiation and at least every
256 Dword
• SYNC – Used when in idle to maintain bit
synchronization
• CONT – Used to suppress repeated primitives

43. SATA Primitives
• X_RDY
• R_RDY
• R_IP
• R_OK
• R_ERR
SOF
EOF
HOLD
HOLDA

44. SATA Frame Structure
• All SATA frames consist of:
– A start of frame (SOF) delimiter
– A payload – transport layer information
– A Cyclic Redundancy Check (CRC)
– An end of frame (EOF) delimiter
SOF CRC EOFPayload Data

45. Link Layer Protocol (1)
SYNCSYNCSYNCSYNCSYNCSYNC
SYNC SYNCSYNCSYNCSYNCSYNC
Host Device

46. Link Layer Protocol (2)
SYNCSYNCX_RDYX_RDYX_RDYX_RDY
SYNC SYNCSYNCSYNCSYNCSYNC
Host Device

47. Link Layer Protocol (3)
X_RDYX_RDYX_RDYX_RDYX_RDYX_RDY
SYNC R_RDYR_RDYR_RDYR_RDYSYNC
Host Device

48. Link Layer Protocol (4)
X_RDYX_RDYSOFDATADATADATA
R_RDY R_RDYR_RDYR_RDYR_RDYR_RDY
Host Device

49. Link Layer Protocol (5)
DATADATADATADATADATADATA
R_RDY R_IPR_IPR_IPR_IPR_RDY
Host Device

50. Link Layer Protocol (6)
DATADATACRCEOFWTRMWTRM
R_IP R_IPR_IPR_IPR_IPR_IP
Host Device

51. Link Layer Protocol (7)
CRCEOFWTRMWTRMWTRMWTRM
R_IP R_IPR_IPR_IPR_IPR_IP
Host Device

52. Link Layer Protocol (8)
WTRMWTRMWTRMWTRMWTRMWTRM
R_IP R_OKR_OKR_OKR_OKR_IP
Host Device

53. Link Layer Protocol (9)
WTRMWTRMSYNCSYNCSYNCSYNC
R_OK R_OKR_OKR_OKR_OKR_OK
Host Device

54. Link Layer Protocol (last)
SYNCSYNCSYNCSYNCSYNCSYNC
R_OK SYNCSYNCSYNCSYNCR_OK
Host Device

55. SATA Architectural Model
Device Control Software
Buffer Memory
DMA management
Serial digital transport control
Serial digital link control
Serial physical interface
Device Layers
Host Control Software
Buffer Memory
DMA management
Host Layers
Serial digital transport
control
Serial digital link control
Serial physical interface
Application
Transport
Link
Physical

56. Transport Layer
• Responsible for the management of Frame
Information Structures (FIS)
• At the command of Application layer:
– Format the FIS
– Make frame transmission request to Link layer
– Pass FIS contents to Link layer
– Receive transmission status from Link layer and
reports to Application layer

57. Frame Information Structure (FIS)
• A FIS is a mechanism to transfer information
between host and device application layers
– Shadow Register Block contents
– ATA commands
– Data movement setup information
– Read and write data
– Self test activation
– Unique FIS Type Code

58. FIS types
FIS TYPE
CODE
Description Direction
27h Register transfer host to device H D
34h Register transfer device to host D H
A1h Set Device bits D H
39h DMA Activate D H
41h DMA Setup D H
58h BIST Activate D H
5Fh PIO Setup D H
46h Data D H

59. Register – Host to Device FIS
Byte 3 Byte 2 Byte 1 Byte 0
Dword 0 Features Command Reserved FIS TYPE
(27h)
Dword 1 Dev/Head Cyl High Cyl Low Sector
Number
Dword 2 Features
(exp)
Cyl High
(exp)
Cyl Low
(exp)
Sector
Number
Dword 3 Control Reserved Sector
Count
Sector
Count
Dword 4 Reserved Reserved Reserved Reserved

60. BIST Activate FIS
Byte 3 Byte 2 Byte 1 Byte 0
0 Reserved [ TASLFPRV ] Reserved FIS Type 58h
1 Data [31:24] Data [23:16] Data [15:8] Data [7:0]
2 Data [31:24] Data [23:16] Data [15:8] Data [7:0]
T - Far end transmit only – transmit Dwords defined in words 1 & 2
A - No ALIGN transmission (valid only with T)
S - Bypass scrambling (valid only with T)
L - Far end retimed loopback with ALIGN insertion
F - Far end analog loopback
P - Transmit primitives defined in words 1 & 2 of the FIS
R - Reserved
V - Vendor Unique Test Mode – other bits undefined

61. Data FIS
Byte 3 Byte 2 Byte 1 Byte 0
Dword 0 Reserved Reserved Reserved FIS TYPE
(46h)
Dword 1
N Dwords of Data
Minimum 1 Dword
Maximum 2048 Dwords
Dword 2
. . .
Dword N

62. SATA Architectural Model
Device Control Software
Buffer Memory
DMA management
Serial digital transport control
Serial digital link control
Serial physical interface
Device Layers
Host Control Software
Buffer Memory
DMA management
Host Layers
Serial digital transport
control
Serial digital link control
Serial physical interface
Application
Transport
Link
Physical

63. Command / Application Layer
• Defined using a series of state diagrams
– Register H  D
– Register D  H
– DMA data in
– DMA data out
• Host command layer may be the same but
may only support legacy commands

65. Compatibility SATA
• PCI SATA controller card
• Windows 2000/XP/2003/Vista
• Integrated SATA CRC on both levels of
command and data packets