3. Functional block Diagram
• INPUT OUTPUT (I/O) DEVICE
I/P :Key board, scanner, card reader etc
O/P : Display, printer LED etc
• MEMORY
RAM, ROM
• MICROPROCESSOR
Central Processor Unit ( CPU ) include
ALU, Timing & control unit for synchronizations
5-Mar-14
Prof.Nitin Ahire
3
4. Number System
• Decimal number system (DNS)(10)
0,1,2 ……,9,10
• Binary number system(2)
0,1,10,11,100
• Hexadecimal number system (16)
0,1,2,…..,9,A,B,C,D,E,F,10,11
• Advantages of Hex No over BCD No system
(1111 1111)2
(FF)16
(255)10
5-Mar-14
Prof.Nitin Ahire
4
5. Review for Logic Devices
• Tri State Devices :
3 States are logic 1, logic 0 & high
impedances state ( Z )
Enable
Active high
Enable
Active Low
5-Mar-14
Prof.Nitin Ahire
5
6. Tri-State Buffers
• An important circuit element that is used
extensively in memory.
• This buffer is a logic circuit that has three
states:
– Logic 0, logic1, and high impedance.
– When this circuit is in high impedance mode it
looks as if it is disconnected from the output
completely.
The Output is Low
The Output is High
High Impedance
6
7. The Tri-State Buffer
• This circuit has two inputs and one output.
– The first input behaves like the normal
input for the circuit.
– The second input is an “enable”.
• If it is set high, the output follows the proper
circuit behaviour.
• If it is set low, the output looks like a wire
connected to nothing.
Input
Output
Enable
OR
Input
Output
Enable
7
8. Review for Logic Devices
• Buffer e.g. 74LS244(unidirectionl) & 74LS245(Bidirection)
• Buffer is a logic CKT that amplifies the current or
power
• It has one I/P line and one O/P line
• The logic level of O/P is the same as that of the
I/P
• Basically used as to increase the driving capacity
of logic CKT
simple buffer
5-Mar-14
Active low buffer
Prof.Nitin Ahire
8
9. D – F/F (Latch)
Q
clk
I/P
I/P
D F/F
clk
Q
5-Mar-14
O/P
Prof.Nitin Ahire
9
10. Introduction to 8085
• CPU built into a single semiconductor
chip is called as microprocessor
• The microprocessor work as a brain
of a computer
• It consist of ALU, registers and
control unit
• The microprocessor are usually
characterized by speed, word length
(bit), architecture, instruction set Etc
5-Mar-14
Prof.Nitin Ahire
10
11. 8085 Features
• 8085 is a 8-bit processor
• Frequency of operation
a) 8085 --- 3Mhz
b) 8085-2 --- 5Mhz
c) 8085-1 --- 6Mhz
• 8085 has 16 bit address bus to access
memory
• 8 bit address bus to access I/O
location
5-Mar-14
Prof.Nitin Ahire
11
12. 8085 Features
• It required only single +5V power supply
• 8085 has following registers
a) 8 bit accumulator
b) six 8- bit general purpose registers
c) 8-bit flag register
d) 16 –bit PC and SP
• It has 5 hardware and 8 software interrupt
• 8085 required 6 Mhz crystal
• It can transmit and receive serial data
5-Mar-14
Prof.Nitin Ahire
12
14. X1
Serial I/O
ports
X2 vcc
SID
CLK CKT &
P.S.
H.O.A.B
A8-A15
SOD
AD0- AD7
TRAP
Externally
Initiated
Signal
RST 7.5
RST 6.5
RST 5.5
INTR
READY
ALE
8085
Functional
Pin Diagram
HOLD
5-Mar-14
S0
S1
Control &
Status
Signal
IO/M
RD
WR
RESET IN
External
Acknowledge
Signal
Multiplexed
A/D Bus
INTA
CLK OUT
HLDA
Prof.Nitin Ahire
RESET OUT
14
15. INTA RST 7.5 to 5.5
TRAP
SID
SOD
INTR
P.S
+5V
GND
Serial I/O Control
Interrupt control
8 bit Internal BUS
MUX
W8
I.R. 8
F/F 5
ALU
8
Inst.
Decoder
&
M/C
Encoder
DECODRE
Accumulator 8 Temp. Reg
Z8
B
C
D
E
H
L
SP 16
PC 16
Internal latch
CLK OUT RESET IN RESET OUT
X1
Timing and control unit
A/D. Buffer
Add. Buffer
X2
READY
WR RD ALE S0 S1Prof.Nitin Ahire HOLD
IO/M HLDA
5-Mar-14
AD0-AD7
A15-A8
15
16. INTA RST 7.5 to 5.5
TRAP
SID
SOD
INTR
P.S
+5V
GND
Serial I/O Control
Interrupt control
8 bit Internal BUS
MUX
I.R. 8
F/F 5
ALU
8
Inst.
Decoder
&
M/C
Encoder
DECODRE
Accumulator 8 Temp. Reg
8
W8
B
Z8
C
D
E
H
L
SP 16
PC 16
Internal latch
CLK OUT RESET IN RESET OUT
X1
Timing and control unit
A/D. Buffer
Add. Buffer
X2
READY
WR RD ALE S0 S1Prof.Nitin Ahire HOLD
IO/M HLDA
5-Mar-14
AD0-AD7
A15-A8
16
17. Registers
• The register contains a set of
binary storage cells/Flip Flop
• 6 general purpose 8 bit Reg.
B,C,D,E,H&L (or can be used as
pair of 16 bit reg. like BC,DE,HL)
• W & Z (Temp reg.)
• 16 bit Reg are PC And SP
• 8 bit flag register
5-Mar-14
Prof.Nitin Ahire
A
F
B C
D E
H L
SP
PC
17
19. Interrupts
• 8085 has 5 hardware interrupts
8 software interrupts
• All software interrupt are vectored
• Out of 5 hardware interrupt 4 are
vector and 1 is non vector
also 4 are maskable and one is non
mask able
5-Mar-14
Prof.Nitin Ahire
19
20. De multiplexing Of AD0-AD7
ALE
Latch
AD0-AD7
A0-A7
8085
D0-D7
IO/M
A8-A15
5-Mar-14
Prof.Nitin Ahire
20
21. De multiplexing Of AD0-AD7
ALE
AD0-AD7
Latch A0-A7
8085
IO/M
D0-D7
5-Mar-14
Prof.Nitin Ahire
21
24. Flags Register ( 8 bit )
S
D7
Z
D6
--
AC
D5
D4
• S –sign flag
P
D3
D2
--
D1
C
D0
(for signed number)
if D7=1 the number in accumulator
will be –ve number
D7=0 the number in accumulator
will be +ve number
• Z – zero flag
5-Mar-14
if D6=1The zero flag is set if the result
in accumulator is zero
Prof.Nitin Ahire
24
25. Flags Register ( 8 bit )
S
D7
Z
D6
AC
D5
D4
P
D3
D2
C
D1
D0
AC –
Auxiliary carry in the arithmetic operation, when the carry
is generated digit D3 and passed on digit D4 the AC flag is set
P–
parity flag after an arithmetic and logical operation, if the
result has even number of ones the flag is set if it has odd
numbers of ones, the flag is reset
CY –
Carry flag if an arithmetic operation results in carry, the
carry flag is set otherwise it is reset. The carry flag also serves as
a barrow flag for subtraction
5-Mar-14
Prof.Nitin Ahire
25
26. Subtraction process in 8085
• 1 : find 1‟s complement of the subtrahend
• 2 : find 2‟s complement of the subtrahend
• 3 : Adds 2‟s complement of the
subtrahend to the minuend
• 4 : complements the CY flag.
These steps are invisible to the user, only
the result is available to the user.
For unsigned number if CY is reset the result
is positive and if CY is set the result is
negative(2‟complement)
5-Mar-14
Prof.Nitin Ahire
26
27. Sign flag (used only for sign No.)
• Sign flag: This flag is used with signed
numbers in the arithmetic operation.
With sign number, bit D7 is reserved
for indicating the sign and the
remaining 7 bit are used to represent
the magnitude of a number
• Sign flag is irrelevant for unsigned
number
5-Mar-14
Prof.Nitin Ahire
27
28. Instruction, Data format
and storage
• Part of instruction each instruction has
two parts
1 opcode: one is the task to be perform
(operational code)
2 operand: data to be operated on
(data)
The data can be specified in the various
form it may in the memory or I/O or in
the instruction it self.
5-Mar-14
Prof.Nitin Ahire
28
30. DATA BUS
Internal Data BUS
MEMORY LOCATION
B C
(A)
D E
INST.
DECODER
H L
SP
CONTROL
LOGIC
DECODER
ALU
3E
20
67
12
4F
2000
2001
2002
2003
2004
PC (2000)
ADD BUS
MERD
3E
5-Mar-14
Prof.Nitin Ahire
30
31. DATA BUS
Internal Data BUS
MEMORY LOCATION
B C
(A)
D E
INST.
DECODER
3E
H L
SP
CONTROL
LOGIC
DECODER
ALU
3E
20
67
12
4F
2000
2001
2002
2003
2004
PC (2001)
ADD BUS
MERD
20
5-Mar-14
Prof.Nitin Ahire
31
32. DATA BUS
Internal Data BUS
MEMORY LOCATION
B C
(A)
D E
INST.
DECODER
H L
20
SP
CONTROL
LOGIC
DECODER
ALU
3E
20
67
12
4F
2000
2001
2002
2003
2004
PC (2002)
ADD BUS
MERD
67
5-Mar-14
Prof.Nitin Ahire
32
33. DATA BUS
Internal Data BUS
MEMORY LOCATION
B C
(A)
D E
INST.
DECODER
H L
20
SP
CONTROL
LOGIC
DECODER
ALU
3E
20
67
12
4F
2000
2001
2002
2003
2004
PC (2003)
ADD BUS
MERD
12
5-Mar-14
Prof.Nitin Ahire
33
34. DATA BUS
Internal Data BUS
MEMORY LOCATION
B C
(A)
D E
INST.
DECODER
H L
20
SP
CONTROL
LOGIC
DECODER
ALU
3E
20
67
12
4F
2000
2001
2002
2003
2004
PC (2004)
ADD BUS
MERD
4F
5-Mar-14
Prof.Nitin Ahire
34
35. Instruction classification
• “Instruction” is a command to the
microprocessor to perform a given task
on specified data”.
• The instruction can be classified into
following fundamental categories
1 Data transfer
2 Arithmetic & Logical operation
3 Branching operation
4 Machine control operation
5-Mar-14
Prof.Nitin Ahire
35
36. Instruction classification
• 1 Data transfer (copy)
basically used to copies data from source
to destination without modifying the
content of the source like,
Opcode operand
MOV
rd, rs
MVI
r, 8-bit
IN
8 bit port add.
OUT
8 bit port add.
5-Mar-14
Prof.Nitin Ahire
36
38. Instruction classification
• Arithmetic operation
These instruction perform arithmetic
operation such as addition
subtraction, increment, decrement.
• ADD R
• ADI data
• ADC R
• ADC M
• ACI data
• DAD Rp
5-Mar-14
Prof.Nitin Ahire
38
41. Instruction classification
• Logical instruction.
These instruction perform various logical
operation with the content of the
accumulator
e.g. 1) AND,OR,EX-OR(ANA R,ANI Data)
2) Rotate (RAL,RAR,RLC,RRC)
3) Compare (CMP B,CPI Data)
4) Complement (CMC, CMA,STC)
5-Mar-14
Prof.Nitin Ahire
41
42. Instruction classification
• Branching operation
These group of instruction alter the
sequence of program execution
either conditionally or unconditionally
e.g. JUMP (conditionally or unconditionally)
CALL & RET (conditionally or unconditionally)
5-Mar-14
Prof.Nitin Ahire
42
43. Instruction classification
• Machine control instruction
These instruction control the machine
function such as Halt (HLT),
interrupt (RST 1) or do noting (NOP)
5-Mar-14
Prof.Nitin Ahire
43
44. Addition of two 8 bit number
(30H + 40H)
LXI H, C200H; load HL pair by C200h
MOV A,M; Move 1st No. in the Reg. A
INX H ; increment the HL pair by 1
ADD M; Add A+(M)=A
INX H; increment the HL pair by 1
MOV M,A; move the result in M
HLT; Stop
5-Mar-14
Prof.Nitin Ahire
44
45. Subtraction of two 8 bit
number (10H-05H)
LXI H, C200H; load HL pair by C200h
MOV A,M ;Move 1st No. in the Reg. A
INX H; increment the HL pair by 1
SUB M ; Subtract A-(M)=A
INX H ; increment the HL pair by 1
MOV M,A ; move the result in M
HLT ; Stop
5-Mar-14
Prof.Nitin Ahire
45
46. Addition of two 16 bit
number ( 1234H+4321H )
LHLD C200H ;
XCHG
;
LHLD C202H ;
DAD D
;
SHLD C204H ;
HLT
;
5-Mar-14
Here L=34, H=12
exchange HL with DE
Here L= 21, H=43
DE+HL = HL
store the result
stop
Prof.Nitin Ahire
46
47. Write a program to transfer a block of data from C550H
to C55FH. Store the data from C570H to C57FH .
LXI H ,C550H
LXI B ,C570H
MVI D,0FH
UP MOV A,M
STAX B
INX H
INX B
DCR D
JNZ UP
RST1
5-Mar-14
Prof.Nitin Ahire
47
48. Minimum mode system(8085)
VCC
A0-A15
X1
A8-A15
ALE
X2
RESET OUT
AD0-AD7
RESET IN
TRAP
RST 7.5
RST 6.5
RST 5.5
INTR
74
LS
373
D0-D7
A0-A7
8
0
8
5
Memory
INTA
READY
SOD
SID
5-Mar-14
MERD
IO/M
RD
WR
I/O
74
LS
138
MEWR
IORD
IOWR
Prof.Nitin Ahire
48
49. Instruction classification
• The 8085 instruction set is classified
into the following 3 group according
to word size or byte size
1) 1- byte instruction
2) 2- byte instruction
3) 3 –byte instruction
5-Mar-14
Prof.Nitin Ahire
49
50. 1- byte instruction
• A 1- byte instruction includes the
opcode and the operand in the same
byte
e.g. Opcode operand hex code
1 MOV
C, A
(4F) (opcode)
2 ADD
B
(80) (Data)
each instruction required 1 memory
location ( 8-bit)
5-Mar-14
Prof.Nitin Ahire
50
51. 2- byte instruction
• In the 2- byte instruction the first byte
specifies the operation code and the
second byte specifies the operand
e.g. Opcode operand hex code
MVI
A, 12H
3E (opcode)
12 (Data)
These instruction required 2 memory
location
5-Mar-14
Prof.Nitin Ahire
51
52. 3- byte instruction
• In 3-byte instruction the first byte specifies the
opcode and the following 2 bytes specify the 16bit address
e.g. Opcode operand hex code
LDA 2050
3A
(Opcode)
50
(Data)
20
(Data)
Note the second byte is the lower address and the
third byte is the high order address
These instruction required 3 memory location
5-Mar-14
Prof.Nitin Ahire
52
53. Addressing mode
• The different methods (mode) to select
the operands (address) are called
addressing mode
• For 8085 they are
1 Immediate addressing
2 Register addressing
3 Direct addressing
4 Indirect addressing
5 Implied addressing
5-Mar-14
Prof.Nitin Ahire
53
54. Addressing mode
1 Immediate addressing
In the immediate addressing mode the
data is specified in the instruction it self.
The immediate addressing mode
instruction are either 2- byte or 3- byte
long.
The instruction contain the letter “I”
indicate the immediate addressing mode.
e.g. 1 MVI A,12h
2 LXI H,2000h
5-Mar-14
Prof.Nitin Ahire
54
55. Addressing mode
2 Register addressing mode
In register addressing mode the source
and destination operands are general
purpose registers
The register addressing mode instructions
are generally of 1 –byte
e.g.
5-Mar-14
1 MOV A,B
2 ADD B
3 PCHL
Prof.Nitin Ahire
55
56. Addressing mode
3 Direct addressing
In the direct addressing mode the
16 bit address of the data or operand
is directly specified in the instruction
These instruction are 3 –byte
instruction.
e.g. 1 LDA 2000h
2 STA 2060h
5-Mar-14
Prof.Nitin Ahire
56
57. Addressing mode
4 Indirect addressing
In the Indirect addressing mode the
instruction reference the memory
through the register pair i.e. the
memory address where the
operand/data is located is specified
by the register pair
e.g.1 MOV A,M
2 LDAX B
5-Mar-14
Prof.Nitin Ahire
57
58. Addressing mode
5 Implied addressing
• The Implied mode of addressing does not
required any operand
• The data is specified within the opcode itself
• Generally these instructions are 1-byte
instruction
• The data is supposed to be present in the
Accumulator
e.g. 1 RAL
2 CMC
5-Mar-14
Prof.Nitin Ahire
58
59. Timing diagram
• For better understanding of each
instruction it is very essential to
understand the Timing diagram of
each instruction.
• The graphical representation of each
instruction with respective to time i.e.
CLOCK is called “Timing Diagram”
5-Mar-14
Prof.Nitin Ahire
59
60. Timing diagram
• Instruction cycle (IC) : The essential step
required by CPU to fetch and execute an
instruction is called IC
IC=FC+EC
• Machine cycle (MC) : Time required by
microprocessor to complete the operation
of accessing memory or I/O device is
called MC.
• T –state :Each clock cycle is called T-state
5-Mar-14
Prof.Nitin Ahire
60
61. Timing diagram
•
•
•
1.
2.
3.
4.
5.
5-Mar-14
The µP operates with reference to clock signal.
The rise and fall of the pulse of the clock gives
one clock cycle.
Each clock cycle is called a T state and a
collection of several T states gives a machine
cycle.
Important machine cycles are :
Op-code fetch.
Memory read.
Memory write.
I/O-read.
I/O write.
Prof.Nitin Ahire
61
63. Timing diagram
• Step 1 (State T1) In the state, 8085 sends
the status signals, IO/M=0, S1=1 and S0=1
• The 8085 send a 16 bit address on A8-A15
and AD0-AD7
• The high order bytes of PC is placed on the
A8-A15 lines, and it remain there upto T3
state. The low order bytes of PC placed on
the AD0-AD7,lines which remain there only
for T1
• During this state, ALE gives a positive pulse
signal is used to latch the add A0-A7.
• No control signal is generated in state.
5-Mar-14
Prof.Nitin Ahire
63
64. Timing diagram
• Step2(T2): The content of PC lower will
disappear on AD0-AD7 lines, so the same
line can be used as data line . The
contents of A0-A7 are still available for
memory from external Latch.
• The control signal RD is made low by the
processor which enables the read ckt of
addressed memory device.
• Then the memory device send the content
on the data bus AD0-AD7
• In addition to these the processor
increments PC content by one
5-Mar-14
Prof.Nitin Ahire
64
65. Timing diagram
• Step3(T3): during this cycle the data
from memory (opcode) is transfer in
the instruction Reg. and RD control
signal made HIGH
5-Mar-14
Prof.Nitin Ahire
65
66. Timing diagram
• Step 4 (T4): the microprocessor
perform only internal operation.
The opcode decoded by the CPU and
8085 decide
1) Whether it should enter T5 and T6
states or not
2) How my bytes of instruction it is?
If instruction doesn‟t required T5 &T6
states, it go to the next MC
5-Mar-14
Prof.Nitin Ahire
66
67. Timing diagram
• Step 5 (T5 &T6): T5 and T6
states, states are required to
complete decoding and some
operations inside the 8085 it depend
on the type of instruction
5-Mar-14
Prof.Nitin Ahire
67
70. Timing diagram
• Following instruction required T5 & T6 states for
the opcode fetch MC
1 CALL
2 CALL conditional
3 DCX Rp
4 INX Rp
5 PCHL
6 SPHL
7 PUSH Rp
8 RET conditional
All other instruction except the above instruction
required opcode fetch of T1 to T4 states only.
5-Mar-14
Prof.Nitin Ahire
70
71. Stack control and branching group
• Stack is the reserved area of the
memory in RAM where temporary
information may be stored
• Stack pointer (SP): an 16-bit SP is
used to hold the address of the most
recent stack entry. It work on the
principle of LIFO or FILO.
5-Mar-14
Prof.Nitin Ahire
71
72. Stack Related Instructions
• LXI SP,16-bit address
• PUSH Rp
• POP RP
• SPHL ( HL
SP)
• XTHL ( HL
SP)
• PCHL ( HL
PC)
5-Mar-14
Prof.Nitin Ahire
72
73. Stack Related Instructions
• PUSH B
Let BC=3010, B=30h, C=10h
suppose SP initialized at FFFF h
after execution of instruction PUSH B
SP=SP-1=FFFF-1=FFFE
B
[FFFE] =30h
again SP=SP-1=FFFE-1=FFFD
C
[FFFD]=10h
SP=[FFFD]
5-Mar-14
Prof.Nitin Ahire
73
74. Stack Related Instructions
• POP B
initially B=20, C=40h
SP at=[FFFD]=10h
at=[FFFE]=30h
After execution of POP B
SP=[FFFD]=10h
[C]
SP=SP+1=[FFFE]=30h
[B]
Again SP=SP+1=[FFFF]
Now B=30h, C=10h and SP=[FFFF]
5-Mar-14
Prof.Nitin Ahire
74
75. Subroutines
• Whenever we need to use a group of
instruction several times throughout
a program there is a way we can avoid
having to write the group of instructions
each time we want to use them.
• one way is to write the group of
instruction separately, Called Subroutines
• whenever we want to execute that group
of instruction we can call that Subroutine.
• The return address has to be stored back
on the stack memory
5-Mar-14
Prof.Nitin Ahire
75
76. Subroutines
e.g
6FFF
31
LXI SP, FFFFh
7000
CD
CALL C200h
7001
00
7002
C2
7003
Next instruction
When this instruction is executed PC contents
7003h (next instruction) will stored on to
the stack and microprocessor will load PC
with C200h and start executing instruction
from C200h
5-Mar-14
Prof.Nitin Ahire
76
77. Subroutines
• If SP= FFFF h
• CALL C200.
(SP-1)=Pc H
(SP-2)=Pc L
SP=SP-2
PC=new C200
5-Mar-14
PC
70
Prof.Nitin Ahire
stack (memory)
FFFF
03
70 FFFE
03 FFED
77
78. Subroutines
• Conditional Call instructions
When condition is true, then CALL at NEW address
else execute the next instruction of the program
1) CZ Add
2) CNZ Add
3) CP Add
4) CM Add
5) CPO Add
6) CPE Add
7) CC Add
8) CNC Add
If condition false 9T True16T
5-Mar-14
Prof.Nitin Ahire
78
79. Subroutines
• RET unconditionally
1 SP
(PC L)
PC
Stack
2 SP+1
(PC H)
70 03
3 SP+2=SP
70
03
FFFF
FFFE
FFFD
Initially SP at FFFD
After execution of RET SP=FFFF
5-Mar-14
Prof.Nitin Ahire
79
80. Subroutines
• RET conditionally
When condition is true, then RET at the main
program
1) RZ
2) RNZ
3) RP
4) RM
5) RPO
6) RPE
7) RC
8) RNC
5-Mar-14
Prof.Nitin Ahire
80
81. Nested Subroutines
• Whenever one subroutine calls
another subroutine in order to
complete a specific task, the operation
is called as nesting. The First
subroutine may call the second
subroutine and in turn the second
subroutine may called first or third
subroutine such routines called
NESTED subroutines
5-Mar-14
Prof.Nitin Ahire
81
83. Nested Subroutines
• There are two kinds of subroutines
1) Re-entrant subroutines.
2) Recursive subroutines.
5-Mar-14
Prof.Nitin Ahire
83
84. Re entrant Subroutines
1)Re-entrant Subroutine
It may happened a Subroutine „1‟ is
called from main program and „2‟
Subroutine is called from Subroutine
„1‟ and Subroutine „2‟ may called
Subroutine „1‟ then the program
re entrant in Subroutine „1‟ this is
called re-entrant Subroutine
5-Mar-14
Prof.Nitin Ahire
84
86. Recursive subroutine
• A procedure which called it self is
called a recursive subroutine
• The recursive subroutine loop takes
long time to execute
• In this type of subroutine we
normally define N ( recursive depth)
it is decrement by one after each
subroutine is call until N=0
5-Mar-14
Prof.Nitin Ahire
86
88. Software Delay
• Delay : operating after an some
time interval.
• Microprocessor take fixed amount of
time to execute each instruction
• Microprocessor driven by fixed
frequency (crystal)
• So using instruction we can generate
a Delay.
5-Mar-14
Prof.Nitin Ahire
88
89. Software Delay
• E.g. delay using NOP instruction
NOP ( 1-byte instruction- 4T state)
assume crystal freq= 4Mhz..
CLK freq = 2Mhz
(T=0.5 microsecond)
Delay using NOP = 4 X 0.5 microsecond
= 2.0 microsecond
5-Mar-14
Prof.Nitin Ahire
89
90. Software Delay
• If we want the more delay than
4T,then we go on increasing NOP after
NOP.
• Impractical (size of program increase)
5-Mar-14
Prof.Nitin Ahire
90
91. Delay using 8 –bit counter
Delay
Initializes 8-bit counter
Decrement counter
No
yes
RET
5-Mar-14
Prof.Nitin Ahire
91
92. Delay using 8 –bit counter
•
MVI C, Count
7T
up: DCR C
4T
JNZ :up
10T/7T
RET
10T
The loop is executed ( count-1 ) times
5-Mar-14
Prof.Nitin Ahire
92
93. Delay using 8 –bit counter
• Formula for delay value
Td=[ M + {(count) X N} -3 ] T
M=No. of T state out side the loop
N=No. of T state inside the loop
M=10+7=17 T; N=10+4=14T
5-Mar-14
Prof.Nitin Ahire
93
94. Delay using 8 –bit counter
JNZ instruction required 10 or 7 T state
based on the condition ( Z=0 or 1)
(when condition is satisfied it take
10T state and if not satisfied it take 7T
state)
so 3 T must be subtracted from total
value
5-Mar-14
Prof.Nitin Ahire
94
95. Delay using 8 –bit counter
• Td max=
=
=
=
[17+[ {255} X 14 ] -3] T
3584 T
3584 X 0.5 microsecond
1792 microsecond
(FF)=(255)
5-Mar-14
Prof.Nitin Ahire
95
96. Delay using 16 bit counter
•
LXI B, (count)H 10T
up: DCX B
6T
MOV A,C
4T
ORA B
4T
JNZ
:up
10/7T
RET
10T
DCX not affect the zero flag.
5-Mar-14
Prof.Nitin Ahire
96
97. Delay using 16 bit counter
Td=[ M + {(count) X N} -3 ] T
M=No. of T state out side the loop
N=No. of T state inside the loop
M=20 T; N=24T
5-Mar-14
Prof.Nitin Ahire
97
98. Delay using 16 bit counter
• Td max= [20+[ {65535}X 24 ] -3] T
= 1572857 T
=1572857 X 0.5 microsecond
= 78642 microsecond
(FFFF)=(65535) largest count.
5-Mar-14
Prof.Nitin Ahire
98
99. Memory and I/O interfacing
• Types of memory
1 ROM (EPROM)
2 RAM
5-Mar-14
Prof.Nitin Ahire
99
100. Memory structure & it‟s
requirement's
I/P decoder
• The read write
memories consist A0
of an array of
A1
registers, where in
each register has a
unique address
• M=No. of register
AM
• N=No. of bits
Data i/Ps
I/P Buffer
WR
MXN
O/P Buffer
RD
CS
5-Mar-14
Prof.Nitin Ahire
Data o/p s
100
101. Memory structure & it‟s
requirement's
• If the memory having 13 address
line and 8 data lines, then it can
access 213 address lines = 8192
and N= 8 bit or 1-byte
• No of address lines of the „up‟ is to
be used to find how much memory
array can be access by that
processor.
5-Mar-14
Prof.Nitin Ahire
101
102. No. of address line
required to accessed the memory
• No of lines
1
2
3
4
10
11
16
5-Mar-14
size of memory
21= 2
22= 4
23= 8
24 =16
210= 1K= 1024
211 =2K= 2048
216 =64K= 65536
Prof.Nitin Ahire
102
103. EPROM IC available in the
market
IC NO
2716
2732
2764
27128
27256
27512
5-Mar-14
size
2k X 8
4k X 8
8k X 8
16k X 8
32K x 8
64k X 8
Prof.Nitin Ahire
103
104. RAM IC available in the
market
IC NO
6116
6264
62512
2114
5-Mar-14
size
2k X 8
8k X 8
64k X 8
1k X 4
Prof.Nitin Ahire
104
105. Comparison between full
and partial decoding
• full decoding
• partial decoding
1) Also referred to be as
absolute decoding
2) All address lines are
consider
3) More hardware
required
1) Also referred to be
as liner decoding
2) Few address lines are
ignored
3) Decoder hardware is
simple
5-Mar-14
Prof.Nitin Ahire
105
107. Memory and I/O interfacing
• Types of memory
1 ROM (EPROM)
2 RAM
5-Mar-14
Prof.Nitin Ahire
107
108. Memory structure & it‟s
requirement's
I/P decoder
• The read write
memories consist A0
of an array of
A1
registers, where in
each register has a
unique address
• M=No. of register
AM
• N=No. of bits
Data i/Ps
I/P Buffer
WR
MXN
O/P Buffer
RD
CS
5-Mar-14
Prof.Nitin Ahire
Data o/p s
108
109. Memory structure & it‟s
requirement's
• If the memory having 13 address
line and 8 data lines, then it can
access 213 address lines = 8192
and N= 8 bit or 1-byte
• No of address lines of the „up‟ is to
be used to find how much memory
array can be access by that
processor.
5-Mar-14
Prof.Nitin Ahire
109
110. No. of address line
required to accessed the memory
• No of lines
1
2
3
4
10
11
16
5-Mar-14
size of memory
21= 2
22= 4
23= 8
24 =16
210= 1K= 1024
211 =2K= 2048
216 =64K= 65536
Prof.Nitin Ahire
110
111. EPROM IC available in the
market
IC NO
2716
2732
2764
27128
27256
27512
5-Mar-14
size
2k X 8
4k X 8
8k X 8
16k X 8
32K x 8
64k X 8
Prof.Nitin Ahire
111
112. RAM IC available in the
market
IC NO
6116
6264
62512
2114
5-Mar-14
size
2k X 8
8k X 8
64k X 8
1k X 4
Prof.Nitin Ahire
112
113. Comparison between full
and partial decoding
• full decoding
• partial decoding
1) Also referred to be as
absolute decoding
2) All address lines are
consider
3) More hardware
required
1) Also referred to be
as liner decoding
2) Few address lines are
ignored
3) Decoder hardware is
simple
5-Mar-14
Prof.Nitin Ahire
113
114. 8085 Memory Interfacing
•
Generally µP 8085 can address 64 kB of memory .
•
Generally EPROMS are used as program memory and RAM as
data memory.
•
We can interface Multiple RAMs and EPROMS to single µP .
•
Memory interfacing includes 3 steps :
1. Select the chip.
2. Identify register.
3. Enable appropriate buffer.
5-Mar-14
Prof.Nitin Ahire
114
116. 8085 Memory Interfacing
• Address lines A0-A10 are used to interface memory
while A11,A12,A13,A14,A15 are given to 3:8 Decoder
to provide an output signal used to select the
memory chip CS¯or Chip select input.
• MEMR¯ and MEMW¯are given to RD¯and WR¯pins
of Memory chip.
• Data lines D0-D7 are given to D0-D7 pins of the
memory chip.
• In this way memory interfacing can be achieved.
5-Mar-14
Prof.Nitin Ahire
116
120. Interrupt system of 8085
• Definition: “It is a mechanism by
which an I/O device ( Hardware
interrupt) or an instruction (software
interrupt) can suspend the normal
execution of the processor and get it
self serviced.”
5-Mar-14
Prof.Nitin Ahire
120
122. Hardware interrupt
• Interrupt : “It is an external
asynchronous input that inform the
„up‟ to complete the instruction that
it is currently executing and fetch a
new routine in order to offer a
service to that I/O devices. Once the
I/O device is serviced, the „up‟ will
continue with execution of its normal
program.”
5-Mar-14
Prof.Nitin Ahire
122
124. Types of Hardware interrupt
• NMI( non maskable)
• Maskable
1) It can‟t be masked or
1) It can be masked or
made pending
made pending
2) Highest priority
3) This interrupt disable 2) Lower priority
all maskable interrupts 3) These interrupt dose
not disable non
4) Used for emergency
maskable interrupt
purpose like power
failure, smoke detector 4) Used to interface
e.g. TRAP
peripherals.
e.g. RST 7.5
5-Mar-14
Prof.Nitin Ahire
124
127. Software interrupt
• These instruction ( RST0-RST7) allow
the „up‟ to transfer the program
control from main program to the
subroutine program (i.e. ISR)
ISR: interrupt service routing
5-Mar-14
Prof.Nitin Ahire
127
128. Software interrupt
Interrupt
RST 0
RST 1
RST 2
RST 3
RST 4
RST 5
RST 6
RST 7
5-Mar-14
Restart locations
0 X 8 = 0000h
1 X 8 = 0008h
2 x 8 = 0010h
3 X 8 = 0018h
4 X 8 = 0020h
5 X 8 = 0028h
6 X 8 = 0030h
7 X 8 = 0038h
Prof.Nitin Ahire
128
129. Software interrupt / hardware
interrupt
• Hardware interrupt
• Software interrupt
1)It is an asynchronous
1)It is as synchronous event event
2)This interrupt is requested 2)This interrupt is
requested by external
by executing instruction
device
3)PC is incremented
3)PC is not incremented
4)The priority is highest
4)The priority is lower
than softer interrupt
5)It can‟t be ignored
6)It is not used to interface 5)Can be masked
6)It is used to interface
the peripheral
peripheral devices
Used in debugging
5-Mar-14
Prof.Nitin Ahire
129
130. Interrupt related
instructions
1) EI : it is used to enable the all
maskable interrupt. It required 1byte, one MC (4T). It does not
affect on TRAP
2) DI : it is used to disable all
maskable interrupt. 1-byte (4T). It
does not affect on TRAP
5-Mar-14
Prof.Nitin Ahire
130
131. Interrupt related
instructions
SIM : (set interrupt mask)
1-byte (4T) state.
• Used to enable or disable RST 7.5, RST
6.5, RST 5.5 interrupts.
• It does not affect on TRAP & INTR .
• It is used in serial data transmission
• It also transfer serial data bit „D7‟of „A‟
to the SOD pin
• Hence the CWR format must be load in
the „A‟ before execution of SIM
5-Mar-14
131
Prof.Nitin Ahire
instruction.
132. SIM (bit pattern)
• SOD pin
SOD
SDE
X
R 7.5
MSE
M’ 7.5 M’ 6.5 M’ 5.5
•
•
•
•
•
D7= SOD
D6= serial data enable 1=enable, 0=disable
D5= Don‟t care
D4= Reset R7.5 F/F, 1=Reset 0=no effect
D3=MSE Mask set enable 1=D2,D1,D0 bit are effective
0=D2,D1,D0 bit are ignored
• D2= M‟7.5 Mask RST 7.5 1= Mask or disable R7.5
0= Enable RST 7.5
• D1=M‟6.5 Mask RST 6.5 1= Mask or disable R6.5
0= Enable RST 6.5
• D0=M‟5.5 Mask RST 5.5 1= Mask or disable R5.5
0= Enable RST 5.5
5-Mar-14
Prof.Nitin Ahire
132
133. Interrupt related
instructions
RIM : ( read interrupt mask)
1-byte (4T) state.
• It gives the status of the pending maskable
interrupt (RST 7.5 – RST 5.5)
• It does not affect on TRAP & INTR
• It can also transfer the contents of the serial
input data on the SID pin into the
accumulator („D7‟ bit.)
• Hence after execution of this instruction
serial data get load in to the accumulator
5-Mar-14
Prof.Nitin Ahire
133
134. RIM (bit pattern)
• SID pin
SID
•
•
•
•
I 7.5
I 6.5
I 5.5
IE
M 7.5
M 6.5
M 5.5
D7= SID
D6=
D5=
if 1 respective interrupt is pending
D4=
0 respective interrupt is not pending
• D3=IE interrupt enable
• D2=
• D1=
• D0=
5-Mar-14
if 1 respective interrupt is Masked
0 respective interrupt is unmasked
Prof.Nitin Ahire
134
136. Features of 8155 (PPI)
•
•
•
1)
2)
3)
4)
5)
6)
It is a multifunction device designed to use in
minimum mode system
It contain RAM, I/O ports and Timer
Features
2k static RAM cell organized as 256 bytes
2 programmable 8 bit I/O ports (A,B)
1 programmable 6 bit I/O port (c)
1 programmable 14 bit binary down
counter/timer
An internal address latch to de multiplex AD0AD7 using ALE
Internal selection logic for memory and I/O.
using command register
5-Mar-14
Prof.Nitin Ahire
136
138. Pin out
• ADo-AD7 : address and data lines
internally de multiplex by using
internal latch and ALE signal address
lines are used to access the memory
or I/O port depending on the status
of IO/M^ pin i/p
•
D0-D7 lines act as data bus
5-Mar-14
Prof.Nitin Ahire
138
139. Pin out
• ALE : used to de multiplex the AD0AD7
• IO/M^ : used to differentiate
between IO or memory
• CE^ : used to select the 8155
• RD^ : used for to read the data from
memory or I/O
• WR^: used for to write the data from
memory or I/OProf.Nitin Ahire
5-Mar-14
139
140. Pin out
• Reset : used to reset the 8155 IC
• PA0-PA7,PB0-PB7 : Port A and Port B I/P 8 bit
pins they can be programmed either i/p or o/p
port using command register
• PC0-PC5 : these are 6 bit I/O pins they can be
used as simple Input output port or control port
when PA and/or PB are used in handshake mode
• Timer in: this is an i/p to the timer
• Timer out :This is an o/p pin depending on the
mode of the timer o/p can be either a square
wave or pulse.
• VCC, GND : +5 v resp. to GND
5-Mar-14
Prof.Nitin Ahire
140
141. I/O port or timer selection
IO/M^
1
1
1
1
1
1
0
5-Mar-14
A2
0
0
0
0
1
1
A1
0
0
1
1
0
0
Prof.Nitin Ahire
A0
0
1
0
1
0
1
CWR
PORT A
PORT B
PORT C
Timer LSB
Timer MSB
Memory option
141
142. Control Word of 8155
D7
•
•
•
•
•
•
D6
D5
D4
D3
D2
D0=Port A
0=Input
D1=Port B
1=Output
D2 &D3 used with port C
D4 (IEA=interrupt Enable Port A)
D5 (IEB=interrupt Enable Port B)
D6&D7 used in timer mode
5-Mar-14
Prof.Nitin Ahire
D1
D0
1=Enable
0=Disable
142
143. D7 D6
0 0
0 1
1
1
5-Mar-14
0
1
timer commands
NOP
Stop counting if timer
is running
Stop after TC (stop after
at the count)
Start timer if is not
running
Prof.Nitin Ahire
143
144. Timer mode
• MSB
• LSB
M2
M1
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
• Mode 0 In this mode the timer o/p remains high for half the
count
and goes low for the remaining
count, thus providing the single
square wave. The
pulse width is determined by count and clk freq
• Mode 1 In this mode the initial count is automatically reloaded
at the
end of each count. Provide the continuous square
wave.
• Mode 2 In this mode single clock pulse is provided at the end
of count
• Mode 3 This is similar to mode 2 except the initial count is
reloaded to provided a Prof.Nitin Ahire wave form
continuous
5-Mar-14
144
145. • For port C
D3 D2
0 0 = ALT
1 1 = ALT
0 1 = ALT
1 0 = ALT
5-Mar-14
1(port C as Input mode)
2(Port C as Output Mode)
3 used in handshake mode
4 along with Port A &B
Prof.Nitin Ahire
145
146. Example 1
• Design a square wave generator with
a pulse width of 100 us by using the
8155 timer if clock freq is 3MHz.
Sol : T=1/F=1/3MHz=330ns
Timer count=pulse period/CLK period
= 200us/330ns=606
count = 025Eh
5-Mar-14
Prof.Nitin Ahire
146
147. • Assuming the port addresses
CWR=20h
Timer LSB=24h
Timer MSB=25h
Count =025Eh
Therefore 5Eh must be load in the LSB timer
Select mode 1 for square wave.
Therefore 42h (01000010)must be load in the
MSB timer
5-Mar-14
Prof.Nitin Ahire
147
148. • Control word
To start the timer D7 and D6 bit must
be 1
set the bit of CWR and send to
address 20h
therefore C0h (11000000) must be
load in CWR register.
5-Mar-14
Prof.Nitin Ahire
148
149. Program for square wave
• MVI A,5Eh
OUT 24H
MVI A,42H
OUT 25H
MVI A,C0H
OUT 20H
HLT
5-Mar-14
Prof.Nitin Ahire
149
151. Feature of 8255
• It is programmable parallel I/O device
• It has 3,8 bit I/O Ports: Port A, Port
B, Port C, which are arranged in two
groups of 12 pins.
• TTL compatible
• Direct bit set/reset capability is
available for Port C
5-Mar-14
Prof.Nitin Ahire
151
152. 8255 PIN DIAGRAM
PA0-PA7
PB0-PB7
PC0-PC7
D0-D7
RESET
RD¯
WR ¯
A0-A1
CS ¯
5-Mar-14
Vcc , Gnd
I/O
I/O
I/O
I/O
I
I
I
I
I
I
Port A Pins
Port B Pins
Port C Pins
Data Pins
Reset pin
Read input
Write input
Address pins
Chip select
Prof.Nitin Ahire
+5volt supply
152
154. 8255 BLOCK DIAGRAM
Data Bus Buffer: It is an 8 bit data buffer used
to interface 8255 with 8085. It is connected to
D0-D7 bits of 8255.
Read/write control logic: It consists of inputs
RD¯,WR¯,A0,A1,CS¯ .
RD¯,WR¯ are used for reading and writing on
to 8255 and are connected to MEMR¯,MEMW¯
of 8085 respectively.
A0,A1 are Port select signals used to select the
particular port .
CS ¯ is used to select the 8255 device .
It is controlled by the output of the 3:8 decoder
5-Mar-14
154
Prof.Nitin Ahire
used to decode the address lines of 8085.
155. 8255 BLOCK DIAGRAM
A0,A1 decide the port to be used in 8255.
A1
A0
Selected port
0
0
1
1
0
1
0
1
Port A
5-Mar-14
Port B
Port C
Control Register
Prof.Nitin Ahire
155
156. 8255 BLOCK DIAGRAM
Group A and Group B Control:
Group A control consists of Port A and Port C
upper.
Group B control consists of Port B and Port C
lower.
Each group is controlled through software.
They receive commands from the RD¯, WR¯
pins to allow access to bit pattern of 8085.
The bit pattern consists of :
1. Information about which group is operated.
2. Information about mode of Operation.
5-Mar-14
Prof.Nitin Ahire
156
157. 8255 BLOCK DIAGRAM
• PORT A,B: These are bi-directional 8 bit ports
each and are used to interface 8255 with CPU
or peripherals.
• Port A is controlled by Group A while Port B is
controlled by Group B Control.
• PORT C: This is a bi-directional 8 bit port
controlled partially by Group A control and
partially by Group B control .
• It is divided into two parts Port C upper and
Port C lower each of a nibble.
• It is used mainly for control signals and
interfacing with peripherals.
5-Mar-14
157
Prof.Nitin Ahire
158. 8255 Operating Mode
• 8255 provides one control word register
• It is selected when
A0=1,A1=1,CS^=0,WR^=0
• The read operation is not allowed for CWR
• There are two CWR formats (mode)
1)BSR mode 2)I/O mode
• The two basic modes are selected by D7
bit of control register
• when D7=1 it is a I/O mode & D7=0 it is
BSR mode
5-Mar-14
158
Prof.Nitin Ahire
159. 8255 MODES
• BSR (Bit Set Reset) Mode
• Only C is available for bit mode access.
• Allows single bit manipulation for control
applications
• Mode 0 : Simple I/O
• Any of A, B, CL and CH can be programmed as
input or output
• Mode 1: I/O with Handshake
• A and B can be used for I/O
• C provides the handshake signals
• Mode 2: Bi-directional with handshake
• A is bi-directional with C providing handshake
signals
• B is simple I/O (mode-0) or handshake I/O
5-Mar-14(mode-1)
Prof.Nitin Ahire
159
160. BSR mode
D7
D5
D4
D3
D2
D1
D0
0
•
•
•
D6
X
x
x
b
b
b
S/R
Bit D7 must be zero for BSR mode
The BSR mode is a port C bit set/reset mode.
The indivisible bit of port C can be set or reset
by writing a control word in CWR.
• Port C bit set/reset ; if D0=0 reset
D0=1 set
• The port pin of port C is selected using bit
D3,D2,D1
• The BSR mode affect only one bit of port C at a
time
5-Mar-14
160
Prof.Nitin Ahire
161. Port C bit selection
D3/b
0
0
0
0
1
1
1
1
5-Mar-14
D2/b
0
0
1
1
0
0
1
1
D1/b
0
1
0
1
0
1
0
1
Prof.Nitin Ahire
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
0
1
2
3
4
5
6
7
161
162. Example
• Write a set of instruction to perform the
following
1)Set bit 4 of port C
2)Reset bit 4 of port C( Assume Port C Address
=12 h)
Sol: 1) MVI A, 09h
OUT 12h
2) MVI A,08h
OUT 12h
5-Mar-14
Prof.Nitin Ahire
162
163. I/O mode (CWR)
D7
D6
D5
I/O,BSR Mode A Mode A
D4
PA
D3
D2
PCU Mode B
D1
D0
PB
PCL
• When the bit D7=1 then I/O mode is selected
• The bit D6 and D5 used for mode selection of Group A
• If the D4 =1port A act as I/P port
D4 = 0 port A act as O/P Port
• If the D3 = 1 Port C Upper act as I/P Port
D3 = 0 port C Upper act as O/P Port
• The bit D2 used for mode selection of Group B
• If the D1 = 1 port B act as I/P Port
•
D1 = 0 port B act as O/P Port
• If the D0 = 1 Port C Lower act as I/P Port
D0 = 0 Port C Lower act as O/P Port
5-Mar-14
Prof.Nitin Ahire
163
164. Example
• Write a program to initialize 8255 in
the configuration given below:
1 Port A : Simple I/P
2 Port B : Simple O/P
3 Port CL: O/P
4 Port CU: I/P
Assume CWR address is 83h
5-Mar-14
Prof.Nitin Ahire
164
165. solutions
I/O,BSR Mode A Mode A
1
0
0
PA
1
PCU Mode B
1
0
PB
PCL
0
0
• MVI A,98h
OUT 83h
5-Mar-14
Prof.Nitin Ahire
165
166. INTERFACING 8085 & 8255
• Here 8255 is interfaced in I/O Mapped I/O mode.
Initially we write down the addresses and then
interface it .
A15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Port
1
0
0
0
0
X
X
X
X
X
X
X
X
X
0
0
A
1
0
0
0
0
X
X
X
X
X
X
X
X
X
0
1
B
1
0
0
0
0
X
X
X
X
X
X
X
X
X
1
0
C
1
0
0
0
0
X
X
X
X
X
X
X
X
X
1
1
CW
5-Mar-14
Prof.Nitin Ahire
166
167. INTERFACING 8085 & 8255
• Thus we get addresses ,considering don‟t cares to
be zero as
Port A =80H
Port B =81H
Port C =82H
CWR =83H
• Then, we give A11,A12,A13 pins to A,B,C inputs of
Decoder to enable 8255 or Chip Select.
• A15 is logic 1 so it is given to active HIGH G1 pin&
A14 ,IO/M ¯ are given to active low G2B ¯,G2A ¯
pins.
5-Mar-14
167
• Output from Latch Prof.Nitin Ahire as A0,A1 pins to 8255
is given
while D0-D7 are given as data inputs.
168. INTERFACING 8085 & 8255
A15
A14
IO/M
A13
A12
A11
A
G2A G2B G1
B
PA
C
/CS
8085
8255
3:8 decoder
(AD0-AD7)
O0
74373O1
A0-A7
PB
PC
O7
RD ¯
WR ¯
RD¯
WR¯
5-Mar-14
A0
A1
D7-D0
ALE
Prof.Nitin Ahire
168
169. INTERFACING 8085 & 8255
Example:
Take data from 8255 port B.
Add FF H .
Output result to port A.
5-Mar-14
Prof.Nitin Ahire
169
170. Solution
MVI A,82H
OUT 83H
LDA 81H
ADI FFH
OUT 80H.
RST1.
5-Mar-14
Initialize 8255.
Take data from port B
Add FF H to data
OUT Result to port A.
STOP.
Prof.Nitin Ahire
170
172. Stepper motor
• Hardware : A stepper motor is a
digital motor. It can be driven by
digital signals motor shown in the
figure ( ckt ) has two phases, with
center tap winding.
• The center taps of these winding are
connected to the +5Volt supply.
• Due to this, motor can be excited by
grounding 4 terminals of the 2
5-Mar-14
172
Prof.Nitin Ahire
winding.
173. Locking system for stepper
motor
• In the stepper motor it is not
desirable to excite both the ends of
the same winding simultaneously.
• This cancel the flux and motor
winding may damage.
• To avoid this digital clocking system
must be design.
5-Mar-14
Prof.Nitin Ahire
173
174. Data bit pass to the port A
PA0
1
1
0
0
5-Mar-14
PA1 PA2 PA3
0
1
0 = 0A
0
0
1 = 09
1
0
1 = 05
1
1
0 = 06
Prof.Nitin Ahire
174
176. Initialized Port A as O/P Port
• Program for stepper motor
LXI SP,FFFFH
MVI A,80H ; to make port A as o/p port
OUT CWR
BACK: LXI H,5000H ;HL act as memory pointer
MVI C,04H
;counter for the steps
UP:
MOV A,M
;data bits transfer on the lower nibble of
port A
OUT PORT A
CALL DELAY ; delay for the steps
INX H
; increment the HL pair for the next
data bits
DCR C
; decrement the counter
JNZ UP
;check zero flag
JMP BACK ; jump back for continuous loop ( motor
rotation)
5-Mar-14
Prof.Nitin Ahire
176
