Vishnu Vardhan Reddy Poreddy is a computer engineering graduate from North Carolina State University seeking a position in design automation. He has experience in IC design at LSI/Avago and worked on complex SoCs in 28nm technology involving floorplanning, placement, routing and timing analysis. During an internship at Intel, he developed automation scripts and made code changes to improve runtime efficiency. His academic projects include ASIC designs in Verilog for algorithms and NoC routers, C++ based cache and branch predictor simulators, and SystemVerilog verification of a microcontroller. He is proficient in Verilog, C/C++, Perl and EDA tools from Cadence, Altera and Xil

1. VISHNU VARDHAN REDDY POREDDY
MS in Computer Engineering | 919-579-3912 | vporedd@ncsu.edu | www.linkedin.com/in/vporeddy
EDUCATION
North Carolina State University, Raleigh, NC Computer Engineering GPA: 3.67/4.0 Dec’16
National Institute of Technology, Trichy, India Electronics&CommunicationsEngg. GPA:7.73/10 May’12
TECHNICAL SKILLS
General linux, windows.
Languages Verilog, C, C++, Perl, System Verilog, Tcl/Tk.
BackEnd Tools ICCompiler, PrimeTime, Star-RC, Formality, Redhawk,
FrontEnd Tools Altera-Quartus, Modelsim, Xilinx, Cadence-Virtuoso,
INDUSTRY EXPERIENCE
LSI/Avago, India R&D Engineer IC Design-II July’12 to July’15
Worked in the Physical Design team which is responsible to get complex SoCs in 28nm-technology through FloorPlanning,
Place, Clock, Route and STA.
 Worked on some of the complex blocks in LSI Axxia Processor,ST-Ericsson Baseband processor and Cisco switch with
teams spread across US, Shanghai and India.
 Blocks were 1-3 million instances clocked at 500-725MHz. Solved critical issues like Congestion, Timing and IVD
through strategic approaches.
 Developed a Tcl script to build a balanced binary tree to any number of sinks. It was widely used across different
projects with SERDES interface. The skew achieved is less than 20ps.
 Worked closely with DFT team to develop a Tcl script which adds ECO flops to the existing scan-chains. This reduced
the manual work for the rest of the team.
 Worked as a standby STA engineer for a full-chip design and resolved flow issues.
INTEL Corporation, Folsom, CA Design Automation Intern June’16 to Aug’216
 Worked on an internal Regression tool to test reliability of the flow scripts on multiple test cases. Setup a automated
flow as per the requirements.
 Developed scripts: Generate a connectivity matrix for plan groups; Check and report changes in UPF; Custom path
definition for plan groups at Full Chip level; Code changes to improve runtime of procs.
ACADEMIC PROJECTS
 Cadence-Virtuoso
 128-Bit Synchronous SRAM: Schematic and layout implementation of a 4-bit word, 32-word, R/W port
Synchronous SRAM using FreePDK15 library. The whole design is optimized for power and speed. Various
models of Decoders and configurations are studied.
 ASIC Designs in Verilog
 Bellman Ford Algorithm: An optimized design to find the shortest spanning tree between a pair of graph
nodes that can handle negative edge weights.
 6-Port Bufferless Router for 3-D Network on Chip: Uses deflection routing algorithm with a permutation
network which does not have any sequential dependency in port allocation giving high-speed router.
 Generic Network Interface for Network on Chip: Designed Asynchronous FIFOs and Ping-Pong memory
banks to handle clock domain crossing at the interface.
 C++ based simulators:
 L1 and L2 Cache design with variable size, variable configuration and Victim Cache.
 Branch Predictors: Bimodal, Gshare and Hybrid models with different configurations.
 Dynamic Instruction Scheduler:A fully pipelined architecturewith Re-Oder Buffers, Issue Queue and Rename
Map table to enable Out-Of-Order Execution.
 LC3 Micro-Controller Verification using SystemVerilog
 Golden References for each Block and Top and written and verified usingSystem Verilog. Randomized testing
and Directed testing techniques are implemented to achieve higher coverage faster.
ACHIEVEMENTS
 SPARK award through employee recognition Program at LSI.
 OUTSTANDING employee during the performance appraisal at LSI, 2014.