3. 3
History of Technology Leadership
1990 1995 2006 2014
Rambus
founded
Nintendo64
ships with
RDRAM®
1999
PCs ship
with RDRAM®
2000 2005
500M RDRAM®
devicesship
Sony
PLAYSTATION®3
ships
2011
Acquired
Cryptography
ResearchInc.
Introduced
R+™ solutions,
Binary Pixel,
Major IP licensing
agreements
2013
UnveiledSmart
Sensor Technology,
CryptoManager™,
JoinedJEDEC
Revolutionized the memory market
with RDRAM and an innovative
business model
Rambus 1.0 Rambus 2.0 Rambus 3.0
Diversified offering with
continued focus on invention
and licensing
Engaging the industry to
deliver value through IP as a
product
2015
Launch R+ DDR4
ServerDIMM
Chipset
Sony
PLAYSTATION®2
ships
4. 4
Rambus At-a-Glance
• Founded in 1990; publicly traded on NASDAQ (RMBS) since 1997
• Over 500 employees; primarily engineers/inventors, increasing sales & marketing
• Headquartered in Sunnyvale, CA with regional offices around the globe
5. 5
Rambus Senior Leadership Team
Laura
Stark
SVP, GM
Emerging
Solutions
Mike
Schroeder
SVP, Human
Resources
Jerome
Nadel
Chief Marketing
Officer
Paul
Kocher
Chief Scientist
Ron
Black
CEO
Martin
Scott
SVP, GM
Cryptography
Research
Satish
Rishi
Chief Financial
Officer
Jae
Kim
General
Counsel
Craig
Hampel
Chief Scientist
Luc
Seraphin
SVP, GM
Memory +
Interfaces
Kit
Rogers
SVP, WW Sales
& Technology
Partnerships
Krishna
Moorthy
VP, Managing
Director IDC
9. 9
4.4ZB (2014) < 44ZB (2020)
Digital Universe is massive and growing –
projected to double every 2 years
More. Faster. Better.
• Chips to enable more capacity at
high-performance for enterprise
and data center servers
• Interfaces to deliver data faster to
chips and memory
• Innovations to make systems with
better power efficiency, reliability
and usability
The World’s Data. Delivered.
Source: IDC 2014
10. 10
Memory + Interface Products and Solutions
R+ DDRn
Memory PHYs
• R+ DDR4/DDR3,
LPDDR4/3, DDR3/3L
• R+ Next-Gen DDR
• R+ HBM2
R+ Serial
Link PHYs
• R+ Multi-Protocol PHYs:
CEI6/11/25,
PCIe1/2/3/4, XAUI,
10GbE, SATA, JESD, FC,
CPRI, HMC, etc.
R+ DDR4 DIMM
Chipset
• DDR4 @ 2666Mpbs
• Register Clock Driver
(RCD)
• Data Buffer (DB)
LabStation
Validation
Platform
System, Board
and Chip
Co-Design
Bring-up, De-bug
and Characterization
Support
Enterprise
Networking Mobile
Storage
Data Center
Offerings
Enablement
Markets
11. 11
Enhanced
Margin
Optimized
Power
Superior Debug
and Serviceability
Integrated tools for
bring-up and debug
Works out-of-the-box
with no BIOS changes
required
Wide margin I/O
design with advanced
programmability
Exceed JEDEC
reliability standards for
ESD and EOS
Advanced power
management
Frequency-based, low-
power optimization
Industry-leading
Performance
Fully-compliant with the latest
JEDEC DDR4 RCD02 and DB02
standard at 2666 Mbps
Operational up to 2933 Mbps
R+ DDR4 Server DIMM Chipset
Built for speed, power efficiency and reliability, the RB26
DDR4 chipset for RDIMM and LRDIMM server modules
delivers top-of-the-line performance and capacity
needed to meet the growing demands on enterprise and
data center systems.
12. 12
Server DIMM Chipset = RCD + DB
Module buffers are now the critical
technology to achieve memory speed and
capacity for all server CPUs using DDR4
RegisteredDIMM (RDIMM)
Load ReducedDIMM (LRDIMM)
RegisterClock
Driver(RCD)
Data Buffer
(DB)
RCD
Boost Capacity and Bandwidth with DDR4 DIMMs
13. 13
Industry-leading Performance and Margin
• Compliant with latest JEDEC spec @ 2666 Mbps; built-in
support for 2933Mbps
• Wide margin IO design with advanced programmability
• Exceeds JEDEC reliability requirements
Optimized Power
• Frequency-based power optimization
Best-in-class Debug and Serviceability
• Integrated tools for bring-up and debug
• Works out of the box with default system BIOS
Standard Made Better
Sampling today
RB26 DDR4 Server DIMM Chipset
14. 14
Enhanced Design
Flexibility
Reduced
Power
Improved
Performance
Industry-leading
data rates
Increased bandwidth
Flexible packaging
options
Improved margin
and yield
Wide range of PLL
clock multipliers
Fine-grain power-up
/down options
Fully Standards-
Compatible
Faster time-to-market
Multi-protocol support
R+ DDRn PHYs
With their reduced power consumption and
industry-leading data rates, our line-up of
enhanced memory interface solutions support a
broad range of industry standards with improved
margin and flexibility.
15. 15
SoC Cost and Complexity on the Rise
Rising Design Cost and Complexity
90 65 45/50 32/28 22/20
Process (nm)
$18 16
$36 38
$68
81
$104
165 $164
190Design ImplementationCosts ($M)
Numberof IP Blocks per Design
Source: International Business Strategies
Re-spin
Probability
30-50+%
4-16%
• Increasing design complexity and
cost combined with increasing
performance requirements driving
the need for verified, high-margin IP
solutions
• Approaching ~200 IP blocks
per SoC
• Over $160M in design
implementation costs
• $10M+ potential revenue loss
if late to market due to re-spin
16. 16
• R+ LPDDR3
Supports 2133Mbps, 30% lower power
than LPDDR3
SoC PHYs compatible with LPDDR4,
LPDDR3
• R+ DDR4
Supports 3200Mbps
Designed for high-capacity servers and
consumer applications
R+ Memory Interfaces for Data Center and Mobile
Silicon-proven, high-performance, low-power memory interfaces with improved
system margin and flexibility
Validated solutions with partners:
Integrated tools for easy bring-up
and characterization:
LabStationPlatform On-chip NoiseMonitor
17. 17
Enhanced Design
Flexibility
Reduced
Power
Improved
Performance
Increased data rates
Improved bandwidth
Higher capacity
Support for multiple
packaging options
Enhanced margin
and yield
Improved power
efficiency
Lower signaling and
stand-by power
Fully Standards-
Compatible
Compliant with the latest
JEDEC and industry-standard
specifications
Support for multi-modal
functionality
R+ Serial Link PHYs
Optimized for power and area, our line-up
of R+ Serial Link Interface solutions deliver
maximum performance and flexibility for
today’s most challenging systems.
18. 18
• Big Data driving increasing need for
high-speed serial links, the backbone
of the cloud
• Pervasive across all high-end routers,
switches and networking systems
• 100GbE switch ports are growing from
current annual run-rate of tens of
thousands to handily exceed 10
million by 2019 – Crehan Research
Links are Increasingly Important in Data Centers
0
5
10
15
100GbEPortShipments(M)
2015 2016 2017 2018 2019
Source:Crehan ResearchInc.
19. 19
R+ Serial Links for Data Centers
High-speed, multi-protocol serial link interfaces optimized
for challenging enterprise systems
R+ 1-6G
R+ 1-11G
R+ 1-16G
40G+
(Test chip, modeling, design, etc.)
Performance
DesignComplexity
Demonstrated Excellence
• 15+ years of high-speed SerDes
design
• Silicon demonstrated up to
40Gbps(NRZ) SerDes
• Simulation, modeling and design of
56G interfaces, interconnects and
systems
• State-of-the-art signal and power
integrity internal tool methodology
R+ 1-28G
In Development
Available Today
21. 21
Provision. Protect. Trust.
• Complete security platforms to
provision features and functionality
throughout the device lifecycle
• Security cores to protect digital
entertainment content, electronic
device accessories and consumables
• Fundamental countermeasures and
services to enable trust by design
The World’s Data. Secured.
35B+ connected devices by 2020
with a critical need for robust security Source: IDC 2014
22. 22
Cryptography Research Products and Solutions
DPA Workstation
Platform
DPA Validation
Program
Design, product
evaluation and
training
IoT
Enterprise Digital Entertainment
Government
Mobile
DPA
Countermeasures
• DPA Resistant Cores
and Software Libraries
• Licensed
Countermeasures
CryptoManager
Platform
• Security Engine
• Infrastructure and Key
Provisioning Services
CryptoFirewall
Cores
• Content Protection
Core
• Anti-counterfeiting
Core
Offerings
Enablement
Markets
23. 23
Improve Time-
to-Market
High
Flexibility
Simplified device testing for
power analysis vulnerabilities
Training, evaluation services
and analysis equipment
Ready-to-use,DPA Resistant
solutions
Solutions can be optimized
for performance, size, and
security level
Solutions integrate with
standard cipher modes
such as CBC, ECB, etc.
Superior
Protection
Robust countermeasures to protect
against side-channel attacks
Broad range of hardware, software and
protocol approaches to secure tamper-
resistant devices
Cores validated to resist DPA attacks in
millions of traces
DPA Countermeasures
Protecting nearly 9 billionproducts a year,
our DPA countermeasures include fundamental
solutions and techniques for securing devices
against side-channel attacks.
24. 24
Security depends on secret keys … which must be protected
• Increasing security breaches at all levels – the data center, the network, and devices
• We focus on devices and bring unique, patented solutions to customers that need to secure and manage keys
K
f()inputs outputs
Device computes with key K, but
malicious attempts must never extract K
DPA Countermeasures: Keeping Secrets in Devices
25. 25
License countermeasures to DPA and other
side-channel attacks
• Fundamental intellectual property portfolio
• DPA “Lock” logo and testing program
• DPA Workstation™ test platform
• Design and testing services
• DPA hardened cryptographic cores and
software libraries to ease adoption
• Smart cards
• Smart phones/tablets
• Government/defense
• FPGAs
• Content protection
• Game consoles
• Point-of-sale terminals
• (and more)
Applications
DPA Countermeasure Solutions
26. 26
Improve Time-
to-Market
High
Flexibility
Reduce revenue lost to unauthorized
access and counterfeits
Easy integration in existing systems
Compatible with standard
manufacturing processes
Simplifies device validation to improve
time-to-market
Support distribution of various
Over-the-Top (OTT) content to
STBs and Smart TVs
Supports all content
distribution platforms –
satellite,cable, IPTV and OTT
Superior
Security
Highest level of security for content
protection and anti-counterfeiting
Independent hardware core
maintains security even if other
parts of the chip are compromised
CryptoFirewall Cores
Our cores complement existing security
implementations, and are ideal for protecting
digital content and preventing counterfeiting
in a broad number of applications.
27. 27
CryptoFirewall cores:
Content protection
Integrated in leading set top box SoCs
to protect content independently of the
software/CPU
CryptoFirewall cores:
Anti-counterfeiting
Cost-effective anti-cloning/ anti-
counterfeiting solution; manufacturable
across foundries & customizable
CryptoFirewall™ and Other Secure Cores
Peripheral
Untrusted
communication
CFC
Device SoC
28. 28
The Secure Content Storage Association
(SCSA) Selects Rambus Cryptography
Research To Help Secure Next-Generation
Digital Video Content
Rambus to deliver key provisioning services for VIDITY,
allowing leading technology and media companies to
enable 4K UHDand HighDynamic Range(HDR)
programming
LOS ANGELES and SUNNYVALE, Calif. – September 1,
2015 – Rambus Inc. (NASDAQ:RMBS) today announced
that its Cryptography Research Division has been selected
by the Secure Content Storage Association (SCSA) to run
and manage the VIDITY™ Key Issuance Center. This service,
part of the Cryptography Research Trust Services offering,
manages cryptographic keys that SCSA-enableddevices
and services use in securing high-quality 4K Ultra HD with
HDRHDand SD content. The SCSA develops technologies
for consumers to easily and securely purchase, transfer, and
view content across multiple electronic devices.
“The members of SCSA represent leading global technology
and entertainment brands where delivering a seamless,
high quality consumer experience along with…
NEWS RELEASE
• Secure Content Storage Association (SCSA)
founded by Twentieth Century Fox Home
Entertainment, Warner Brothers Home
Entertainment, SanDisk, and Western Digital
• VIDITY launched by SCSA in May 2015
• VIDITY is the SCSA format designed to enable
robust security for high-value content,
especially 4K, HDR, and early window
• We are a special advisor to the SCSA and
operate the VIDITY Key Issuance Center
Introducing VIDITY™
29. 29
Improved
Profitability
Streamline
Operations
Superior
Security
Provide a robust hardware
root-of-trust
Protect valuable secret keys,
identity credentials, and other
sensitive data
Protect against reverse
engineering and counterfeiting
Reduce NRE and
operating costs
Improve time-to-market
Reduce inventory waste
Automate provisioning
of keys
Enable common platform
across product lines
Integrate easily into
existing manufacturing flow
Secure Supply
Chain
Robust end-to-end
security
Secure provisioning
and tracking
Protect against the leakage
of cryptographic keys
CryptoManager Platform
From mobile phones to the Internet of Things (IoT),
connected devices have a critical need for robust
security. Our key provisioning and feature management
platform provides secure foundations of trust for a
connected world.
30. 30
• CryptoManager Security Engine
o Hardware root of trust
+ Manages the securityof keys and feature controlswithin
the SoC
• CryptoManager Infrastructure
o Appliance
o Tamper-resistant security appliance co-locatedat
customer factory
+ Distributeskeys and feature controls
o Trust Service
o A control center for device services with flexible
deployment options
o Includes an advancedManagementConsole
+ Centrally controlsthe whole systemfromthe cloud
CryptoManager Security Platform
Secure end-to-end device key
and feature management
Admin
HW Root
of Trust
Security
Service
Local
Appliance
Factories
31. 31
Securing devices and applications across all touch points
Building Trust Throughout the Entire Value Chain
Trustby Design Secure Assets&
Clusters
Device Configurations&
CustomerDemands
Applications &
Services
CustomerData &
Intelligence
Manufacturing In-field
Chipset Manufacturers Device Manufacturers Service Providers
Management
33. 38
What is ESD?
Moving the world’s
data from memory
through interfaces
Memory
& Interfaces
Reinventing
embedded security
from silicon to cloud
Cryptography
Research
Reimagining
computing from
sensor to cloud
Emerging
Solutions
Foundational R&D
Invention and harvesting
Methods and architecture
Incubation from concept to market
34. 39
Key Programs
Next-Gen Memory Computational Sensing
New technologies and
architectures to improve
memory performance and
bring compute closer to
memory
New smart sensors that
enable low cost, low
power light weight
sensing everywhere
35. 40
Challenges Facing the Industry
Limits of DRAM scaling
Number of CPU cores
scaling faster than
memory can support
Low CPU UtilizationBig Data Analytics
Cost per bit of DRAM
no longer scaling
with process
Massive and growing
data sets are straining
data center architecture
90nm
0.25um
0.18um
0.13um
65nm 45nm
0.35um
1990 1995 2000 2005
GateOxide
Thickness(nm)
10
1
The end of
traditional scaling
36. 41
Advanced development for future memory
• DDR5+ concepts and technology
• Gen n+2 buffer chips
Emergence of storage-class memory
• Faster than flash; lower cost and more reliable
than DRAM
• Addresses slow-down in DRAM cost reduction
• Alternative bit-cell technology to improve
memory endurance and power efficiency
• Rambus crosspoint ReRAM IP and technology
Next-generation Memory Development
Processing
Memory
Storage
37. 42
Enhanced Power
Efficiency
Accelerated
Computing
Higher memory capacity
reduced time and power
spent moving data
FPGAs enable parallel
offloading and acceleration of
compute tasks close to data
Improved
Performance
Utilizes DRAM to deliver
higher bandwidth and lower
latency vs. SSD
Smart Data Acceleration Research Program
A research program focused on improving the
performance and power efficiency of next-
generation data centers in the age of Big Data by
combining FPGAs and large amounts of memory to
optimize data movement and system performance.
38. 43
• Exploring alternatives to accelerate
the delivery and computation of data
System architectures
Application and Platform Software
FPGA acceleration
• Compatible with existing data center
hardware and software infrastructure
New Memory Architecture: Smart Data Acceleration
Processing
Memory
Storage
SDA Engine
39. 44
Focus Areas for Improving System PerformancePerformance
DRAM vs. SSD
• Lower latency under load improves
application performance; benefits increase
as workload demands rise
Minimizing Data Movement
• High memory capacity reduces the time
and power spent moving data back and
forth across networks
System
with SSD
System
with SDA
Compute Offload and Acceleration
• FPGAs enable parallel offloading and
acceleration of compute tasks next to the
memory storing the data
40. 45
Lensless Smart Sensors
Reduce
Cost
Ultra-low
Power
Eliminates the use of lenses
Enables new form factors
and low-cost infrastructure
Application-specific optics
and algorithms extract
image data with low-power
computer vision
Low-power, low-cost sensor technology that
captures information-rich images in a tiny form
factor using a revolutionary new approach to
optical sensing that replaces traditional lenses
with tiny diffractive optics.
Enhanced
Sensing
Collects information-rich
sensing data
Captures motion, optical
flow, depth and change
Tiny Form
Factor
Replaces lenses with ultra-
miniature phase grating optics
41. 46
Lensless Smart Sensor
Commercial Sensor Lens
~1.5mm
LSS Spiral Grating
0.055mm
Top view Cross-section view
Designed for ubiquitous smart sensing
Size Comparison Spiral Grating Detail
• Object recognition
• Image capture
• Video streaming
• Diffractive optics combine with optimized algorithms to enable a breadth of capabilities:
• Image change detection
• Point tracking
• Range finding
• Sophisticated gesture recognition
42. 47
LSS POD Kit
Partners in Open Development
• Partner with the industry to accelerate
and amplify discovery of applications
for our technology and development
of minimum viable product
prototypes
• Create and deliver hardware
development kits featuring LSS test
chip built on open-source hardware
and software
POD Program
frog IXDS
Notas del editor
From Patents to Products… a continued strategic transition to product ingredients and products
As well, as shared previously, we invent with product centric thinking – imagining how our inventions live in, and improve products.
7
4 key areas
4 key areas
Device personalization creates complexity in manufacturing and in inventory management
Liability associated with the leakage of secret keys during manufacturing
Technology transfer and IP theft through reverse engineering
Chip vendor has one SKU
(un-configured chip)
In 2013, $73B memory market which is ~ 1.25 x the microprocessor market
The memory industry is consolidating
More stability and opportunity
Moore’s Law is slowing, challenging traditional cost equation
Systems will adapt to use the memory technology in non-traditional ways
Data center evolution driving new memory and storage usage models
Power is an ever-increasing challenge
Memory and memory system design are key
Slide 15 – Cost Performance Gap – DRAM and Flash . This is a well-known graphic showing tiering of memory and storage and how cost and performance change. Over time, we’re predicting that the gap between memory and NVM/Flash will grow both in terms of cost and performance and that’s what will open up opportunities for new memories and new architectures.