Régis SANTONJA

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20 years experience in semiconductors (digital and analog) Mixed-signal IC verification - Advanced Mixed-Signal Verification techniques: Hybrid module-based/UVM testbench (drivers, monitors, sequencer, digital and analog parameter randomization), Metric Driven Verification, Functional coverage (mixed-signal assertions), automatic verification plan (vPlan) update (regressions), accurate Verilog-AMS and fast Wreal modeling, SystemVerilog, DPI, VPI. - Motion Sensors verification - Complex Power-Management, Audio and User interface IC (1+ million components) International Team Lead & Project Management - Multi-cultural context (US, Europe, India) - Organize tasks and plannings, priorities,...

verification mixed-signal systemverilog monitoring continuous-time coverage emanager verilog ams asic bind systemverilog; assertions assertions analog verilog-ams semantics mixed signal testbench

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Régis SANTONJA

Re usable continuous-time analog sva assertions - slides

Mixed signal verification challenges - slides

Verification Of 1 M+ Transistors Mixed Signal Ic Presentation