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meraz rizel
meraz rizel

my first seminar slide.

EducaciónTecnología
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R EFERENCE: PUBLISHED BY THE IEEE COMPUTER SOCIETY, JULY 2008 Presented by: Md. Merazul Islam 0507036 Dept. of CSE, KUET
W ARP P ROCESSING ? ,[object Object],[object Object],[object Object],[object Object],[object Object],Md. Merazul Islam, Dept. of CSE, KUET
F PGA C IRCUIT ? ,[object Object],[object Object],[object Object],[object Object],Figure: In the CAD-oriented FPGA, the configurable logic block inputs and outputs are directly connected to the switch matrices. Md. Merazul Islam, Dept. of CSE, KUET
W ARP A RCHITECTURE µ P I$ D$ FPGA Profiler Dynamic Part. Module (DPM) Md. Merazul Islam, Dept. of CSE, KUET Partitioned application executes faster with lower energy consumption 5 Profile application to determine critical regions 2 Profiler Initially execute application in software only 1 µ P I$ D$ Partition critical regions to hardware 3 Dynamic Part. Module (DPM) Program configurable logic & update software binary 4 FPGA
W ARP P ROCESSING S TEPS Md. Merazul Islam, Dept. of CSE, KUET µ P I$ D$ (FPGA) Profiler DPM (CAD) Binary Binary Decompilation Binary HW Bit stream RT Synthesis Partitioning Binary Updater Binary Updated Binary Binary Std. HW Binary JIT FPGA Compilation JIT FPGA Compilation Tech. Mapping/Packing Placement Logic Synthesis Routing
W ARP P ROCESSING S TEPS ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],discover loops, if-else, etc. reduce operation sizes, etc. reroll loops, etc. Md. Merazul Islam, Dept. of CSE, KUET
W ARP P ROCESSING S TEPS ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Md. Merazul Islam, Dept. of CSE, KUET
R ESULTS ,[object Object],[object Object],size time a 120 MB 3 min b 3.6 MB .108 s c 3.6 MB 1.11 s Md. Merazul Islam, Dept. of CSE, KUET
S PEEDUP C OMPARISON ,[object Object],[object Object],Md. Merazul Islam, Dept. of CSE, KUET
C ONCLUSION ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Md. Merazul Islam, Dept. of CSE, KUET

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0507036

  • 1. R EFERENCE: PUBLISHED BY THE IEEE COMPUTER SOCIETY, JULY 2008 Presented by: Md. Merazul Islam 0507036 Dept. of CSE, KUET
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  • 4. W ARP A RCHITECTURE µ P I$ D$ FPGA Profiler Dynamic Part. Module (DPM) Md. Merazul Islam, Dept. of CSE, KUET Partitioned application executes faster with lower energy consumption 5 Profile application to determine critical regions 2 Profiler Initially execute application in software only 1 µ P I$ D$ Partition critical regions to hardware 3 Dynamic Part. Module (DPM) Program configurable logic & update software binary 4 FPGA
  • 5. W ARP P ROCESSING S TEPS Md. Merazul Islam, Dept. of CSE, KUET µ P I$ D$ (FPGA) Profiler DPM (CAD) Binary Binary Decompilation Binary HW Bit stream RT Synthesis Partitioning Binary Updater Binary Updated Binary Binary Std. HW Binary JIT FPGA Compilation JIT FPGA Compilation Tech. Mapping/Packing Placement Logic Synthesis Routing
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