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Intel  8086 MICROPROCESSOR
Features  ,[object Object],[object Object],[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object]
Intel 8086 Internal Architecture
Internal architecture of 8086 ,[object Object],[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object]
BUS INTERFACE UNIT (BIU) ,[object Object],[object Object],[object Object],[object Object],[object Object]
THE QUEUE (Q) ,[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object]
The Queue Operation   Opcode Data Opcode queue From memory Repeat the same procedure for successive contents of Q Execute it with data bytes decoded by the decoder Take 2 nd  byte from Q as opcode, decode 2 nd  byte opcode Execute it with data bytes decoded by the decoder Is it  Single byte? Take 2nd byte from Q as opcode, decode 2nd byte opcode (Decode also decides the no. of data bytes for the instructions) Update queue Opcode 2 nd  byte yes No
Segmented Memory 1 MB ,[object Object],[object Object],[object Object],00000 FFFFF Physical Memory Code segment (64KB) Data segment (64KB) Extra segment (64KB) Stack segment (64KB)
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object]
Segment registers ,[object Object],[object Object],[object Object],[object Object]
Instruction pointer & summing block ,[object Object],[object Object],[object Object],[object Object],[object Object]
[object Object],Inserting a hexadecimal 0H (0000B) with the CSR or shifting the CSR four binary digits left 3 4 B A  0  ( C S ) + 8 A B 4 ( I P ) 3 D 6 5  4  (next address) 34BA 8AB4 CS IP 34BA0 3D645 44B9F Code segment 8AB4  (offset)
[object Object],[object Object],Required Address Offset Segment Address 0000 0000 0010 1001 0000 0001  0000  0000  0010  1001 0001 0000 0000 0000
EXECUTION UNIT ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
EXECUTION UNIT – General Purpose Registers AH AL BH BL CH CL DH DL SP BP SI DI 8 bits 8 bits 16 bits Accumulator Base Count  Data Stack Pointer Base Pointer Source Index Destination Index AX BX CX DX Pointer Index 8 bits 8 bits 16 bits Accumulator Base Count  Data Stack Pointer Base Pointer Source Index Destination Index
EXECUTION UNIT – General Purpose Registers Register Purpose AX Word multiply, word divide, word I /O AL Byte multiply, byte divide, byte I/O, decimal arithmetic AH Byte multiply, byte divide BX Store address information CX String operation, loops CL Variable shift and rotate DX Word multiply, word divide, indirect I/O (Used to hold I/O address during I/O instructions. If the result is more than 16-bits, the lower order 16-bits are stored in accumulator and higher order 16-bits are stored in DX register)
Pointer And Index Registers ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
EXECUTION UNIT – Flag Register ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],U U U U OF DF IF TF SF ZF U AF U PF U CF Carry  Over flow Direction  Interrupt Trap   Sign Zero Auxiliary Parity  U - Unused
EXECUTION UNIT – Flag Register Flag Purpose Carry (CF) Holds the carry after addition or the borrow after subtraction. Also indicates some error conditions, as dictated by some  programs and procedures . Parity (PF) PF=0;odd parity, PF=1;even parity. Auxiliary (AF) Holds the carry (half – carry) after addition or borrow after subtraction between bit positions 3 and 4 of the result  (for example, in BCD addition or subtraction.) Zero (ZF) Shows the result of the arithmetic or logic operation. Z=1; result is zero. Z=0; The result is 0 Sign (SF) Holds the sign of the result after an arithmetic/logic instruction execution. S=1; negative, S=0
Flag Purpose Trap (TF) A control flag. Enables the trapping through an on-chip debugging  feature. Interrupt (IF) A control flag. Controls the operation of the INTR (interrupt request) I=0; INTR pin disabled. I=1; INTR pin enabled. Direction (DF) A control flag. It selects either the increment or decrement mode for DI  and /or SI registers during the string instructions. Overflow (OF) Overflow occurs when signed numbers are added or  subtracted. An overflow indicates the result has exceeded  the capacity of the Machine
Execution unit – Flag Register ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

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26677766 8086-microprocessor-architecture

  • 1. Intel 8086 MICROPROCESSOR
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  • 4. Intel 8086 Internal Architecture
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  • 10. The Queue Operation Opcode Data Opcode queue From memory Repeat the same procedure for successive contents of Q Execute it with data bytes decoded by the decoder Take 2 nd byte from Q as opcode, decode 2 nd byte opcode Execute it with data bytes decoded by the decoder Is it Single byte? Take 2nd byte from Q as opcode, decode 2nd byte opcode (Decode also decides the no. of data bytes for the instructions) Update queue Opcode 2 nd byte yes No
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  • 21. EXECUTION UNIT – General Purpose Registers AH AL BH BL CH CL DH DL SP BP SI DI 8 bits 8 bits 16 bits Accumulator Base Count Data Stack Pointer Base Pointer Source Index Destination Index AX BX CX DX Pointer Index 8 bits 8 bits 16 bits Accumulator Base Count Data Stack Pointer Base Pointer Source Index Destination Index
  • 22. EXECUTION UNIT – General Purpose Registers Register Purpose AX Word multiply, word divide, word I /O AL Byte multiply, byte divide, byte I/O, decimal arithmetic AH Byte multiply, byte divide BX Store address information CX String operation, loops CL Variable shift and rotate DX Word multiply, word divide, indirect I/O (Used to hold I/O address during I/O instructions. If the result is more than 16-bits, the lower order 16-bits are stored in accumulator and higher order 16-bits are stored in DX register)
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  • 26. EXECUTION UNIT – Flag Register Flag Purpose Carry (CF) Holds the carry after addition or the borrow after subtraction. Also indicates some error conditions, as dictated by some programs and procedures . Parity (PF) PF=0;odd parity, PF=1;even parity. Auxiliary (AF) Holds the carry (half – carry) after addition or borrow after subtraction between bit positions 3 and 4 of the result (for example, in BCD addition or subtraction.) Zero (ZF) Shows the result of the arithmetic or logic operation. Z=1; result is zero. Z=0; The result is 0 Sign (SF) Holds the sign of the result after an arithmetic/logic instruction execution. S=1; negative, S=0
  • 27. Flag Purpose Trap (TF) A control flag. Enables the trapping through an on-chip debugging feature. Interrupt (IF) A control flag. Controls the operation of the INTR (interrupt request) I=0; INTR pin disabled. I=1; INTR pin enabled. Direction (DF) A control flag. It selects either the increment or decrement mode for DI and /or SI registers during the string instructions. Overflow (OF) Overflow occurs when signed numbers are added or subtracted. An overflow indicates the result has exceeded the capacity of the Machine
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