SlideShare una empresa de Scribd logo
1 de 33
Higher Computing  NAB REVISION
Areas to review: ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Floating Point Representation ,[object Object],[object Object],[object Object],[object Object],mantissa exponent
Colour (Bit) Depth ,[object Object],[object Object],[object Object],Examples on next page >>>
Table of Bit Depth 2 4 = 16 colours 2 8   = 256 colours 2 16 = 65,536 colours True Colour 2 24   = 16,777,216 colours
Unicode ,[object Object],[object Object],[object Object],[object Object]
Resolution Independence ,[object Object],[object Object],[object Object]
Processor Structure Control ALU Registers Cache Main Memory Backing  Storage Address bus Data bus Control bus
Control Bus ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],REFER TO P.12-13: BrightRed Higher Revision
READ Operation ,[object Object],[object Object],[object Object],[object Object],[object Object],FETCH/EXECUTE CYCLE
Memory Read Operation Cache Main Memory Backing  Storage Address bus Data bus Address bus loaded with address of the required memory location The processor activates the READ line on the control bus READ line activated CONTROL BUS The contents of the memory location are transferred along the data bus into the processor If it is an instruction, it is DECODED and EXECUTED in the processor FETCH/EXECUTE CYCLE ***Use arrow keys to control animations*** Control ALU Registers
WRITE Operation ,[object Object],[object Object],[object Object],[object Object],[object Object],FETCH/EXECUTE CYCLE
Memory Write Operation Cache Main Memory Backing  Storage Address bus Data bus WRITE line activated CONTROL BUS FETCH/EXECUTE CYCLE ***Use arrow keys to control animations*** The processor sets up the address bus with the address of the required memory location The processor sets up the data bus with the data to be written to memory The processor activates the WRITE line on the Control Bus The data is transferred along the data bus to the memory location Control ALU Registers
Data Bus ,[object Object],[object Object],[object Object],[object Object],[object Object]
Address Bus ,[object Object],[object Object],[object Object],[object Object],[object Object]
Cache Memory Control ALU Registers Cache Main Memory Backing  Storage Address bus Data bus Control bus ***Use arrow keys to control animations*** ,[object Object],[object Object],[object Object]
Buffer Laser Printer Data to be printed is sent by the FAST processor to the SLOWER functioning printer Buffer Data is stored in the Buffer until the printer is ready to print it. When the printer has ‘caught up’ it requests the data to be printed from the Buffer ***Use arrow keys to control animations*** Not suitable for Network Printing Computer System
Spooling Laser Printer File to be printed PROCESSOR HARD DISK Stored temporarily here ***Use arrow keys to control animations*** Suitable for Network Printing
Parallel Interfaces Many bits are send down parallel lines – faster than serial transmission ***Use arrow keys to control animations*** 0 1 0 1 0 1 1
Serial Transmission 0 One bit is sent down a single line – slower, but more robust than parallel ***Use arrow keys to control animations***
Client/Server Network All data goes through the central SERVER CLIENT CLIENT CLIENT CLIENT CLIENT SERVER
Peer to Peer Network Want to send a file from one computer to another? The file will go from computer to computer on the network until it reaches its destination. Computer 2 Computer 1 Computer 4 Computer 3
Routers/Hubs/Switches A Hub splits a signal down 2 or more channels. Hubs split the signals ‘blindly’ whilst Switches forward data packets down the exact channels more intelligently HUB/SWITCH Network 1 Network 2 Router A router sends data packets between different networks using the Internet Protocol (IP) ROUTER ***Use arrow keys to control animations***
Bus Topology Node 1 Node 2 Node 3 Node 4 Node 5 = main channel ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],***Use arrow keys to control animations*** = data packet
Star Topology = channel ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],***Use arrow keys to control animations*** = data packet
Ring Topology = channel ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],***Use arrow keys to control animations*** = data packet
Mesh Topology = channel ,[object Object],[object Object],[object Object],[object Object],[object Object],***Use arrow keys to control animations*** = data packet
Bootstrap Loader ,[object Object],[object Object],[object Object],[object Object]
Image File Types ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Utility Programs ,[object Object],[object Object],[object Object],[object Object],[object Object],***Use arrow keys to control animations*** Each square represents a sector of the Hard Disk
Viruses, Worms & Trojans ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Detection Techniques ,[object Object],[object Object],[object Object],[object Object],See p.22/23 of BrightRed for more detailed explanations of these areas.
Solid State Storage Devices ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Más contenido relacionado

La actualidad más candente

03 top level view of computer function and interconnection
03 top level view of computer function and interconnection03 top level view of computer function and interconnection
03 top level view of computer function and interconnection
Sher Shah Merkhel
 
Chapter 3 - Top Level View of Computer / Function and Interconection
Chapter 3 - Top Level View of Computer / Function and InterconectionChapter 3 - Top Level View of Computer / Function and Interconection
Chapter 3 - Top Level View of Computer / Function and Interconection
César de Souza
 
8237 dma controller
8237 dma controller8237 dma controller
8237 dma controller
Tech_MX
 

La actualidad más candente (19)

DMA presentation [By- Digvijay]
DMA presentation [By- Digvijay]DMA presentation [By- Digvijay]
DMA presentation [By- Digvijay]
 
Unit 2
Unit 2Unit 2
Unit 2
 
03 top level view of computer function and interconnection
03 top level view of computer function and interconnection03 top level view of computer function and interconnection
03 top level view of computer function and interconnection
 
Unit 5 lect-3-multiprocessor
Unit 5 lect-3-multiprocessorUnit 5 lect-3-multiprocessor
Unit 5 lect-3-multiprocessor
 
DMA operation
DMA operationDMA operation
DMA operation
 
Computer function-and-interconnection 3
Computer function-and-interconnection 3Computer function-and-interconnection 3
Computer function-and-interconnection 3
 
Chapter 3 - Top Level View of Computer / Function and Interconection
Chapter 3 - Top Level View of Computer / Function and InterconectionChapter 3 - Top Level View of Computer / Function and Interconection
Chapter 3 - Top Level View of Computer / Function and Interconection
 
8237 dma controller
8237 dma controller8237 dma controller
8237 dma controller
 
Unit 4-lecte3-io interface
Unit 4-lecte3-io interfaceUnit 4-lecte3-io interface
Unit 4-lecte3-io interface
 
Unit 4-l ecture3-io interface
Unit 4-l ecture3-io interfaceUnit 4-l ecture3-io interface
Unit 4-l ecture3-io interface
 
Chapter 4
Chapter 4Chapter 4
Chapter 4
 
Direct Memory Access
Direct Memory AccessDirect Memory Access
Direct Memory Access
 
Chapter 2
Chapter 2Chapter 2
Chapter 2
 
03 top level view of computer function and interconnection.ppt.enc
03 top level view of computer function and interconnection.ppt.enc03 top level view of computer function and interconnection.ppt.enc
03 top level view of computer function and interconnection.ppt.enc
 
Unit 4-input-output organization
Unit 4-input-output organizationUnit 4-input-output organization
Unit 4-input-output organization
 
Data Manipulation
Data ManipulationData Manipulation
Data Manipulation
 
Dma
DmaDma
Dma
 
Bus aribration
Bus aribrationBus aribration
Bus aribration
 
Chapter 3 caal (1)
Chapter 3 caal (1)Chapter 3 caal (1)
Chapter 3 caal (1)
 

Destacado

Parallel computing
Parallel computingParallel computing
Parallel computing
virend111
 
0 introduction to computer architecture
0 introduction to computer architecture0 introduction to computer architecture
0 introduction to computer architecture
aamc1100
 

Destacado (20)

Introduction To Parallel Computing
Introduction To Parallel ComputingIntroduction To Parallel Computing
Introduction To Parallel Computing
 
Introduction to Parallel Computing
Introduction to Parallel ComputingIntroduction to Parallel Computing
Introduction to Parallel Computing
 
Highly Surmountable Challenges in Ruby+OMR JIT Compilation
Highly Surmountable Challenges in Ruby+OMR JIT CompilationHighly Surmountable Challenges in Ruby+OMR JIT Compilation
Highly Surmountable Challenges in Ruby+OMR JIT Compilation
 
network ram parallel computing
network ram parallel computingnetwork ram parallel computing
network ram parallel computing
 
Parallel computing(1)
Parallel computing(1)Parallel computing(1)
Parallel computing(1)
 
Introduction to parallel_computing
Introduction to parallel_computingIntroduction to parallel_computing
Introduction to parallel_computing
 
VLSI Design(Fabrication)
VLSI Design(Fabrication)VLSI Design(Fabrication)
VLSI Design(Fabrication)
 
Parallel computing
Parallel computingParallel computing
Parallel computing
 
Parallel computing(2)
Parallel computing(2)Parallel computing(2)
Parallel computing(2)
 
Parallel processing
Parallel processingParallel processing
Parallel processing
 
Parallel Algorithms
Parallel AlgorithmsParallel Algorithms
Parallel Algorithms
 
Parallel Algorithms
Parallel AlgorithmsParallel Algorithms
Parallel Algorithms
 
0 introduction to computer architecture
0 introduction to computer architecture0 introduction to computer architecture
0 introduction to computer architecture
 
Parallel Computing
Parallel ComputingParallel Computing
Parallel Computing
 
Applications of paralleL processing
Applications of paralleL processingApplications of paralleL processing
Applications of paralleL processing
 
Parallel processing Concepts
Parallel processing ConceptsParallel processing Concepts
Parallel processing Concepts
 
Introduction to parallel processing
Introduction to parallel processingIntroduction to parallel processing
Introduction to parallel processing
 
Parallel computing
Parallel computingParallel computing
Parallel computing
 
Parallel Algorithms Advantages and Disadvantages
Parallel Algorithms Advantages and DisadvantagesParallel Algorithms Advantages and Disadvantages
Parallel Algorithms Advantages and Disadvantages
 
Parallel algorithms
Parallel algorithmsParallel algorithms
Parallel algorithms
 

Similar a Higher nab preparation

BASIC COMPUTER ARCHITECTURE
BASIC COMPUTER ARCHITECTURE BASIC COMPUTER ARCHITECTURE
BASIC COMPUTER ARCHITECTURE
Himanshu Sharma
 
13. Computer Systems Input And Output Architecture
13. Computer Systems   Input And  Output Architecture13. Computer Systems   Input And  Output Architecture
13. Computer Systems Input And Output Architecture
New Era University
 
ITBIS105 6
ITBIS105 6ITBIS105 6
ITBIS105 6
Suad 00
 

Similar a Higher nab preparation (20)

Unit 5 multi-board system
Unit 5 multi-board systemUnit 5 multi-board system
Unit 5 multi-board system
 
Chapter04
Chapter04Chapter04
Chapter04
 
Ch # 04 computer hardware
Ch # 04 computer hardware Ch # 04 computer hardware
Ch # 04 computer hardware
 
Chapter04
Chapter04Chapter04
Chapter04
 
Cpi unit 01
Cpi unit 01Cpi unit 01
Cpi unit 01
 
A+ certification (Core hardware) Pc Maintenance
 A+ certification (Core hardware) Pc Maintenance  A+ certification (Core hardware) Pc Maintenance
A+ certification (Core hardware) Pc Maintenance
 
Itc lec 3 Ip cycle , system unit, interface
Itc lec 3 Ip cycle , system unit, interfaceItc lec 3 Ip cycle , system unit, interface
Itc lec 3 Ip cycle , system unit, interface
 
CH03-COA10e_ComputerFun5656565656565ction.pdf
CH03-COA10e_ComputerFun5656565656565ction.pdfCH03-COA10e_ComputerFun5656565656565ction.pdf
CH03-COA10e_ComputerFun5656565656565ction.pdf
 
Chapter04 system unit
Chapter04 system unitChapter04 system unit
Chapter04 system unit
 
BASIC COMPUTER ARCHITECTURE
BASIC COMPUTER ARCHITECTURE BASIC COMPUTER ARCHITECTURE
BASIC COMPUTER ARCHITECTURE
 
13. Computer Systems Input And Output Architecture
13. Computer Systems   Input And  Output Architecture13. Computer Systems   Input And  Output Architecture
13. Computer Systems Input And Output Architecture
 
Hardware and software of computer
Hardware and software of computerHardware and software of computer
Hardware and software of computer
 
Motherboard components and their functions
Motherboard components and their functionsMotherboard components and their functions
Motherboard components and their functions
 
Computer Power Point Presentation
Computer Power Point PresentationComputer Power Point Presentation
Computer Power Point Presentation
 
Input output in computer Orgranization and architecture
Input output in computer Orgranization and architectureInput output in computer Orgranization and architecture
Input output in computer Orgranization and architecture
 
Chapter04
Chapter04Chapter04
Chapter04
 
Multimedia Technology
Multimedia TechnologyMultimedia Technology
Multimedia Technology
 
ITBIS105 6
ITBIS105 6ITBIS105 6
ITBIS105 6
 
Data conversion
Data conversionData conversion
Data conversion
 
Computer architecture instruction formats
Computer architecture instruction formatsComputer architecture instruction formats
Computer architecture instruction formats
 

Último

Activity 01 - Artificial Culture (1).pdf
Activity 01 - Artificial Culture (1).pdfActivity 01 - Artificial Culture (1).pdf
Activity 01 - Artificial Culture (1).pdf
ciinovamais
 
Kisan Call Centre - To harness potential of ICT in Agriculture by answer farm...
Kisan Call Centre - To harness potential of ICT in Agriculture by answer farm...Kisan Call Centre - To harness potential of ICT in Agriculture by answer farm...
Kisan Call Centre - To harness potential of ICT in Agriculture by answer farm...
Krashi Coaching
 
Ecosystem Interactions Class Discussion Presentation in Blue Green Lined Styl...
Ecosystem Interactions Class Discussion Presentation in Blue Green Lined Styl...Ecosystem Interactions Class Discussion Presentation in Blue Green Lined Styl...
Ecosystem Interactions Class Discussion Presentation in Blue Green Lined Styl...
fonyou31
 

Último (20)

Measures of Dispersion and Variability: Range, QD, AD and SD
Measures of Dispersion and Variability: Range, QD, AD and SDMeasures of Dispersion and Variability: Range, QD, AD and SD
Measures of Dispersion and Variability: Range, QD, AD and SD
 
Student login on Anyboli platform.helpin
Student login on Anyboli platform.helpinStudent login on Anyboli platform.helpin
Student login on Anyboli platform.helpin
 
Grant Readiness 101 TechSoup and Remy Consulting
Grant Readiness 101 TechSoup and Remy ConsultingGrant Readiness 101 TechSoup and Remy Consulting
Grant Readiness 101 TechSoup and Remy Consulting
 
INDIA QUIZ 2024 RLAC DELHI UNIVERSITY.pptx
INDIA QUIZ 2024 RLAC DELHI UNIVERSITY.pptxINDIA QUIZ 2024 RLAC DELHI UNIVERSITY.pptx
INDIA QUIZ 2024 RLAC DELHI UNIVERSITY.pptx
 
Software Engineering Methodologies (overview)
Software Engineering Methodologies (overview)Software Engineering Methodologies (overview)
Software Engineering Methodologies (overview)
 
BAG TECHNIQUE Bag technique-a tool making use of public health bag through wh...
BAG TECHNIQUE Bag technique-a tool making use of public health bag through wh...BAG TECHNIQUE Bag technique-a tool making use of public health bag through wh...
BAG TECHNIQUE Bag technique-a tool making use of public health bag through wh...
 
General AI for Medical Educators April 2024
General AI for Medical Educators April 2024General AI for Medical Educators April 2024
General AI for Medical Educators April 2024
 
social pharmacy d-pharm 1st year by Pragati K. Mahajan
social pharmacy d-pharm 1st year by Pragati K. Mahajansocial pharmacy d-pharm 1st year by Pragati K. Mahajan
social pharmacy d-pharm 1st year by Pragati K. Mahajan
 
Mattingly "AI & Prompt Design: Structured Data, Assistants, & RAG"
Mattingly "AI & Prompt Design: Structured Data, Assistants, & RAG"Mattingly "AI & Prompt Design: Structured Data, Assistants, & RAG"
Mattingly "AI & Prompt Design: Structured Data, Assistants, & RAG"
 
Activity 01 - Artificial Culture (1).pdf
Activity 01 - Artificial Culture (1).pdfActivity 01 - Artificial Culture (1).pdf
Activity 01 - Artificial Culture (1).pdf
 
Kisan Call Centre - To harness potential of ICT in Agriculture by answer farm...
Kisan Call Centre - To harness potential of ICT in Agriculture by answer farm...Kisan Call Centre - To harness potential of ICT in Agriculture by answer farm...
Kisan Call Centre - To harness potential of ICT in Agriculture by answer farm...
 
Measures of Central Tendency: Mean, Median and Mode
Measures of Central Tendency: Mean, Median and ModeMeasures of Central Tendency: Mean, Median and Mode
Measures of Central Tendency: Mean, Median and Mode
 
microwave assisted reaction. General introduction
microwave assisted reaction. General introductionmicrowave assisted reaction. General introduction
microwave assisted reaction. General introduction
 
Paris 2024 Olympic Geographies - an activity
Paris 2024 Olympic Geographies - an activityParis 2024 Olympic Geographies - an activity
Paris 2024 Olympic Geographies - an activity
 
Explore beautiful and ugly buildings. Mathematics helps us create beautiful d...
Explore beautiful and ugly buildings. Mathematics helps us create beautiful d...Explore beautiful and ugly buildings. Mathematics helps us create beautiful d...
Explore beautiful and ugly buildings. Mathematics helps us create beautiful d...
 
Ecosystem Interactions Class Discussion Presentation in Blue Green Lined Styl...
Ecosystem Interactions Class Discussion Presentation in Blue Green Lined Styl...Ecosystem Interactions Class Discussion Presentation in Blue Green Lined Styl...
Ecosystem Interactions Class Discussion Presentation in Blue Green Lined Styl...
 
Disha NEET Physics Guide for classes 11 and 12.pdf
Disha NEET Physics Guide for classes 11 and 12.pdfDisha NEET Physics Guide for classes 11 and 12.pdf
Disha NEET Physics Guide for classes 11 and 12.pdf
 
Holdier Curriculum Vitae (April 2024).pdf
Holdier Curriculum Vitae (April 2024).pdfHoldier Curriculum Vitae (April 2024).pdf
Holdier Curriculum Vitae (April 2024).pdf
 
Key note speaker Neum_Admir Softic_ENG.pdf
Key note speaker Neum_Admir Softic_ENG.pdfKey note speaker Neum_Admir Softic_ENG.pdf
Key note speaker Neum_Admir Softic_ENG.pdf
 
Interactive Powerpoint_How to Master effective communication
Interactive Powerpoint_How to Master effective communicationInteractive Powerpoint_How to Master effective communication
Interactive Powerpoint_How to Master effective communication
 

Higher nab preparation

  • 1. Higher Computing NAB REVISION
  • 2.
  • 3.
  • 4.
  • 5. Table of Bit Depth 2 4 = 16 colours 2 8 = 256 colours 2 16 = 65,536 colours True Colour 2 24 = 16,777,216 colours
  • 6.
  • 7.
  • 8. Processor Structure Control ALU Registers Cache Main Memory Backing Storage Address bus Data bus Control bus
  • 9.
  • 10.
  • 11. Memory Read Operation Cache Main Memory Backing Storage Address bus Data bus Address bus loaded with address of the required memory location The processor activates the READ line on the control bus READ line activated CONTROL BUS The contents of the memory location are transferred along the data bus into the processor If it is an instruction, it is DECODED and EXECUTED in the processor FETCH/EXECUTE CYCLE ***Use arrow keys to control animations*** Control ALU Registers
  • 12.
  • 13. Memory Write Operation Cache Main Memory Backing Storage Address bus Data bus WRITE line activated CONTROL BUS FETCH/EXECUTE CYCLE ***Use arrow keys to control animations*** The processor sets up the address bus with the address of the required memory location The processor sets up the data bus with the data to be written to memory The processor activates the WRITE line on the Control Bus The data is transferred along the data bus to the memory location Control ALU Registers
  • 14.
  • 15.
  • 16.
  • 17. Buffer Laser Printer Data to be printed is sent by the FAST processor to the SLOWER functioning printer Buffer Data is stored in the Buffer until the printer is ready to print it. When the printer has ‘caught up’ it requests the data to be printed from the Buffer ***Use arrow keys to control animations*** Not suitable for Network Printing Computer System
  • 18. Spooling Laser Printer File to be printed PROCESSOR HARD DISK Stored temporarily here ***Use arrow keys to control animations*** Suitable for Network Printing
  • 19. Parallel Interfaces Many bits are send down parallel lines – faster than serial transmission ***Use arrow keys to control animations*** 0 1 0 1 0 1 1
  • 20. Serial Transmission 0 One bit is sent down a single line – slower, but more robust than parallel ***Use arrow keys to control animations***
  • 21. Client/Server Network All data goes through the central SERVER CLIENT CLIENT CLIENT CLIENT CLIENT SERVER
  • 22. Peer to Peer Network Want to send a file from one computer to another? The file will go from computer to computer on the network until it reaches its destination. Computer 2 Computer 1 Computer 4 Computer 3
  • 23. Routers/Hubs/Switches A Hub splits a signal down 2 or more channels. Hubs split the signals ‘blindly’ whilst Switches forward data packets down the exact channels more intelligently HUB/SWITCH Network 1 Network 2 Router A router sends data packets between different networks using the Internet Protocol (IP) ROUTER ***Use arrow keys to control animations***
  • 24.
  • 25.
  • 26.
  • 27.
  • 28.
  • 29.
  • 30.
  • 31.
  • 32.
  • 33.