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Contemporary Logic Design
Finite State Machine Design

Chapter #8: Finite State Machine Design

Randy H. Katz
University of California, Berkeley

June 1993

© R.H. Katz Transparency No. 8-1

Motivatio Finite State Machine Design
n

• Counters: Sequential Circuits where State = Output

• Generalizes to Finite State Machines:
Outputs are Function of State (and Inputs)
Next States are Functions of State and Inputs
Used to implement circuits that control other circuits
"Decision Making" logic

• Application of Sequential Logic Design Techniques
Word Problems
Mapping into formal representations of FSM behavior
Case Studies


Chapter Overview Finite State Machine Design

Concept of the State Machine

• Partitioning into Datapath and Control

• When Inputs are Sampled and Outputs Asserted

Basic Design Approach

• Six Step Design Process

Alternative State Machine Representations

• State Diagram, ASM Notation, VHDL, ABEL Description Language

Moore and Mealy Machines

• Definitions, Implementation Examples

Word Problems

• Case Studies

Concept of the State Finite State Machine Design
Machine
Computer Hardware = Datapath + Control

Qualifiers
Registers FSM generating sequences
Combinational Functional of control signals
Units (e.g., ALU) Instructs datapath what to
Busses do next
Control

Control "Puppeteer who pulls the
strings"
State

Qualifiers Control
and Signal
Inputs Outputs

"Puppet" Datapath


Machine
Example: Odd Parity Checker
Assert output whenever input bit stream has odd # of 1's

Reset Present State Input Next State Output
Even 0 Even 0
0 Even 1 Odd 0
Even
[0]
Odd 0 Odd 1
Odd 1 Even 1
1 1 Symbolic State Transition Table
Odd
[1] Present State Input Next State Output
0
0 0 0 0
0 1 1 0
1 0 1 1
State 1 1 0 1
Diagram
Encoded State Transition Table


Machine
Example: Odd Parity Checker
Next State/Output Functions
NS = PS xor PI; OUT = PS

Input Output
NS T Q
Input CLK
D Q
PS/Output
CLK Q
Q R
R
Reset Reset

D FF Implementation T FF Implementation

Input 1 0 0 1 1 0 1 0 1 1 1 0

Clk

Output 1 1 1 0 1 1 0 0 1 0 1 1

Timing Behavior: Input 1 0 0 1 1 0 1 0 1 1 1 0

Concept of State Finite State Machine Design
Machine
Timing:
When are inputs sampled, next state computed, outputs asserted?

State Time: Time between clocking events

• Clocking event causes state/outputs to transition, based on inputs

• For set-up/hold time considerations:

Inputs should be stable before clocking event

• After propagation delay, Next State entered, Outputs are stable

NOTE: Asynchronous signals take effect immediately
Synchronous signals take effect at the next clocking event

E.g., tri-state enable: effective immediately
sync. counter clear: effective at next clock event


Concept of State Finite State Machine Design
Machine
Example: Positive Edge Triggered Synchronous System

State Time On rising edge, inputs sampled
outputs, next state computed

After propagation delay, outputs and
next state are stable
Clock
Immediate Outputs:
affect datapath immediately
Inputs could cause inputs from datapath to change

Delayed Outputs:
take effect on next clock edge
Outputs propagation delays must exceed hold times


Machine
Communicating State Machines
One machine's output is another machine's input

X
CLK
FSM 1 FSM 2
Y
FSM1 A A B

X
Y=0 X=0
Y=0 X=0
A C FSM2 C D D
[1] [0]

X=1 Y
Y=1
X=1

B D
Y=0,1 [0] X=0 [1]

Machines advance in lock step

Initial inputs/outputs: X = 0, Y = 0

Basic Design Approach Finite State Machine Design
Six Step Process

1. Understand the statement of the Specification

2. Obtain an abstract specification of the FSM

3. Perform a state mininimization

4. Perform state assignment

5. Choose FF types to implement FSM state register

6. Implement the FSM

1, 2 covered now; 3, 4, 5 covered later;
4, 5 generalized from the counter design procedure


Basic Design Approach Finite State Machine Design
Example: Vending Machine FSM
General Machine Concept:
deliver package of gum after 15 cents deposited

single coin slot for dimes, nickels

no change

Step 1. Understand the problem:
Draw a picture!

Block Diagram N
Coin
Vending Open Gum
Sensor D
Machine Release
Reset FSM Mechanism

Clk


Vending Machine Finite State Machine Design
Example
Step 2. Map into more suitable abstract representation

Tabulate typical input sequences:
three nickels
nickel, dime
dime, nickel Reset
two dimes S0
two nickels, dime
N D
Draw state diagram:
S1 S2
Inputs: N, D, reset

Output: open N D
D N

S3 S4 S5 S6

[open] [open] [open]
N D

S7 S8
[open] [open]


Example
Step 3: State Minimization
Present Inputs Next Output
Reset
0¢
State D N State Open
0¢ 0 0 0¢ 0
N 0 1 5¢ 0
5¢
1 0 10¢ 0
D 1 1 X X
5¢ 0 0 5¢ 0
N 0 1 10¢ 0
10¢ 1 0 15¢ 0
D 1 1 X X
N, D 10¢ 0 0 10¢ 0
0 1 15¢ 0
15¢
1 0 15¢ 0
[open]
1 1 X X
15¢ X X 15¢ 1
reuse states
whenever Symbolic State Table
possible


Example
Step 4: State Encoding
Present State Inputs Next State Output
Q1 Q0 D N D1 D0 Open
0 0 0 0 0 0 0
0 1 0 1 0
1 0 1 0 0
1 1 X X X
0 1 0 0 0 1 0
0 1 1 0 0
1 0 1 1 0
1 1 X X X
1 0 0 0 1 0 0
0 1 1 1 0
1 0 1 1 0
1 1 X X X
1 1 0 0 1 1 1
0 1 1 1 1
1 0 1 1 1
1 1 X X X


Example
Step 5. Choose FFs for implementation
D FF easiest to use
Q1 Q1 Q1
Q1 Q0 Q1 Q0 Q1 Q0
DN DN DN

N N N
D D D

Q0 Q0 Q0
K-map for D1 K-map for D0 K-map for Open
Q1
D D1 D Q Q1

Q0
CLK
RQ
Q1
D1 = Q1 + D + Q0 N
N
reset
N
Q0 OPEN D0 = N Q0 + Q0 N + Q1 N + Q1 D
Q0
N D0
D Q
Q0 OPEN = Q1 Q0
Q1 CLK Q0
N RQ
Q1 reset
D 8 Gates

Example
Step 5. Choosing FF for Implementation
J-K FF

Present State Inputs Next State J1 K1 J0 K 0
Q1 Q0 D N D 1 D0
0 0 0 0 0 0 0 X 0 X
0 1 0 1 0 X 1 X
1 0 1 0 1 X 0 X
1 1 X X X X X X
0 1 0 0 0 1 0 X X 0
0 1 1 0 1 X X 1
1 0 1 1 1 X X 0
1 1 X X X X X X
1 0 0 0 1 0 X 0 0 X
0 1 1 1 X 0 1 X
1 0 1 1 X 0 1 X
1 1 X X X X X X
1 1 0 0 1 1 X 0 X 0
0 1 1 1 X 0 X 0
1 0 1 1 X 0 X 0
1 1 X X X X X X

Remapped encoded state transition table

Example
Implementation:
Q1 Q1
Q1 Q0 Q1 Q0
DN DN J1 = D + Q0 N

K1 = 0
N N
D D
J0 = Q0 N + Q1 D
Q0 Q0
K-map for J1 K-map for K1
K0 = Q1 N
Q1 Q1
Q1 Q0 Q1 Q0
DN DN

N
N N Q0 J Q1
Q
D D D Q1
CLK K Q
Q0 R

Q0 Q0 N
K-map for J0 K-map for K0 OPEN
Q1

D Q0
J Q
Q1 CLK
Q0
KR Q
N

reset 7 Gates

Alternative State Machine Representations Finite State Machine Design
Why State Diagrams Are Not Enough
Not flexible enough for describing very complex finite state machines

Not suitable for gradual refinement of finite state machine

Do not obviously describe an algorithm: that is, well specified
sequence of actions based on input data

algorithm = sequencing + data manipulation

separation of control and data

Gradual shift towards program-like representations:

• Algorithmic State Machine (ASM) Notation

• Hardware Description Languages (e.g., VHDL)


Algorithmic State Machine (ASM) Notation
Three Primitive Elements:

• State Box

• Decision Box State
Entry Path

• Output Box State Code
* ***
State Machine in one state State State Box
block per state time Name
State ASM
Output List
Single Entry Point T F
Block
Condition

Unambiguous Exit Path
for each combination Condition Output
Box
of inputs Box
Conditional
Output List
Outputs asserted high (.H)
or low (.L); Immediate (I) Exits to
other ASM Blocks
or delayed til next clock


ASM Notation
Condition Boxes:
Ordering has no effect on final outcome

Equivalent ASM charts:
A exits to B on (I0 • I1) else exit to C

A 010 A 010

F F
I0 I1
T T
F F
I1 I0

T T

B C B C


Example: Parity Checker
Input X, Output Z
Even 0
Nothing in output list implies Z not asserted

Z asserted in State Odd
F
X Symbolic State Table:
T
Present Next
Input State State Output
Odd 1 F Even Even —
H.Z T Even Odd —
F Odd Odd A
T Odd Even A
F T
X
Encoded State Table:
Present Next
Input State State Output
Trace paths to derive 0 0 0 0
state transition tables 1 0 1 0
0 1 1 1
1 1 0 1


ASM Chart for Vending Machine

0¢ 00 10¢ 10

T T
D D
F F
F F
N N
T T

5¢ 01 15¢ 11
H.Open

T F
N Reset
F T
F T
D 0¢


Hardware Description Languages: VHDL
ENTITY parity_checker IS
PORT (
x, clk: IN BIT; Interface Description
z: OUT BIT);
END parity_checker; Architectural Body
ARCHITECTURE behavioral OF parity_checker IS
BEGIN
main: BLOCK (clk = ‘1’ and not clk’STABLE)

TYPE state IS (Even, Odd);
SIGNAL state_register: state := Even; Guard Expression
BEGIN state_even:
BLOCK ((state_register = Even) AND GUARD)
BEGIN
state_register <= Odd WHEN x = ‘1’
ELSE Even
END BLOCK state_even;
Determine New State
BEGIN state_odd:
BLOCK ((state_register = Odd) AND GUARD)
BEGIN
state_register <= Even WHEN x = ‘1’
ELSE Odd;
END BLOCK state_odd;

z <= ‘0’ WHEN state_register = Even ELSE Determine Outputs
‘1’ WHEN state_register = Odd;
END BLOCK main;
END behavioral;

ABEL Hardware Description Language
module parity test_vectors ([clk, RESET, X] -> [SREG])
title 'odd parity checker state machine' [0,1,.X.] -> [S0];
u1 device 'p22v10'; [.C.,0,1] -> [S1];
[.C.,0,1] -> [S0];
"Input Pins [.C.,0,1] -> [S1];
clk, X, RESET pin 1, 2, 3; [.C.,0,0] -> [S1];
[.C.,0,1] -> [S0];
"Output Pins [.C.,0,1] -> [S1];
Q, Z pin 21, 22; [.C.,0,0] -> [S1];
[.C.,0,0] -> [S1];
Q, Z istype 'pos,reg'; [.C.,0,0] -> [S1];
end parity;
"State registers
SREG = [Q, Z];
S0 = [0, 0]; " even number of 0's
S1 = [1, 1]; " odd number of 0's

equations
[Q.ar, Z.ar] = RESET; "Reset to state S0

state_diagram SREG
state S0:
if X then S1
else S0;
state S1:
if X then S0
else S1;


Moore and Mealy Machine Design Procedure Finite State Machine Design
Definitions
Mealy Machine
Xi Zk Outputs depend on
Inputs Combinational Outputs
Logic for
state AND inputs
Outputs and
Next State Input change causes
an immediate output
State change
State Register Clock Feedback
Asynchronous signals

State
Register
Moore Machine
Xi Comb.
Combinational
Inputs Logic for
Logic for Outputs are function
Outputs
Next State solely of the current
(Flip-flop Zk state
Inputs) Outputs

Clock Outputs change
synchronously with
state changes
state
feedback


Moore and Mealy Finite State Machine Design
Machines
State Diagram Equivalents

N D + Reset
Mealy Reset/0
(N D + Reset)/0
Reset Moore
Machine 0¢ 0¢ Machine
[0]
Reset/0 Reset
N/0 N

5¢ 5¢
N D/0 D/0 ND D
[0]

N/0 N

10¢ 10¢
D/1 D
N D/0 [0] ND
N+D/1 N+D

15¢ 15¢

[1] Reset
Reset/1

Outputs are associated Outputs are associated
with Transitions with State


Machines vs. Transitions
States
Mealy Machine typically has fewer states than Moore Machine
for same output sequence
0
0 0/0
0
Same I/O behavior:
Assert a single output [0]
1/0
0/0
whenever at least two 1’s 0 1
0 1
have been received in a 1

sequence. [0]
1/1

1
Different # of states 2

[1] 1

S0 00 S0 0

IN IN

S1 01 S1 1
Equivalent
ASM Charts
IN IN

S2 10
H.OUT H.OUT

IN

Machines
Timing Behavior of Moore Machines
Reverse engineer the following:

X J Q A Input X
C Output Z
X
KR Q A State A, B = Z
B
FFa
Reset

Clk

X J Q Z
X C
KR Q B
A
FFb
Reset

Two Techniques for Reverse Engineering:

• Ad Hoc: Try input combinations to derive transition table

• Formal: Derive transition by analyzing the circuit

Machines
Ad Hoc Reverse Engineering
Behavior in response to input sequence 1 0 1 0 1 0:
100

X
Clk
A
Z
Reset
Reset X =1 X =0 X =1 X=0 X =1 X=0 X=0
AB = 00 AB = 00 AB = 11 AB = 11 AB = 10 AB = 10 AB = 01 AB = 00

A B X A+ B+ Z
0 0 0 ? ? 0
1 1 1 0
0 1 0 0 0 1
Partially Derived 1 ? ? 1
State Transition 1 0 0 1 0 0
Table 1 0 1 0
1 1 0 1 1 1
1 1 0 1


Machines
Formal Reverse Engineering
Derive transition table from next state and output combinational
functions presented to the flipflops!

Ja = X Ka = X • B Z=B
Jb = X Kb = X xor A

FF excitation equations for J-K flipflop:
A+ = Ja • A + Ka • A = X • A + (X + B) • A
B+ = Jb • B + Kb • B = X • B + (X • A + X • A) • B

Next State K-Maps:
AB
00 01 11 10
X
0 1 1
A+
State 00, Input 0 -> State 00
1 1 1 1 State 01, Input 1 -> State 11
AB
X 00 01 11 10
0 1
B+
1 1 1 1

Machines ASM Chart for the Mystery Moore Machine
Complete

S0 00 S3 11
H.Z

0 1 0
X X
1
S1 01 S2 10
H.Z

0 1 1 0
X X

Note: All Outputs Associated With State Boxes
No Separate Output Boxes — Intrinsic in Moore Machines


Machines Engineering a Mealy Machine
Reverse

Clk
A
X
A B
D Q J Q
DA A C B
C X
R Q KR Q

Reset Reset

A
DA X
X
B
B Z
X X
A

Input X, Output Z, State A, B
State register consists of D FF and J-K FF

Machine Method
Ad Hoc
Signal Trace of Input Sequence 101011:
100

X Note glitches
Clk in Z!
A Outputs valid at
B following falling
clock edge
Z

Reset
Reset X =1 X =0 X =1 X =0 X =1 X =1
AB =00 AB =00 AB =00 AB =01 AB =11 AB =10 AB =01
Z =0 Z =0 Z =0 Z =0 Z=1 Z =1 Z =0

A B X A+ B+ Z
0 0 0 0 1 0
Partially completed 1 0 0 0
state transition table 0 1 0 ? ? ?
based on the signal 1 1 1 0
trace 1 0 0 ? ? ?
1 0 1 1
1 1 0 1 0 1
1 ? ? ?

Machines Method
Formal
A+ = B • (A + X) = A • B + B • X

B+ = Jb • B + Kb • B = (A xor X) • B + X • B

=A•B•X + A•B•X + B•X

Z =A•X + B•X
Missing Transitions and Outputs:
AB
X 00 01 11 10 State 01, Input 0 -> State 00, Output 1
0 1 State 10, Input 0 -> State 00, Output 0
A+ State 11, Input 1 -> State 11, Output 1
1 1 1

AB
X 00 01 11 10
0 1
B+
1 1 1 1

AB
X 00 01 11 10
0 1 1
Z
1 1 1

Machines
ASM Chart for Mystery Mealy Machine
S0 = 00, S1 = 01, S2 = 10, S3 = 11

S0 00 S2 10

0
1 X
X
1
0 H. Z

S1 01 S3 11
H. Z
H.Z

0 1 1
X X
0

NOTE: Some Outputs in Output Boxes as well as State Boxes
This is intrinsic in Mealy Machine implementation


Machines
Synchronous Mealy Machine

Clock

Xi Zk
Inputs Combinational
Outputs
Logic for
Outputs and
Next State

State Register Clock state
feedback

latched state AND outputs

avoids glitchy outputs!


Finite State Machine Word Finite State Machine Design
Problems
Mapping English Language Description to Formal Specifications

Four Case Studies:

• Finite String Pattern Recognizer

• Complex Counter with Decision Making

• Traffic Light Controller

• Digital Combination Lock

We will use state diagrams and ASM Charts


Problems
Finite String Pattern Recognizer
A finite string recognizer has one input (X) and one output (Z).
The output is asserted whenever the input sequence …010…
has been observed, as long as the sequence 100 has never been
seen.

Step 1. Understanding the problem statement

Sample input/output behavior:
X: 00101010010…
Z: 00010101000…

X: 11011010010…
Z: 00000001000…


Problems
Finite String Recognizer
Step 2. Draw State Diagrams/ASM Charts for the strings that must be
recognized. I.e., 010 and 100.

Reset
S0
[0] Moore State Diagram
0 1
Reset signal places
S1 S4 FSM in S0
[0] [0]
1 0
S2 S5
[0] [0]
0 0
0,1
S3 S6
Outputs 1 Loops in State
[1] [0]


Problems
Exit conditions from state S3: have recognized …010
if next input is 0 then have …0100!
if next input is 1 then have …0101 = …01 (state S2)

Reset
S0
[0]
0 1
S1 0 S4
[0] [0]
1 0
S2 S5
[0] [0]
0 0
1 0,1
S3 0 S6
[1] [0]


Problems
Exit conditions from S1: recognizes strings of form …0 (no 1 seen)
loop back to S1 if input is 0

Exit conditions from S4: recognizes strings of form …1 (no 0 seen)
loop back to S4 if input is 1

Reset
S0
[0]
0 1
0
S1 0 S4 1
[0] [0]
1 0
S2 S5
[0] [0]
0 0
1 0,1
S3 0 S6
[1] [0]


Problems
S2, S5 with incomplete transitions

S2 = …01; If next input is 1, then string could be prefix of (01)1(00)
S4 handles just this case!

S5 = …10; If next input is 1, then string could be prefix of (10)1(0)
S2 handles just this case!
Reset
S0
[0]
0 1
0
S1 0 S4 1
[0] [0]
Final State Diagram
1 1 0
S2 1 S5
[0] [0]
0 0
1 0,1
S3 0 S6
[1] [0]


Problems

module string state_diagram SREG
title '010/100 string recognizer state machine state S0: if X then S4 else S1;
Josephine Engineer, Itty Bity Machines, Inc.' state S1: if X then S2 else S1;
u1 device 'p22v10'; state S2: if X then S4 else S3;
state S3: if X then S2 else S6;
"Input Pins state S4: if X then S4 else S5;
clk, X, RESET pin 1, 2, 3; state S5: if X then S2 else S6;
state S6: goto S6;
"Output Pins
Q0, Q1, Q2, Z pin 19, 20, 21, 22; test_vectors ([clk, RESET, X] -> [Z]
[0,1,.X.] -> [0];
Q0, Q1, Q2, Z istype 'pos,reg'; [.C.,0,0] -> [0];
[.C.,0,0] -> [0];
"State registers [.C.,0,1] -> [0];
SREG = [Q0, Q1, Q2, Z]; [.C.,0,0] -> [1];
S0 = [0,0,0,0]; " Reset state [.C.,0,1] -> [0];
S1 = [0,0,1,0]; " strings of the form ...0 [.C.,0,0] -> [1];
end string;
equations
[Q0.ar, Q1.ar, Q2.ar, Z.ar] = RESET; "Reset to S0

ABEL Description

Problems
Review of Process:

• Write down sample inputs and outputs to understand specification

• Write down sequences of states and transitions for the sequences
to be recognized

• Add missing transitions; reuse states as much as possible

• Verify I/O behavior of your state diagram to insure it functions
like the specification


Problems Counter
Complex
A sync. 3 bit counter has a mode control M. When M = 0, the counter
counts up in the binary sequence. When M = 1, the counter advances
through the Gray code sequence.

Binary: 000, 001, 010, 011, 100, 101, 110, 111
Gray: 000, 001, 011, 010, 110, 111, 101, 100

Valid I/O behavior:
Mode Input M Current State Next State (Z2 Z1 Z0)
0 000 001
0 001 010
1 010 110
1 110 111
1 111 101
0 101 110
0 110 111


Problems Counter
Complex
One state for each output combination
Add appropriate arcs for the mode control
S0 000
Reset
S0
[000]
M=0 S1 001
M=1 S1
H.Z 0

[001]
0 1
M=0 M

M=1 M=1 S2
[010] S2 010 S3 011
H.Z 1 H.Z 1
M=1 M=0 H.Z 0

S3 0
M
[011] M=0 1
1
M

M=0 S6 110
0
S4 H.Z 2 S4 100
[100] H.Z 1 H.Z 2

M=1 M=0 1
S5 S7 111 M
[101] H.Z 2 0
H.Z 1
M=0 H.Z 0
S5 101
M=1 S6 H.Z 2
H.Z 0
[110] 0 1
M
M=1 M=0 0 1
S7 M
[111]

Problems Counter
Complex

module counter
title 'combination binary/gray code upcounter
Josephine Engineer, Itty Bity Machines, Inc.'
u1 device 'p22v10';
state_diagram SREG
"Input Pins state S0: goto S1;
clk, M, RESET pin 1, 2, 3; state S1: if M then S3 else S2;
state S2: if M then S6 else S3;
"Output Pins state S3: if M then S2 else S4;
Z0, Z1, Z2 pin 19, 20, 21; state S4: if M then S0 else S5;
Z0, Z1, Z2 istype 'pos,reg'; state S6: goto S7;
"State registers
SREG = [Z0, Z1, Z2]; test_vectors ([clk, RESET, M] -> [Z0, Z1, Z2])
S0 = [0,0,0]; [0,1,.X.] -> [0,0,0];
S1 = [0,0,1]; [.C.,0,0] -> [0,0,1];
S2 = [0,1,0]; [.C.,0,0] -> [0,1,0];
S3 = [0,1,1]; [.C.,0,1] -> [1,1,0];
S4 = [1,0,0]; [.C.,0,1] -> [1,1,1];
S5 = [1,0,1]; [.C.,0,1] -> [1,0,1];
S6 = [1,1,0]; [.C.,0,0] -> [1,1,0];
S7 = [1,1,1]; [.C.,0,0] -> [1,1,1];
end counter;
equations
[Z0.ar, Z1.ar, Z2.ar] = RESET; "Reset to state S0

ABEL Description

Problems
Traffic Light Controller
A busy highway is intersected by a little used farmroad. Detectors
C sense the presence of cars waiting on the farmroad. With no car
on farmroad, lights remain green in highway direction. If vehicle on
farmroad, highway lights go from Green to Yellow to Red, allowing
the farmroad lights to become green. These stay green only as long
as a farmroad car is detected but never longer than a set interval.
When these are met, farm lights transition from Green to Yellow to
Red, allowing highway to return to green. Even if farmroad vehicles
are waiting, highway gets at least a set interval as green.

Assume you have an interval timer that generates a short time pulse
(TS) and a long time pulse (TL) in response to a set (ST) signal. TS
is to be used for timing yellow lights and TL for green lights.
Farmroad

C
HL
FL
Highway

Highway

FL
HL C

Farmroad

Problems
Picture of Highway/Farmroad Intersection:

Farmroad

C
HL
FL
Highway

Highway
FL
HL C

Farmroad


Problems
• Tabulation of Inputs and Outputs:
Input Signal Description
reset place FSM in initial state
C detect vehicle on farmroad
TS short time interval expired
TL long time interval expired

Output Signal Description
HG, HY, HR assert green/yellow/red highway lights
FG, FY, FR assert green/yellow/red farmroad lights
ST start timing a short or long interval

• Tabulation of Unique States: Some light configuration imply others
State Description
S0 Highway green (farmroad red)
S1 Highway yellow (farmroad red)
S2 Farmroad green (highway red)
S3 Farmroad yellow (highway red)


Problems
Refinement of ASM Chart:
Start with basic sequencing and outputs:

S0 S3
H.HG H.HR
H.FR H.FY

S1 S2
H.HY H.HR
H.FR H.FG


ProblemsLight Controller
Traffic
Determine Exit Conditions for S0:
Car waiting and Long Time Interval Expired- C • TL

S0 S0
H.HG H.HG
H.FR H.FR

0 0
TL TLÊ¥Ê
C

1 1
0
C H.ST

1

H.ST S1
H.HY
H.FR
S1
H.HY
H.FR

Equivalent ASM Chart Fragments

Problems
S1 to S2 Transition:
Set ST on exit from S0
Stay in S1 until TS asserted
Similar situation for S3 to S4 transition

S1 S2
H.HY H.ST H.HR
H.FR H.FG

0 1
TS


Problems
S2 Exit Condition: no car waiting OR long time interval expired

S0 S3
H.HG H.HR
H.FR H.ST H.FY

0 1 0
TL ¥ C TS

1

H.ST H.ST

S1 S2
H.HY H.ST H.HR
H.FR H.FG

0 1 0
TS TL + C
1

Complete ASM Chart for Traffic Light Controller

ProblemsLight Controller
Traffic
Compare with state diagram:
TL + C
Reset
S0
TL¥C/ST TS/ST S0: HG
TS
S1 S3 S1: HY

TS/ST TS S2: FG
TL + C/ST
S2 S3: FY

TL ¥ C

Advantages of State Charts:

• Concentrates on paths and conditions for exiting a state

• Exit conditions built up incrementally, later combined into
single Boolean condition for exit

• Easier to understand the design as an algorithm


Problems
module traffic HY = !Q0 & Q1;
title 'traffic light FSM' HR = (Q0 & !Q1) # (Q0 & Q1);
u1 device 'p22v10'; FG = Q0 & !Q1;
FY = Q0 & Q1;
"Input Pins FR = (!Q0 & !Q1) # (!Q0 & Q1);
clk, C, RESET, TS, TL
pin 1, 2, 3, 4, 5; state_diagram SREG
state S0: if (TL & C) then S1 with ST = 1
"Output Pins else S0 with ST = 0
Q0, Q1, HG, HY, HR, state S1: if TS then S2 with ST = 1
FG, FY, FR, ST else S1 with ST = 0
pin 14, 15, 16, 17, 18, state S2: if (TL # !C) then S3 with ST = 1
19, 20, 21, 22; else S2 with ST = 0
state S3: if TS then S0 with ST = 1
Q0, Q1 istype 'pos,reg'; else S3 with ST = 0
ST, HG, HY, HR,
FG, FY, FR istype 'pos,com';test_vectors
([clk,RESET, C, TS, TL]->[SREG,HG,HY,HR,FG,FY,FR,ST])
"State registers [.X., 1,.X.,.X.,.X.]->[ S0, 1, 0, 0, 0, 0, 1, 0];
SREG = [Q0, Q1]; [.C., 0, 0, 0, 0]->[ S0, 1, 0, 0, 0, 0, 1, 0];
S0 = [ 0, 0]; [.C., 0, 1, 0, 1]->[ S1, 0, 1, 0, 0, 0, 1, 0];
S1 = [ 0, 1]; [.C., 0, 1, 0, 0]->[ S1, 0, 1, 0, 0, 0, 1, 0];
S2 = [ 1, 0]; [.C., 0, 1, 1, 0]->[ S2, 0, 0, 1, 1, 0, 0, 0];
S3 = [ 1, 1]; [.C., 0, 1, 0, 0]->[ S2, 0, 0, 1, 1, 0, 0, 0];
[.C., 0, 1, 0, 1]->[ S3, 0, 0, 1, 0, 1, 0, 0];
equations [.C., 0, 1, 1, 0]->[ S0, 1, 0, 0, 0, 0, 1, 0];
[Q0.ar, Q1.ar] = RESET; end traffic;
HG = !Q0 & !Q1;
ABEL Description

Problems
Digital Combination Lock

"3 bit serial lock controls entry to locked room. Inputs are RESET,
ENTER, 2 position switch for bit of key data. Locks generates an
UNLOCK signal when key matches internal combination. ERROR
light illuminated if key does not match combination. Sequence is:
(1) Press RESET, (2) enter key bit, (3) Press ENTER, (4) repeat (2) &
(3) two more times."

Problem specification is incomplete:
• how do you set the internal combination?
• exactly when is the ERROR light asserted?

Make reasonable assumptions:
• hardwired into next state logic vs. stored in internal register
• assert as soon as error is detected vs. wait until full combination
has been entered

Our design: registered combination plus error after full combination

Problems
Understanding the problem: draw a block diagram …
RESET

Operator Data ENTER UNLOCK
KEY-IN
Combination
Lock FSM ERROR
L0
Internal
L1
Combination
L2

Inputs: Outputs:
Reset Unlock
Enter Error
Key-In
L0, L1, L2


Problems
Enumeration of states:

what sequences lead to opening the door?
error conditions on a second pass …
START state plus three key COMParison states

START
START entered on RESET

Exit START when ENTER is pressed
1
Reset

0
Enter
0
1
COMP0

N
Continue on if Key-In matches L0
KI = L0
Y

Problems
COMP0 IDLE1

Path to unlock:

N 0
KI = L 0 Enter
Y 1
IDLE0 COMP2
Wait for
Enter Key press

0 N
Enter KI = L2

1 Y
COMP1 DONE

H.Unlock

N 0
Compare Key-IN KI = L1 Reset

Y 1

START


Problems
Now consider error paths

Should follow a similar sequence as UNLOCK path, except
asserting ERROR at the end:

IDLE0' IDLE1' ERROR3
H.Error

0 0 0
Enter Enter Reset

1 1 1
ERROR1 ERROR2

START

COMP0 error exits to IDLE0'

COMP1 error exits to IDLE1'

COMP2 error exits to ERROR3


Reset + Enter
Problems
Digital Combination Lock Reset
Start

Reset ¥ Enter

Comp0
KI = L0 KI ≠L0
¡

Enter Enter
Idle0 Idle0'

Enter Enter

Comp1 Error1
Equivalent State Diagram
KI ≠L1
¡
KI = L1
Enter
Enter
Idle1 Idle1'

Enter Enter

Comp2 Error2
≠
KI ¡ L2
KI = L2

Reset Reset
Done Error3
[Unlock] [Error]

Reset Reset

Start Start


Problems
Combination Lock
module lock
title 'comb. lock FSM' equations
u1 device 'p22v10'; [Q0.ar, Q1.ar, Q2.ar, Q3.ar] = RESET;
UNLOCK = !Q0 & Q1 & Q2 & !Q3;"asserted in DONE
"Input Pins ERROR = Q0 & !Q1 & Q2 & Q3; "asserted in ERROR3
clk, RESET, ENTER, L0, L1, L2, KI
pin 1, 2, 3, 4, 5, 6, 7; state_diagram SREG
state START: if (RESET # !ENTER)
"Output Pins then START else COMP0;
Q0, Q1, Q2, Q3, UNLOCK, ERROR state COMP0: if (KI == L0) then IDLE0 else IDLE0p;
pin 16, 17, 18, 19, 14, 15; state IDLE0: if (!ENTER) then IDLE0 else COMP1;
state COMP1: if (KI == L1) then IDLE1 else IDLE1p;
Q0, Q1, Q2, Q3 istype 'pos,reg';state IDLE1: if (!ENTER) then IDLE1 else COMP2;
UNLOCK, ERROR istype 'pos,com';state COMP2: if (KI == L2) then DONE else ERROR3;
state DONE: if (!RESET) then DONE else START;
"State registers state IDLE0p:if (!ENTER) then IDLE0p else ERROR1;
SREG = [Q0, Q1, Q2, Q3]; state ERROR1:goto IDLE1p;
START = [ 0, 0, 0, 0]; state IDLE1p:if (!ENTER) then IDLE1p else ERROR2;
COMP0 = [ 0, 0, 0, 1]; state ERROR2:goto ERROR3;
IDLE0 = [ 0, 0, 1, 0]; state ERROR3:if (!RESET) then ERROR3 else START;
COMP1 = [ 0, 0, 1, 1];
IDLE1 = [ 0, 1, 0, 0]; test_vectors
COMP2 = [ 0, 1, 0, 1];
DONE = [ 0, 1, 1, 0]; end lock;
IDLE0p = [ 0, 1, 1, 1];
ERROR1 = [ 1, 0, 0, 0];
IDLE1p = [ 1, 0, 0, 1];
ERROR2 = [ 1, 0, 1, 0];
ERROR3 = [ 1, 0, 1, 1];

Chapter Review Finite State Machine Design

Basic Timing Behavior an FSM
• when are inputs sampled, next state/outputs transition and stabilize
• Moore and Mealy (Async and Sync) machine organizations
outputs = F(state) vs. outputs = F(state, inputs)

First Two Steps of the Six Step Procedure for FSM Design
• understanding the problem
• abstract representation of the FSM

Abstract Representations of an FSM
• ASM Charts, Hardware Description Languages

Word Problems
• understand I/O behavior; draw diagrams
• enumerate states for the "goal"; expand with error conditions
• reuse states whenever possible

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