SHPINE TECHNOLOGIES:
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Hazard Identification (HAZID) vs. Hazard and Operability (HAZOP): A Comparati...
VLSI PROJECTS TITLES 2014-2015
1. Contact us : 24/1, Vellalar street, Kodambakkam, Chennai-600024.
Phone: 044-43548566, 8110081181.
Email id:shpinetechnologies@gmail.com,Web site: www.shpine.com
VLSI PROJECT TITLES 2014-2015
S.NO CODE TITLES
1 STV01 Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal
Matrix Code
2 STV02 Implementation of Delay Test for Diagnosis of Power Switches
3 STV03 Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating
4 STV04 Measure of Variation-Aware Variable Latency Design for all applications
5 STV05 In-depth performance measure of On Deadlock Problem of On-Chip Buses
Supporting Out-of-Order Transactions
6 STV06 Design of Low cost and AI based approach of On-Chip Oscilloscope to
Measure Jitter, Glitch and Skew of high speed signals
7 STV07 Design of Gated-Latch Utilization Technique for Clock-Tree Power
Optimization system
8 STV08 Design of Neural Networks With Hyperbolic Tangent Activation Function
9 STV09 Analysis and calculation of Ultra-High Throughput Low-Power Packet
Classification
10 STV10 High performance Low-Power Pulse-Triggered Flip-Flop Design Based on a
Signal Feed-Through Scheme
11 STV11 Reliable and time based Light-Weight On-Chip Structure for Measuring
Timing Uncertainty Induced by Noise in Integrated Circuits
12 STV12 Design, Test and evaluation of Framed Trace-Buffer system for FPGA
Testing
13 STV13 Analysis and calculation of Ultra-High Throughput Low-Power Packet
Classification
2. Contact us : 24/1, Vellalar street, Kodambakkam, Chennai-600024.
Phone: 044-43548566, 8110081181.
Email id:shpinetechnologies@gmail.com,Web site: www.shpine.com
S.NO CODE TITLES
14 STV14 Design of Cell-Based Process Resilient Multiphase Clock Generation
15 STV15 Reconfigurable High-Resolution All-Digital Duty-Cycle Corrector with auto
correct module
16 STV16 Software/Hardware Parallel Long-Period Random Number Generation
Framework Based on the WELL Method
17 STV17 Low-Complexity Reconfigurable Fast Filter Bank for Multi-Standard
Wireless Receivers
18 STV18 Use of SSTA Tools for Evaluating BTI Impact on Combinational Circuits
19 STV19 FPGA based Process-Resilient Low-Jitter All-Digital PLL via Smooth Code-
Jumping
20 STV20 LASIC: Loop-Aware Sleepy Instruction Caches Based on STT-RAM
Technology