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Cell Today and Tomorrow - IBM Systems and Technology Group
1.
Systems and Technology
Group © 2005 IBM Corporation Cell today and tomorrow H. Peter Hofstee, Ph. D. Cell Chief Scientist and Chief Architect, Cell Synergistic Processor IBM Systems and Technology Group SCEI/Sony Toshiba IBM (STI) Design Center Austin, Texas
2.
Systems and Technology
Group © 2005 IBM Corporation 2 Acknowledgements ƒ Cell Broadband Engine (“Cell”) is the result of a deep partnership between SCEI/Sony, Toshiba, and IBM ƒ Cell represents the work of more than 400 people starting in 2001and a design investment of about $400M
3.
Systems and Technology
Group © 2005 IBM Corporation 3 Agenda ƒ Basics – Performance: Power wall , Memory/Latency wall – Multicore and specialization ƒ Cell – Asynchronous load/store (DMA) – Microarchitecture decisions ƒ Cell Performance – Things that work really well – Things that will likely work well – Question marks ƒ Cell Systems ƒ Future of Cell and things for Academia to look at
4.
Systems and Technology
Group © 2005 IBM Corporation 4 BASICS
5.
Systems and Technology
Group © 2005 IBM Corporation 5 Computing Paradigm Shift Today: – Single thread performance hitting limits • Architecture and process technology saturated • Small percentage gains expected to remain But: – Signs of paradigm shift to application specific system customization • Large multiple gains for specific applications • Cell –~50x on TRE, ~100x on FFT • Datapower –XML acceleration • Many examples in embedded markets Future: – Greater performance demands • Immersive Interaction –3D, real-time, gaming inspired applications –Rich media, data-intensive content • Sensory Computing –New network tier –Autonomous agents performing intelligent analysis on streaming data >A&D: battlefield coordination Single Thread Performance SPECint Single thread performance growth rate slows dramatically Historical Trend 45% CGR
6.
Systems and Technology
Group © 2005 IBM Corporation 6 Solutions ƒ Memory wall: – More slower threads – Asynchronous loads ƒ Efficiency wall: – More slower threads – Specialized function ƒ Power wall: – Reduce transistor power • operating voltage • limit oxide thickness scaling • limit channel length – Reduce switching per function INCREASE CONCURRENCY: Multi-Core INCREASE SPECIALIZATION: Non-Homogeneous
7.
Systems and Technology
Group © 2005 IBM Corporation 7 CELL
8.
Systems and Technology
Group © 2005 IBM Corporation 8 Motivation: Cell Goals ƒ Outstanding performance, especially on game/multimedia applications. – Challenges: Power Wall, Frequency Wall, Memory Wall ƒ Real time responsiveness to the user and the network. – Challenges: Real-time in an SMP environment, Security ƒ Applicable to a wide range of platforms. – Challenge: Maintain programmability while increasing performance ƒ Support an introduction in 2005/6. – Challenge: Structure innovation such that 5yr. schedule can be met
9.
Systems and Technology
Group © 2005 IBM Corporation 9 Cell Concept ƒ Compatibility with 64b Power Architecture™ – Builds on and leverages IBM investment and community ƒ Increased efficiency and performance – Non Homogenous Coherent Chip Multiprocessor • Allows an attack on the “Frequency Wall” – Streaming DMA architecture attacks “Memory Wall” – High design frequency, low operating voltage attacks “Power Wall” – Highly optimized implementation ƒ Interface between user and networked world – Flexibility and security – Multi-OS support, including RTOS/non-RTOS – Architectural extensions for real-time management
10.
Systems and Technology
Group © 2005 IBM Corporation 10 Cell Architecture is … COHERENT BUS Power ISA MMU/BIU Power ISA MMU/BIU … IO transl. Memory Incl. coherence/memory compatible with 32/64b Power Arch. Applications and OS’s 64b Power Architecture™
11.
Systems and Technology
Group © 2005 IBM Corporation 11 Cell Architecture is … 64b Power Architecture™ COHERENT BUS (+RAG) Power ISA +RMT MMU/BIU +RMT Power ISA +RMT MMU/BIU +RMT IO transl. Memory Plus Memory Flow Control (MFC) MMU/DMA +RMT Local Store Memory MMU/DMA +RMT Local Store Memory LS Alias LS Alias … … …
12.
Systems and Technology
Group © 2005 IBM Corporation 12 Cell Architecture is … 64b Power Architecture™+ MFC COHERENT BUS (+RAG) Power ISA +RMT MMU/BIU +RMT Power ISA +RMT MMU/BIU +RMT IO transl. Memory Plus Synergistic Processors MMU/DMA +RMT Local Store Memory MMU/DMA +RMT Local Store Memory LS Alias LS Alias … … … Syn. Proc. ISA Syn. Proc. ISA
13.
Systems and Technology
Group © 2005 IBM Corporation 13 Asynchronous Load/Store (DMA) ƒ THE major architectural decision in Cell – Motivated by memory wall – Enabled by a large market ƒ Fundamental change to programmers. – Transition from demand-fetch to software controlled prefetch – Bill Dally’s “plumbing project analogy” – “Bucket brigade” analogy
14.
Systems and Technology
Group © 2005 IBM Corporation 14 Permute Unit Load-Store Unit Floating-Point Unit Fixed-Point Unit Branch Unit Channel Unit Result Forwarding and Staging Register File Local Store (256kB) Single Port SRAM 128B Read 128B Write DMA Unit Instruction Issue Unit / Instruction Line Buffer 8 Byte/Cycle 16 Byte/Cycle 128 Byte/Cycle 64 Byte/Cycle On-Chip Coherent Bus SPE BLOCK DIAGRAM
15.
Systems and Technology
Group © 2005 IBM Corporation 15 Other (Micro)Architectural and Decisions ƒ Large shared register file ƒ Local store size tradeoffs ƒ Dual issue, In order ƒ Software branch prediction ƒ Channels Microarchitecture decisions, more so than architecture decisions show bias towards compute-intensive codes
16.
Systems and Technology
Group © 2005 IBM Corporation 16
17.
Systems and Technology
Group © 2005 IBM Corporation 17 First pass hardware measurement in the Lab - Nominal Voltage = 1V 0.9 1 1.1 1.2 Supply Voltage 3 3.5 4 4.5 Frequency [GHz] Fmax Hardware Performance Measurement (85°C) ƒ 250M transistors … 235mm2 ƒ Top frequency >4GHz – Lab conditions – Most efficient at ~1V ƒ > 200 GFlops (SP) @3.2GHz ƒ > 20 GFlops (DP) @3.2GHz ƒ Up to 25.6 GB/s memory B/W ƒ Up to 70+ GB/s I/O B/W – Practical ~ 50GB/s ƒ 100+ simultaneous bus transactions – 16+8 entry DMA queue per SPE CELL PROCESSOR STATISTICS
18.
Systems and Technology
Group © 2005 IBM Corporation 18 CELL PERFORMANCE (AND PROGRAMMING)
19.
Systems and Technology
Group © 2005 IBM Corporation 19 Things that work extremely well today ( up to 100x) ƒ Problem can be re-coded ƒ Predictable non-trivial memory access pattern – Can build scatter-gather lists ƒ Problem can benefit from SIMD ƒ Focus on 32b float, or <=32b integer ƒ Examples: – FFTw ( best result about 100GFlops ) – Terrain Rendering Engine – Volume rendering ƒ Typical code is double-buffered gather-compute-scatter
20.
Systems and Technology
Group © 2005 IBM Corporation 20 Things that work well today ( about 10-20x) ƒ Compute bound codes ƒ Small enough to be rewritten ƒ Main datatype is 32b float or <= 32b Int ƒ Benefits from SIMD ƒ Examples: – Crypto codes ( RSA, SHA, DES, etc. etc. etc.) – Media codes ( MPEG 2, MPEG 4, H.264, JPEG ) – … many many others …
21.
Systems and Technology
Group © 2005 IBM Corporation 21 Things likely to work well ƒ Library .. Device/API based applications – Graphics and physics and sound and … ƒ Scientific codes … library based – No rewrite – If granularity is ok
22.
Systems and Technology
Group © 2005 IBM Corporation 22 Question marks ƒ Can a compiler based approach, without restructuring code specifically for the SPEs result in a chip-level advantage? – About 3-4x more SPEs in same area or power – But, have to compiler manage local store ƒ Interesting benchmarks: SpecFP, MediaBench, EEMBC, etc. – New more explicitly parallel benchmarks? ƒ Would you ever use an SPE for a SpecInt-type workload?
23.
Systems and Technology
Group © 2005 IBM Corporation 23 Cell based systems
24.
Systems and Technology
Group © 2005 IBM Corporation 24 Cell Processor Isn't Just for Games. Innovative Chip is best high-performance embedded processor of 2005 We chose the Cell BE as the best high-performance embedded processor of 2005 because of its innovative design and future potential....Even if the Cell BE accumulates no more design wins, the PlayStation 3 could drive sales to nearly 100 million units over the likely five-year lifespan of the console. That would make the Cell BE one of the most successful microprocessors in history. “…Cell could power hundreds of new apps, create a new video- processing industry and fuel a multibillion-dollar build out of tech hardware over ten years.” -- Forbes “It was originally conceived as the microprocessor to power Sony's [PS3], but it is expected to find a home in lots of other broadband- connected consumer items and in servers too.” -- IEEE Spectrum
25.
Systems and Technology
Group © 2005 IBM Corporation 25 Cell BE based Systems: SCEI, Mercury, … and IBM!
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Systems and Technology
Group © 2005 IBM Corporation 26 ƒ Toshiba Announces Cell Chip Set and Cell Reference Set 20 September, 2005 ƒ Tokyo--Toshiba Corporation today took major steps toward creating a comprehensive development environment for applications based on the Cell microprocessor with the announcement of a Cell Chip Set consisting of the new microprocessor and key peripheral chips, and a Cell Reference Set development platform. The chip set and the reference set will support development of digital consumer products and communication equipment that draw on the powerful broadband capabilities of the Cell microprocessor. ƒ "Software developers and other customers will be eager to make full use of Cell's unsurpassed multitasking and real-time processing functions," said Tomotaka Saito, General Manager of Broadband System LSI Division, Toshiba Corporation Semiconductor Company. "The Cell Chip Set and Reference Set will support them in developing products and applications that reach new levels of performance and excitement." ƒ The Cell Chip Set is composed of the Cell processor, a Super Companion Chip—the interface between Cell and external audio/visual input/output equipment—and a power supply system chip optimized to drive the Cell microprocessor. ƒ The Cell Reference Set development platform consists of a Cell microprocessor, peripheral chips mounted on a printed circuit board with a general-use interface, peripheral equipment, such as DVD and HDD drives, and cooling equipment required for stable operation, all housed in case. The available software includes operating systems and middleware and software development tools. This combination of hardware and software reduces development costs, cuts turnaround time and simplifies testing. ƒ Toshiba expects to start marketing the chips set and reference set in April 2006 or later, once it has assured supply of the component chips and all related documentation. ƒ Toshiba Corporation will showcase the Cell Chip Set and Cell Reference Set, and demonstrate digital media applications on the Cell Reference Set at the Toshiba booth of CEATEC JAPAN 2005, from October 4 to October 8 at Makuhari Messe. ƒ Outlines of Cell Chip Set and Cell Reference Set: ƒ Cell Chip Set: ƒ Cell microprocessor: Next generation microprocessor jointly developed by IBM, Sony Group and Toshiba. Adopts a multi-core architecture and offers super high-speed data transfer capability. The processor is expected to find application in equipment handling data-rich media applications. ƒ Super Companion Chip: Cell's peripheral LSI, which houses audio and image interfaces supporting Cell's super high-speed data transfer capability. The chip also supports a group of interfaces for various systems (video, audio input/output, digital AV interface, IEEE1394, digital tuner interface) and a group of interfaces that make it easier to connect standard input/output devices (standard bus interface, high speed network interface and storage device interface.) ƒ Highly efficient power supply system: The supply system is optimized to drive the Cell processor. Includes controller LSI, TB6814FLG, which makes it possible to offer high-speed response and high-accuracy required by Cell. Includes multi-chip module, TB7003FL, which embeds power device in a small 8mm x 8mm package. Realizes small, high-power and high-efficient power supply system which has 4 phases of 1MHz high-speed switches. ƒ Cell Reference Set: ƒ Development platform for Cell-based, next generation digital consumer products, ƒ High-speed multi-bit wiring technology and wide variety of interfaces that supports broadband system architecture ƒ Linux and ITRON are both provided on the hypervisor OS that manages hardware resources. This approach facilitates the reuse of application property. ƒ A comprehensive development environment including the Eclipse framework based editor, compiler, debugger, and performance monitor. ƒ An audio-visual application model includes simultaneous multiple digital and analog broadcast television reception, recording and playback. SOURCE: TOSHIBA
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Group © 2005 IBM Corporation 27 Future of Cell and Things for Academia to look at
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Group © 2005 IBM Corporation 28 User Interaction Drives Innovation in Computing Time Punch Cards Green Screen/ Teletype Spreadsheet WWW Gaming Main Frame Multitasking Main Frame Batch Client/Server Internet Mini-Computer WYSIWYG Stand Alone PC Windows Word Processing Level of Interaction Immersive Interaction Online Gaming Source: J.A. Kahle
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Group © 2005 IBM Corporation 29 Characteristics of the Latest Transition in User Interaction ƒ Windows ƒ Click and wait… ƒ Client-centric ƒ User data accessible from client only ƒ Device-centric ƒ Connected ƒ Wired, sporadic ƒ E-mail/newsgroups ƒ Immersive, 3D interactivity ƒ Real-time ƒ Distributed ƒ User data accessible everywhere ƒ Device-agnostic ƒ Collaborative ƒ Wireless, always-on ƒ Text messaging/blogs
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Group © 2005 IBM Corporation 30 Some things for Academia to look at ƒ Specialization in computer architectures – Beyond OS/Application, what specialization makes sense in a general-(enough) purpose chip/system multiprocessor? ƒ Programming paradigms and compilation techniques to deal with memory wall ƒ New types of applications (often real-time) made possible by a dramatic jump in performance – E.g. gesture and emotion recognition