dutycycle correction

1. DUTY CYCLE CORRECTION USING ASIC
FOR HIGH SPEED COMMUNICATION
Presented by
Gunde Mounika

2. • Abstract
• Introduction
• Methodology
• Duty Cycle
• Applications
• Conclusion
Contents

3. It is applied as a percentage of the measured
average power of a modulated signal to obtain the
signal power. This circuit uses two stages of
correction, with the first stage performing course
correction and the second stage performing fine
corrections. This allows the power to be determined
during the pulse given the measurement of the
average power of a modulated signal with a known
duty cycle. In this analysis, the duty cycle correction
circuits and their significance in Application Specific
Integrated Circuit (ASIC) design.
ABSTRA
CT

4. The digital correction circuit is more reliable, simpler to
use, and capable of higher-frequency resolution
improvement.
This is crucial for high-speed circuits and logic families
because it determines how much time is allotted for
the pre-charge and evaluation phases; If this time is
off from the desired value, performance will suffer.
The clock signal can be further weakened by
environmental and process variables, making it
challenging to produce and disseminate high-
frequency clocks with a fixed duty cycle Before
providing the clock signals to the sensitive parts of the
design, the duty cycle value was measured.
INTRODUCTION

5.  The measurement is based on a specific logic, and once the
measurement is performed based on the duty cycle value, the
clock switches to the correction circuit, this correction can be
controlled using a controller.
 The required amount of correction was controlled by selecting
bits from 0 to 15. The selection of each bit corrects the input
clock signal by a fixed amount.
 the clock switches to the correction circuit . The DCC circuit is
designed for high-speed interfaces such as the Universal Serial
Bus (USB) and Peripheral Component Interconnect Express
(PCIE)
 The DCC has improved stability, correction range, and operating
frequency compared to mixed-signal and all-digital DCCs.
Contd.,

6.  A small and compact automated home system controller that
combines comfort, security, and an automated load transfer
switch was proposed and designed under an Application
Specific Integrated Circuit (ASIC) design flow.
 A dual feedback loop with a differential input clock was added
to reduce the impact of charge pump imbalance on circuit
performance.
 A chopping technique was also introduced to improve the loop
gain while suppressing the DC offset in the feedback loop.
Furthermore, a novel Duty-Cycle Adjuster (DCA) with
configurable load capacitance was presented to maintain the
duty-cycle correction range over a wide frequency range. The
proposed DCC was implemented in a 65-nm CMOS process
with a 1-V supply voltage. proposed an analog duty-cycle

7. Methodology
90 nm Technology
Leading semiconductor companies, such as Toshiba, Sony,
Samsung, IBM, Intel, Fujitsu, TSMC, Elpida, AMD, Infineon,
Texas Instruments, and Micron Technology, have
commercialized the 90 nm process for MOSFET (CMOS)
production between 2003 and 2005, with a historic and
associated 70% upward trend every two to three years. The
significant costs associated with this change were reflected in
performance concerns.
Cadence Virtuoso System Design Platform
It is a system based solution that provides functionality to
drive the simulation of ICs and packages from a single
schematic.

8. Duty cycle is the ratio of time a load or circuit is ON
compared to the time the load or circuit is OFF. Duty cycle,
sometimes called "duty factor," is expressed as a
percentage of ON time. A 60% duty cycle is a signal that is
ON 60% of the time and OFF the other 40%.
Duty Cycle= ON time / (ON time + OFF
time)
The idea of duty cycle correction circuits, its significance
Period = 1/Frequency period = T + T on off
Duty cycle = T (T +T ) *100 (in percentage)
Duty Cycle

10. Circuit Diagram of Duty Cycle Adjuster

11. Output for Time Period with
On and Off Position
Duty Cycle Adjustment by
Delay Line

12. Applications
 In real-time systems, where precise timing is
important, duty-cycle correction circuits have a wide
range of applications.
 High-speed communication systems are constructed in
the duty-cycle correction circuit that is used in high-
speed communication systems to ensure accurate
timing for data transmission. Digital signal processing
is used in digital signal processing applications to
improve the accuracy and efficiency of operations
such as filtering, modulation, and demodulation.
 The accurate timing of microprocessors and
microcontrollers is essential for executing instructions
and controlling peripherals.
 Test and measurement equipment is used in test and
measurement equipment to generate and measure
signals with high precision by ensuring accurate
timing.

13. A duty-cycle correction circuit was proposed in this,
which was used to correct the inconsistencies caused by
environmental and process fluctuations in the duty cycle.
The results indicate that less than 1% can be used to adjust
the duty cycle of the input clock from 15 to 63%. The loop
could accurately output a 50% duty cycle for a wide range
of input duty cycles. The adjuster circuit is used in the duty-
cycle correction circuit to alter the duty cycle of the input
clock and is responsible for controlling the delay between
the two complementary signals. The circuit is more resilient
and capable of producing a very fine resolution when
compared to analog techniques currently used for duty-
cycle correction.
Conclusion