libmc is a memcached client library for Python without any other dependencies in runtime. It's mainly written in C++ and Cython. https://github.com/douban/libmc
Finding a useful outlet for my many Adventures in goEleanor McHugh
A talk about my Leanpub-published living eBook: A Go Developer's Notebook. Buy my book? Write your own Book using Leanpub? Learn you some Golang for fun?
Finding a useful outlet for my many Adventures in goEleanor McHugh
A talk about my Leanpub-published living eBook: A Go Developer's Notebook. Buy my book? Write your own Book using Leanpub? Learn you some Golang for fun?
T Series Core Router Architecture Review (Whitepaper)Juniper Networks
Juniper Networks® T Series Core Routers have been in production since 2002, with the introduction of the Juniper Networks T640 Core Router. Since that time, T Series routers have evolved to maintain an unequivocal industry lead in capacity (slot, chassis, and system) and operational efficiencies in power and usability. Maintaining this standard has in part been possible due to design decisions made with the very first T Series system. The T Series demonstrates how Juniper has evolved its router architecture to achieve substantial technology breakthroughs in packet forwarding performance, bandwidth density, IP service delivery, and system reliability. At the same time, the integrity of the original design has made these breakthroughs possible. Not only do T Series platforms deliver industry-leading scalability, they do so while maintaining feature and software continuity across all routing platforms. Whether deploying a single-chassis or multichassis system, service providers can be assured that the T Series satisfies all networking requirements.
CUDA by Example : CUDA C on Multiple GPUs : NotesSubhajit Sahu
Highlighted notes of:
Chapter 11: CUDA C on Multiple GPUs
Book:
CUDA by Example
An Introduction to General Purpose GPU Computing
Authors:
Jason Sanders
Edward Kandrot
“This book is required reading for anyone working with accelerator-based computing systems.”
–From the Foreword by Jack Dongarra, University of Tennessee and Oak Ridge National Laboratory
CUDA is a computing architecture designed to facilitate the development of parallel programs. In conjunction with a comprehensive software platform, the CUDA Architecture enables programmers to draw on the immense power of graphics processing units (GPUs) when building high-performance applications. GPUs, of course, have long been available for demanding graphics and game applications. CUDA now brings this valuable resource to programmers working on applications in other domains, including science, engineering, and finance. No knowledge of graphics programming is required–just the ability to program in a modestly extended version of C.
CUDA by Example, written by two senior members of the CUDA software platform team, shows programmers how to employ this new technology. The authors introduce each area of CUDA development through working examples. After a concise introduction to the CUDA platform and architecture, as well as a quick-start guide to CUDA C, the book details the techniques and trade-offs associated with each key CUDA feature. You’ll discover when to use each CUDA C extension and how to write CUDA software that delivers truly outstanding performance.
Table of Contents
Why CUDA? Why Now?
Getting Started
Introduction to CUDA C
Parallel Programming in CUDA C
Thread Cooperation
Constant Memory and Events
Texture Memory
Graphics Interoperability
Atomics
Streams
CUDA C on Multiple GPUs
The Final Countdown
All the CUDA software tools you’ll need are freely available for download from NVIDIA.
Jason Sanders is a senior software engineer in NVIDIA’s CUDA Platform Group, helped develop early releases of CUDA system software and contributed to the OpenCL 1.0 Specification, an industry standard for heterogeneous computing. He has held positions at ATI Technologies, Apple, and Novell.
Edward Kandrot is a senior software engineer on NVIDIA’s CUDA Algorithms team, has more than twenty years of industry experience optimizing code performance for firms including Adobe, Microsoft, Google, and Autodesk.
Learn about IBM PowerVM Best Practices.This IBM Redbooks publication provides best practices for planning, installing, maintaining, and monitoring the IBM PowerVM Enterprise Edition virtualization features on IBM POWER7 processor technology-based servers.
For more information on Power Systems, visit http://ibm.co/Lx6hfc.
Visit http://bit.ly/KWh5Dx to 'Follow' the official Twitter handle of IBM India Smarter Computing.
The IBM Flex System platform provides a unique set of features that enable the integration of leading-edge technologies and transformation approaches into the data centers. These IBM Flex System features ensure that the availability, performance, scalability, security, and manageability goals of the data center networking design are met as efficiently as possible. For more information on Pure Systems, visit http://ibm.co/18vDnp6.
Visit http://on.fb.me/LT4gdu to 'Like' the official Facebook page of IBM India Smarter Computing.
Learn about the configuration of IBM PowerVC. IBM PowerVC is built on OpenStack that controls large pools of server, storage, and networking resources throughout a data center. IBM Power Virtualization Center provides security services that support a secure environment. Installation requires just 20 minutes to get a virtual machine up and running. For more information on Power Systems, visit http://ibm.co/Lx6hfc.
Visit http://on.fb.me/LT4gdu to 'Like' the official Facebook page of IBM India Smarter Computing.
T Series Core Router Architecture Review (Whitepaper)Juniper Networks
Juniper Networks® T Series Core Routers have been in production since 2002, with the introduction of the Juniper Networks T640 Core Router. Since that time, T Series routers have evolved to maintain an unequivocal industry lead in capacity (slot, chassis, and system) and operational efficiencies in power and usability. Maintaining this standard has in part been possible due to design decisions made with the very first T Series system. The T Series demonstrates how Juniper has evolved its router architecture to achieve substantial technology breakthroughs in packet forwarding performance, bandwidth density, IP service delivery, and system reliability. At the same time, the integrity of the original design has made these breakthroughs possible. Not only do T Series platforms deliver industry-leading scalability, they do so while maintaining feature and software continuity across all routing platforms. Whether deploying a single-chassis or multichassis system, service providers can be assured that the T Series satisfies all networking requirements.
CUDA by Example : CUDA C on Multiple GPUs : NotesSubhajit Sahu
Highlighted notes of:
Chapter 11: CUDA C on Multiple GPUs
Book:
CUDA by Example
An Introduction to General Purpose GPU Computing
Authors:
Jason Sanders
Edward Kandrot
“This book is required reading for anyone working with accelerator-based computing systems.”
–From the Foreword by Jack Dongarra, University of Tennessee and Oak Ridge National Laboratory
CUDA is a computing architecture designed to facilitate the development of parallel programs. In conjunction with a comprehensive software platform, the CUDA Architecture enables programmers to draw on the immense power of graphics processing units (GPUs) when building high-performance applications. GPUs, of course, have long been available for demanding graphics and game applications. CUDA now brings this valuable resource to programmers working on applications in other domains, including science, engineering, and finance. No knowledge of graphics programming is required–just the ability to program in a modestly extended version of C.
CUDA by Example, written by two senior members of the CUDA software platform team, shows programmers how to employ this new technology. The authors introduce each area of CUDA development through working examples. After a concise introduction to the CUDA platform and architecture, as well as a quick-start guide to CUDA C, the book details the techniques and trade-offs associated with each key CUDA feature. You’ll discover when to use each CUDA C extension and how to write CUDA software that delivers truly outstanding performance.
Table of Contents
Why CUDA? Why Now?
Getting Started
Introduction to CUDA C
Parallel Programming in CUDA C
Thread Cooperation
Constant Memory and Events
Texture Memory
Graphics Interoperability
Atomics
Streams
CUDA C on Multiple GPUs
The Final Countdown
All the CUDA software tools you’ll need are freely available for download from NVIDIA.
Jason Sanders is a senior software engineer in NVIDIA’s CUDA Platform Group, helped develop early releases of CUDA system software and contributed to the OpenCL 1.0 Specification, an industry standard for heterogeneous computing. He has held positions at ATI Technologies, Apple, and Novell.
Edward Kandrot is a senior software engineer on NVIDIA’s CUDA Algorithms team, has more than twenty years of industry experience optimizing code performance for firms including Adobe, Microsoft, Google, and Autodesk.
Learn about IBM PowerVM Best Practices.This IBM Redbooks publication provides best practices for planning, installing, maintaining, and monitoring the IBM PowerVM Enterprise Edition virtualization features on IBM POWER7 processor technology-based servers.
For more information on Power Systems, visit http://ibm.co/Lx6hfc.
Visit http://bit.ly/KWh5Dx to 'Follow' the official Twitter handle of IBM India Smarter Computing.
The IBM Flex System platform provides a unique set of features that enable the integration of leading-edge technologies and transformation approaches into the data centers. These IBM Flex System features ensure that the availability, performance, scalability, security, and manageability goals of the data center networking design are met as efficiently as possible. For more information on Pure Systems, visit http://ibm.co/18vDnp6.
Visit http://on.fb.me/LT4gdu to 'Like' the official Facebook page of IBM India Smarter Computing.
Learn about the configuration of IBM PowerVC. IBM PowerVC is built on OpenStack that controls large pools of server, storage, and networking resources throughout a data center. IBM Power Virtualization Center provides security services that support a secure environment. Installation requires just 20 minutes to get a virtual machine up and running. For more information on Power Systems, visit http://ibm.co/Lx6hfc.
Visit http://on.fb.me/LT4gdu to 'Like' the official Facebook page of IBM India Smarter Computing.
AIX 5L Version 5.3 introduces many new features, including NFS Version 4 and Advanced Accounting, and exploits the advanced capabilities of POWER5 equipped severs, such as Virtual SCSI, Virtual Ethernet SMT, Micro-Partitioning, and others. This IBM Redbook focuses on the differences introduced in AIX 5L Version 5.3 when compared to AIX 5L Version 5.2. For more information on Power Systems, visit http://ibm.co/Lx6hfc.
Visit the official Scribd Channel of IBM India Smarter Computing at http://bit.ly/VwO86R to get access to more documents.
Using recycled concrete aggregates (RCA) for pavements is crucial to achieving sustainability. Implementing RCA for new pavement can minimize carbon footprint, conserve natural resources, reduce harmful emissions, and lower life cycle costs. Compared to natural aggregate (NA), RCA pavement has fewer comprehensive studies and sustainability assessments.
CHINA’S GEO-ECONOMIC OUTREACH IN CENTRAL ASIAN COUNTRIES AND FUTURE PROSPECTjpsjournal1
The rivalry between prominent international actors for dominance over Central Asia's hydrocarbon
reserves and the ancient silk trade route, along with China's diplomatic endeavours in the area, has been
referred to as the "New Great Game." This research centres on the power struggle, considering
geopolitical, geostrategic, and geoeconomic variables. Topics including trade, political hegemony, oil
politics, and conventional and nontraditional security are all explored and explained by the researcher.
Using Mackinder's Heartland, Spykman Rimland, and Hegemonic Stability theories, examines China's role
in Central Asia. This study adheres to the empirical epistemological method and has taken care of
objectivity. This study analyze primary and secondary research documents critically to elaborate role of
china’s geo economic outreach in central Asian countries and its future prospect. China is thriving in trade,
pipeline politics, and winning states, according to this study, thanks to important instruments like the
Shanghai Cooperation Organisation and the Belt and Road Economic Initiative. According to this study,
China is seeing significant success in commerce, pipeline politics, and gaining influence on other
governments. This success may be attributed to the effective utilisation of key tools such as the Shanghai
Cooperation Organisation and the Belt and Road Economic Initiative.
We have compiled the most important slides from each speaker's presentation. This year’s compilation, available for free, captures the key insights and contributions shared during the DfMAy 2024 conference.
Online aptitude test management system project report.pdfKamal Acharya
The purpose of on-line aptitude test system is to take online test in an efficient manner and no time wasting for checking the paper. The main objective of on-line aptitude test system is to efficiently evaluate the candidate thoroughly through a fully automated system that not only saves lot of time but also gives fast results. For students they give papers according to their convenience and time and there is no need of using extra thing like paper, pen etc. This can be used in educational institutions as well as in corporate world. Can be used anywhere any time as it is a web based application (user Location doesn’t matter). No restriction that examiner has to be present when the candidate takes the test.
Every time when lecturers/professors need to conduct examinations they have to sit down think about the questions and then create a whole new set of questions for each and every exam. In some cases the professor may want to give an open book online exam that is the student can take the exam any time anywhere, but the student might have to answer the questions in a limited time period. The professor may want to change the sequence of questions for every student. The problem that a student has is whenever a date for the exam is declared the student has to take it and there is no way he can take it at some other time. This project will create an interface for the examiner to create and store questions in a repository. It will also create an interface for the student to take examinations at his convenience and the questions and/or exams may be timed. Thereby creating an application which can be used by examiners and examinee’s simultaneously.
Examination System is very useful for Teachers/Professors. As in the teaching profession, you are responsible for writing question papers. In the conventional method, you write the question paper on paper, keep question papers separate from answers and all this information you have to keep in a locker to avoid unauthorized access. Using the Examination System you can create a question paper and everything will be written to a single exam file in encrypted format. You can set the General and Administrator password to avoid unauthorized access to your question paper. Every time you start the examination, the program shuffles all the questions and selects them randomly from the database, which reduces the chances of memorizing the questions.
Low power architecture of logic gates using adiabatic techniquesnooriasukmaningtyas
The growing significance of portable systems to limit power consumption in ultra-large-scale-integration chips of very high density, has recently led to rapid and inventive progresses in low-power design. The most effective technique is adiabatic logic circuit design in energy-efficient hardware. This paper presents two adiabatic approaches for the design of low power circuits, modified positive feedback adiabatic logic (modified PFAL) and the other is direct current diode based positive feedback adiabatic logic (DC-DB PFAL). Logic gates are the preliminary components in any digital circuit design. By improving the performance of basic gates, one can improvise the whole system performance. In this paper proposed circuit design of the low power architecture of OR/NOR, AND/NAND, and XOR/XNOR gates are presented using the said approaches and their results are analyzed for powerdissipation, delay, power-delay-product and rise time and compared with the other adiabatic techniques along with the conventional complementary metal oxide semiconductor (CMOS) designs reported in the literature. It has been found that the designs with DC-DB PFAL technique outperform with the percentage improvement of 65% for NOR gate and 7% for NAND gate and 34% for XNOR gate over the modified PFAL techniques at 10 MHz respectively.
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Tips
▶ Prefer “switch statements” to if-else condition.
▶ “Exception” and “heap allocation” are slow in C++.
▶ Avoid memory copy.
▶ SmallVector optimization.
▶ Undocumented “UIO MAXIOV” limit in iovec.
▶ clean buffer on error
▶ Server may refuse if too much data is “send”(sent) without
“recv”-ing
▶ Lazy connecting.
▶ GIL issue.
▶ gevent issue.
▶ man 2 recv: For TCP sockets, the return value 0 means the
peer has closed its half side of the connection.
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Tips
▶ Prefer “switch statements” to if-else condition.
▶ “Exception” and “heap allocation” are slow in C++.
▶ Avoid memory copy.
▶ SmallVector optimization.
▶ Undocumented “UIO MAXIOV” limit in iovec.
▶ clean buffer on error
▶ Server may refuse if too much data is “send”(sent) without
“recv”-ing
▶ Lazy connecting.
▶ GIL issue.
▶ gevent issue.
▶ man 2 recv: For TCP sockets, the return value 0 means the
peer has closed its half side of the connection.
▶ write the right benchmark. bench order? dependency?
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Tips
▶ Prefer “switch statements” to if-else condition.
▶ “Exception” and “heap allocation” are slow in C++.
▶ Avoid memory copy.
▶ SmallVector optimization.
▶ Undocumented “UIO MAXIOV” limit in iovec.
▶ clean buffer on error
▶ Server may refuse if too much data is “send”(sent) without
“recv”-ing
▶ Lazy connecting.
▶ GIL issue.
▶ gevent issue.
▶ man 2 recv: For TCP sockets, the return value 0 means the
peer has closed its half side of the connection.
▶ write the right benchmark. bench order? dependency?
▶ md5 is slow. bugfree fnv1 is hard to implement.
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Tips
▶ Prefer “switch statements” to if-else condition.
▶ “Exception” and “heap allocation” are slow in C++.
▶ Avoid memory copy.
▶ SmallVector optimization.
▶ Undocumented “UIO MAXIOV” limit in iovec.
▶ clean buffer on error
▶ Server may refuse if too much data is “send”(sent) without
“recv”-ing
▶ Lazy connecting.
▶ GIL issue.
▶ gevent issue.
▶ man 2 recv: For TCP sockets, the return value 0 means the
peer has closed its half side of the connection.
▶ write the right benchmark. bench order? dependency?
▶ md5 is slow. bugfree fnv1 is hard to implement.
▶ vim: Rip-Rip/clang complete + cpplint.py