This document provides information about the features and architecture of the 8051 microcontroller. It describes the 8-bit CPU, 64K program memory, 64K data memory, 4K on-chip program memory, 128 bytes of on-chip data RAM, 32 I/O lines, two timers, UART serial communication, interrupt structure, and on-chip oscillator. It also covers the pin descriptions, registers, memory mapping, stack, I/O port programming, timers, and interrupts of the 8051. Finally, it discusses the instruction set groups for arithmetic, logical, data transfer, boolean, and program branching operations.
2. FEATURESFEATURES
8-bit CPU optimized for control applications
Extensive Boolean processing (Single-bit logic) capabilities
64K Program Memory address space
64K Data Memory address space
4K bytes of on-chip Program Memory
128 bytes of on-chip Data RAM
32 bidirectional and individually addressable 1/0 lines
Two 16-bit timer/counters
Full duplex UART
6-source/5-vector interrupt structure with two priority levels
On-chip clock oscillator
3. Contents:Contents:
IntroductionIntroduction
Block Diagram andBlock Diagram and Pin Description of the 8051Pin Description of the 8051
RegistersRegisters
Memory mapping in 8051Memory mapping in 8051
Stack in the 8051Stack in the 8051
I/O Port ProgrammingI/O Port Programming
TimerTimer
InterruptInterrupt
4. Why do we need to learnWhy do we need to learn
Microprocessors/controllers?Microprocessors/controllers?
The microprocessor is the core of
computer systems.
Nowadays many communication, digital
entertainment, portable devices, are
controlled by them.
A designer should know what types of
components he needs, ways to reduce
production costs and product reliable..
5. Different aspects of a
microprocessor/controller
Hardware :Interface to the real world
Software :order how to deal with inputs
6. The necessary tools for aThe necessary tools for a
microprocessor/controllermicroprocessor/controller
CPU: Central Processing Unit
I/O: Input /Output
Bus: Address bus & Data bus
Memory: RAM & ROM
Timer
Interrupt
Serial Port
Parallel Port
9. Microprocessor
CPU is stand-alone, RAM,
ROM, I/O, timer are separate
designer can decide on the
amount of ROM, RAM and
I/O ports.
expansive
versatility
general-purpose
Microcontroller
• CPU, RAM, ROM, I/O and
timer are all on a single chip
• fix amount of on-chip ROM,
RAM, I/O ports
• for applications in which cost,
power and space are critical
• single-purpose
Microprocessor vs. Microcontroller
10. Embedded system means the processor is embedded into that
application.
An embedded product uses a microprocessor or microcontroller to
do one task only.
In an embedded system, there is only one application software that
is typically burned into ROM.
Example : printer, keyboard, video game player
Embedded System
11. 1. meeting the computing needs of the task efficiently and cost
effectively
• speed, the amount of ROM and RAM, the number of I/O ports
and timers, size, packaging, power consumption
• easy to upgrade
• cost per unit
1. availability of software development tools
• assemblers, debuggers, C compilers, emulator, simulator,
technical support
1. wide availability and reliable sources of the microcontrollers.
Three criteria in Choosing a Microcontroller
15. Pins of 8051Pins of 8051 (( 1/41/4 ))
Vcc ( pin 40 ):
Vcc provides supply voltage to the chip.
The voltage source is +5V.
GND ( pin 20 ): ground
XTAL1 and XTAL2 ( pins 19,18 )
16. Figure (a). XTAL Connection to 8051Figure (a). XTAL Connection to 8051
C2
30pF
C1
30pF
XTAL2
XTAL1
GND
Using a quartz crystal oscillator
We can observe the frequency on the XTAL2 pin.
17. Pins of 8051Pins of 8051 (( 2/42/4 ))
RST ( pin 9 ): reset
It is an input pin and is active high ( normally low ) .
The high pulse must be high at least 2 machine
cycles.
It is a power-on reset.
Upon applying a high pulse to RST, the
microcontroller will reset and all values in registers
will be lost.
Reset values of some 8051 registers
19. Pins of 8051Pins of 8051 (( 3/43/4 ))
/EA ( pin 31 ): external access
There is no on-chip ROM in 8031 and 8032 .
The /EA pin is connected to GND to indicate the code is
stored externally.
/PSEN & ALE are used for external ROM.
For 8051, /EA pin is connected to Vcc.
“/” means active low.
/PSEN ( pin 29 ): program store enable
This is an output pin and is connected to the OE pin of the
ROM.
20. Pins of 8051Pins of 8051 (( 4/44/4 ))
ALE ( pin 30 ): address latch enable
It is an output pin and is active high.
8051 port 0 provides both address and data.
The ALE pin is used for de-multiplexing the address
and data by connecting to the G pin of the 74LS373
latch.
I/O port pins
The four ports P0, P1, P2, and P3.
Each port uses 8 pins.
All I/O pins are bi-directional..
21. Pins of I/O PortPins of I/O Port
The 8051 has four I/O ports
Port 0 ( pins 32-39 ): P0 ( P0.0 ~ P0.7 )
Port 1 ( pins 1-8 ) : P1 ( P1.0 ~ P1.7 )
Port 2 ( pins 21-28 ): P2 ( P2.0 ~ P2.7 )
Port 3 ( pins 10-17 ): P3 ( P3.0 ~ P3.7 )
Each port has 8 pins.
Named P0.X ( X=0,1,...,7 ) , P1.X, P2.X, P3.X
Ex : P0.0 is the bit 0 ( LSB ) of P0
Ex : P0.7 is the bit 7 ( MSB ) of P0
These 8 bits form a byte.
Each port can be used as input or output (bi-direction).
22. Hardware Structure of I/O PinHardware Structure of I/O Pin
Each pin of I/O ports
Internal CPU bus : communicate with CPU
A D latch store the value of this pin
D latch is controlled by “Write to latch”
Write to latch = 1 : write data into the D latch
2 Tri-state buffer :
TB1: controlled by “Read pin”
Read pin = 1 : really read the data present at the pin
TB2: controlled by “Read latch”
Read latch = 1 : read value from internal latch
A transistor M1 gate
Gate=0: open
Gate=1: close
24. A Pin of Port 1A Pin of Port 1
8051 IC
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU
bus
M1
P1.X
pinP1.X
TB1
TB2
P0.x
25. Writing “1” to Output Pin P1.XWriting “1” to Output Pin P1.X
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU
bus
M1
P1.X
pinP1.X
8051 IC
2. output pin is
Vcc1. write a 1 to the pin
1
0 output 1
TB1
TB2
26. Writing “0” to Output Pin P1.XWriting “0” to Output Pin P1.X
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU
bus
M1
P1.X
pinP1.X
8051 IC
2. output pin is
ground1. write a 0 to the pin
0
1 output 0
TB1
TB2
27. Reading “High” at Input PinReading “High” at Input Pin
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU bus
M1
P1.X pin
P1.X
8051 IC
2. MOV A,P1
external pin=High
1. write a 1 to the pin MOV
P1,#0FFH
1
0
3. Read pin=1 Read latch=0
Write to latch=1
1
TB1
TB2
28. Reading “Low” at Input PinReading “Low” at Input Pin
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU bus
M1
P1.X pin
P1.X
8051 IC
2. MOV A,P1
external pin=Low1. write a 1 to the pin
MOV P1,#0FFH
1
0
3. Read pin=1 Read latch=0
Write to latch=1
0
TB1
TB2
29. Other PinsOther Pins
P1, P2, and P3 have internal pull-up resisters.
P1, P2, and P3 are not open drain.
P0 has no internal pull-up resistors and does not
connects to Vcc inside the 8051.
P0 is open drain.
Compare the figures of P1.X and P0.X.
However, for a programmer, it is the same to program
P0, P1, P2 and P3.
All the ports upon RESET are configured as output.
30. A Pin of Port 0A Pin of Port 0
8051 IC
D Q
Clk Q
Read latch
Read pin
Write to latch
Internal CPU
bus
M1
P0.X
pinP1.X
TB1
TB2
P1.x
31. Port 0 with Pull-Up ResistorsPort 0 with Pull-Up Resistors
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
DS5000
8751
8951
Vcc
10 K
Port0
32. Port 3 Alternate FunctionsPort 3 Alternate Functions
1717RDRDP3.7P3.7
1616WRWRP3.6P3.6
1515T1T1P3.5P3.5
1414T0T0P3.4P3.4
1313INT1INT1P3.3P3.3
1212INT0INT0P3.2P3.2
1111TxDTxDP3.1P3.1
1010RxDRxDP3.0P3.0
PinPinFunctionFunctionP3 BitP3 Bit
33. RESET Value of Some 8051 Registers:RESET Value of Some 8051 Registers:
0000DPTR
0007SP
0000PSW
0000B
0000ACC
0000PC
Reset ValueRegister
RAM are all zero..
34. INTERNAL RAM STRUCTUREINTERNAL RAM STRUCTURE
Direct &
Indirect
Addressing
Inirect
Addressing
Only
Direct
Addressing
Only SFR
128 Byte
Internal RAM
36. 128 BYTE RAM128 BYTE RAM
128 BYTE
INTERNAL RAM
Register Banks
Reg Bank 0
Reg Bank 1
Reg Bank 2
Reg Bank 3
BIT Addressable
Area
General Purpose
Area
37. RAM memory space allocation in the 8051
7FH
30H
2FH
20H
1FH
17H
10H
0FH
07H
08H
18H
00H
Register Bank 0
)Stack) Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
38. REGISTER BANK STRUCTUREREGISTER BANK STRUCTURE
R0R0 R1R1 R2R2 R3R3 R4R4 R5R5 R6R6 R7R7Bank 0
R0R0 R1R1 R2R2 R3R3 R4R4 R5R5 R6R6 R7R7Bank 3
R0R0 R1R1 R2R2 R3R3 R4R4 R5R5 R6R6 R7R7Bank 2
R0R0 R1R1 R2R2 R3R3 R4R4 R5R5 R6R6 R7R7Bank 1
CYCY ACAC F0F0 RS1RS1 RS0RS0 OVOV -- PP
Program Status Word -Program Status Word - PSWPSW
40. Memory mapping in 8051Memory mapping in 8051
ROM memory map in 8051 family
0000H
0FFFH
0000H
1FFFH
0000H
7FFFH
8751
AT89C51
8752
AT89C52
4k
DS5000-32
8k 32k
from Atmel Corporation
from Dallas Semiconductor
41. Stack in the 8051Stack in the 8051
The register used to access
the stack is called SP (stack
pointer) register.
The stack pointer in the 8051
is only 8 bits wide, which
means that it can take value
00 to FFH. When 8051
powered up, the SP register
contains value 07.
7FH
30H
2FH
20H
1FH
17H
10H
0FH
07H
08H
18H
00H
Register Bank 0
)Stack) Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
42.
43. Instruction SetInstruction Set
5 Groups5 Groups
Arithmetic Operation GroupArithmetic Operation Group
Logical Operation GroupLogical Operation Group
Data Transfer GroupData Transfer Group
Boolean Variable Manipulation GroupBoolean Variable Manipulation Group
Program Branching GroupProgram Branching Group
44. Instruction SetInstruction Set
5 Groups5 Groups
Arithmetic Operation GroupArithmetic Operation Group
Logical Operation GroupLogical Operation Group
Data Transfer GroupData Transfer Group
Boolean Variable Manipulation GroupBoolean Variable Manipulation Group
Program Branching GroupProgram Branching Group
51. 5151
Instruction SetInstruction Set
5 Groups5 Groups
Arithmetic Operation GroupArithmetic Operation Group
Logical Operation GroupLogical Operation Group
Data Transfer GroupData Transfer Group
Boolean Variable Manipulation GroupBoolean Variable Manipulation Group
Program Branching GroupProgram Branching Group
56. 5656
Instruction SetInstruction Set
5 Groups5 Groups
Arithmetic Operation GroupArithmetic Operation Group
Logical Operation GroupLogical Operation Group
Data Transfer GroupData Transfer Group
Boolean Variable Manipulation GroupBoolean Variable Manipulation Group
Program Branching GroupProgram Branching Group
57. 5757
Data Transfer GroupData Transfer Group
MOV A,DirectMOV A,Direct
MOV A,RnMOV A,Rn
MOV A,@RiMOV A,@Ri
MOV A,#DataMOV A,#Data
MOV Rn,DirectMOV Rn,Direct
MOV Rn,@RiMOV Rn,@Ri
MOV Rn,#DataMOV Rn,#Data
58. 5858
Data Transfer GroupData Transfer Group
MOV Direct,DirectMOV Direct,Direct
MOV Direct,RnMOV Direct,Rn
MOV Direct,@RiMOV Direct,@Ri
MOV Direct,#DataMOV Direct,#Data
MOV Direct,AMOV Direct,A
MOV @Ri,AMOV @Ri,A
MOV @Ri,#DataMOV @Ri,#Data
59. 5959
Data Transfer GroupData Transfer Group
MOV @Ri,DirectMOV @Ri,Direct
MOV DPTR,#DATA16MOV DPTR,#DATA16
MOVC A,@A+DPTRMOVC A,@A+DPTR
MOVC A,@A+PCMOVC A,@A+PC
MOVX A,@RiMOVX A,@Ri
MOVX @Ri,AMOVX @Ri,A
MOVX @DPTR,AMOVX @DPTR,A
60. 6060
Data Transfer GroupData Transfer Group
PUSH DirectPUSH Direct
POPPOP DirectDirect
XCHXCH A,RnA,Rn
XCHXCH A,DirectA,Direct
XCHXCH A,@RiA,@Ri
XCHD A,@RiXCHD A,@Ri
61. 6161
Instruction SetInstruction Set
5 Groups5 Groups
Arithmetic Operation GroupArithmetic Operation Group
Logical Operation GroupLogical Operation Group
Data Transfer GroupData Transfer Group
Boolean Variable Manipulation GroupBoolean Variable Manipulation Group
Program Branching GroupProgram Branching Group
62. 6262
Boolean Variable Manipulation GroupBoolean Variable Manipulation Group
CLRCLR CC
CLRCLR bitbit
SETBSETB CC
SETB bitSETB bit
CPLCPL CC
CPLCPL bitbit
65. 6565
Instruction SetInstruction Set
5 Groups5 Groups
Arithmetic Operation GroupArithmetic Operation Group
Logical Operation GroupLogical Operation Group
Data Transfer GroupData Transfer Group
Boolean Variable Manipulation GroupBoolean Variable Manipulation Group
Program Branching GroupProgram Branching Group
66. 6666
Program Branching GroupProgram Branching Group
ACALLACALL addr11addr11
LCALLLCALL addr16addr16
RETRET
RETIRETI
AJMPAJMP addr11addr11
LJMPLJMP addr16addr16
SJMPSJMP relrel
72. TMOD RegisterTMOD Register::
Gate : When set, timer only runs while INT(0,1) is
high.
C/T : Counter/Timer select bit.
M1 : Mode bit 1.
M0 : Mode bit 0.
73. TCON Register:TCON Register:
TF1: Timer 1 overflow flag.
TR1: Timer 1 run control bit.
TF0: Timer 0 overflag.
TR0: Timer 0 run control bit.
IE1: External interrupt 1 edge flag.
IT1: External interrupt 1 type flag.
IE0: External interrupt 0 edge flag.
IT0: External interrupt 0 type flag.
90. 9090
SERIAL PORT– Mode 0
The Serial Port in Mode-0 has the following
features:
• Serial data enters and exits through RXD
• TXD outputs the shifl clock
• 8 bits are transmitted / received
• The baud rate is fixed at (1/12) of the
oscillator frequency
93. 9393
SERIAL PORT– Mode 1
The Serial Port in Mode-1 has the following features:
• Serial data enters RXD
• Serial data exits through TXD
• On receive, the stop bit goes into RB8 in SCON
• 10 bits are transmitted / received
Start bit (0)
Data bits (8)
Stop Bit (1)
• Baud rate is determined by the Timer 1 over
flow rate.
96. 9696
SERIAL PORT– Mode 2
The Serial Port in Mode-2 has the following features:
• Serial data enters RXD
• Serial data exits through TXD
• 9th data bit (TB8) can be assign value 0 or 1
• On receive, the 9th
data bit goes into RB8 in SCON
• 11 bits are transmitted / received
Start bit (0)
Data bits (9)
Stop Bit (1)
• Baud rate is programmable – (1/32) or (1/64)
of the oscillator frequency
99. 9999
SERIAL PORT– Mode 3
The Serial Port in Mode-3 has the following features:
• Serial data enters RXD
• Serial data exits through TXD
• 9th data bit (TB8) can be assign value 0 or 1
• On receive, the 9th
data bit goes into RB8 in SCON
• 11 bits are transmitted / received
Start bit (0)
Data bits (9)
Stop Bit (1)
• Baud rate is determined by the Timer 1
over flow rate.
105. 105105
INTERRUPTS
The Interrupt structure has the following features:
• 6 sources / 5 vectored interrupts
• Each interrupts can be individually programmable
• Each interrupts can have two priority levels
• Priority levels can be programmed
• All interrupts can be masked by a single bit - EA
• External interrupt type can be programmed
Edge triggered
Level Triggered
106. Interrupt Enable Register :Interrupt Enable Register :
EA : Global enable/disable.
--- : Undefined.
ET2 :Enable Timer 2 interrupt.
ES :Enable Serial port interrupt.
ET1 :Enable Timer 1 interrupt.
EX1 :Enable External 1 interrupt.
ET0 : Enable Timer 0 interrupt.
EX0 : Enable External 0 interrupt..
122. 122122
82558255
Programmable Peripheral InterfaceProgrammable Peripheral Interface
X X X
Not Used
Bit Select
000 = Bit 0
001 = Bit 1
010 = Bit 2
011 = Bit 3
100 = Bit 4
101 = Bit 5
110 = Bit 6
111 = Bit 7
D0D0D1D1D2D2D3D3D4D4D5D5D6D6D7D7
0
BSR Mode Selected
Control Word – BSR Mode
Bit Set/Reset
1 = Set
0 = Reset
148. 148148
1) Stepper Motor Control
2) Matrix Keyboard
3) Dynamic 7 Segment Display
4) Analog to Digital converter
5) DC Motor Control
6) LCD Display
7) Serial Data Transfer
149. STEPPER MOTOR CONTROLSTEPPER MOTOR CONTROL
Stepper MotorStepper Motor
Winding DiagramWinding Diagram
SpecificationsSpecifications
Rotation / Excitation methodsRotation / Excitation methods
Clockwise / Anti Clockwise SequenceClockwise / Anti Clockwise Sequence
Single & Multi Winding ExcitationSingle & Multi Winding Excitation
Driving unit Digital & AnalogDriving unit Digital & Analog
152. MATRIX KEYBOARDMATRIX KEYBOARD
General Keyboard StructureGeneral Keyboard Structure
Adv & Disadv of General KeyboardAdv & Disadv of General Keyboard
Layout of Matrix KeyboardLayout of Matrix Keyboard
Scanning and Sense LinesScanning and Sense Lines
Scan SequenceScan Sequence
Key De-bounce MethodsKey De-bounce Methods
163. ANALOG TO DIGITAL CONVERTERANALOG TO DIGITAL CONVERTER
ADCADC
WorkingWorking
TypesTypes
ApplicationsApplications
Specifications –Specifications – No of Bits, i/p, o/p etcNo of Bits, i/p, o/p etc
166. DC MOTOR CONTROLDC MOTOR CONTROL
DC MotorDC Motor
Speed Control MethodsSpeed Control Methods
Advantage of PWM MethodAdvantage of PWM Method
Driving CircuitDriving Circuit
172. 172172SKB'sSKB's
Pin number Symbol Level I/O Function
1 Vss - - Power supply (GND)
2 Vcc - - Power supply (+5V)
3 Vee - - Contrast adjust
4 RS 0/1 I
0 = Instruction input,
1 = Data input
5 R/W 0/1 I
0 = Write to LCD module,
1 = Read from LCD module
6 E 1, 1->0 I Enable signal
7 DB0 0/1 I/O Data bus line 0 (LSB)
8 DB1 0/1 I/O Data bus line 1
9 DB2 0/1 I/O Data bus line 2
10 DB3 0/1 I/O Data bus line 3
11 DB4 0/1 I/O Data bus line 4
12 DB5 0/1 I/O Data bus line 5
13 DB6 0/1 I/O Data bus line 6
14 DB7 0/1 I/O Data bus line 7 (MSB)
173. 173173SKB'sSKB's
Instruction
Code
Description
Executi
on time
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Clear
display 0 0 0 0 0 0 0 0 0 1
Clears display and returns cursor to the home position (address
0).
1.64mS
Cursor
home 0 0 0 0 0 0 0 0 1 *
Returns cursor to home position (address 0). Also returns display
being shifted to the original position. DDRAM contents remains
unchanged.
1.64mS
Entry mode
set 0 0 0 0 0 0 0 1 I/D S
Sets cursor move direction (I/D), specifies to shift the display
(S). These operations are performed during data read/write.
40uS
Display
On/Off
control
0 0 0 0 0 0 1 D C B
Sets On/Off of all display (D), cursor On/Off (C) and blink of
cursor position character (B).
40uS
Cursor/disp
lay shift 0 0 0 0 0 1 S/C R/L * *
Sets cursor-move or display-shift (S/C), shift direction (R/L).
DDRAM contents remains unchanged.
40uS
Function
set 0 0 0 0 1 DL N F * *
Sets interface data length (DL), number of display line (N) and
character font(F).
40uS
Set
CGRAM
address
0 0 0 1 CGRAM address
Sets the CGRAM address. CGRAM data is sent and received
after this setting.
40uS
Set
DDRAM
address
0 0 1 DDRAM address
Sets the DDRAM address. DDRAM data is sent and received
after this setting.
40uS
Read busy-
flag and
address
counter
0 1 BF CGRAM / DDRAM address
Reads Busy-flag (BF) indicating internal operation is being
performed and reads CGRAM or DDRAM address counter
contents (depending on previous instruction).
0uS
Write to
CGRAM or
DDRAM
1 0 write data Writes data to CGRAM or DDRAM. 40uS
Read from
CGRAM or
DDRAM
1 1 read data Reads data from CGRAM or DDRAM. 40uS
versatility 多用途的 : any number of applications for PC
processor 整合到整個系統中 , 你只看到此系統的外觀 , 應用 , 感覺不到有 processor 在其中 . Embedded system 通常只有一項應用 , 而 PC 有許多 applications (game, accounting, fax, mail...) A printer is an example of embedded system since the processor inside it performs one task only.
Program is to read data from P0 and then send data to P1