The document describes the design of a 10-bit, 50MS/s pipelined analog-to-digital converter (ADC) implemented in a 180nm CMOS process. Key aspects of the design include a flip-around track-and-hold amplifier, 1.5-bit per stage pipeline stages with gain of 2, and operational transconductance amplifiers optimized for power efficiency. Simulation results show the ADC achieves 9.64 effective bits, consumes 24.5mW of power, and has a figure of merit better than prior published pipelined ADCs of similar resolution and speed.

1. A Low-Power, Medium-Resolution, High-Speed
CMOS Pipelined ADC
D. Meganathan Axel Jantsch
Department of Electronics Engineering, Department of ICT,
Madras Institute of Technology, Royal Institute of Technology (KTH),
Anna University, Chennai, India-600044. Stockholm, Sweden-164 40.
Each pipeline stage consists of a multiplying digital-to-
Abstract— This paper presents the systematic design approach of
a low-power, medium-resolution, high-speed pipelined Analog-to-
analog converter (MDAC) and an analog-to-digital sub
Digital Converter (ADC). The ADC is implemented in 180nm converter (ADSC). Each pipelined stage generates a coarse
digital CMOS technology. The converter achieves signal-to-noise ADSC output and a reconstructed residue signal for the later
distortion ratio of 59.8 dB, spurious-free dynamic range of 89 dB stages. These digital codes are cascaded to obtain overall
and effective number of bits of 9.64-bits at sampling speed of resolution of the ADC. Pipeline ADC operates using two-
50MHz with an input signal frequency of 4MHz. The peak clock phases. During the phase Φ1 , CLK1 is high and the
differential-nonlinearity of the converter is 0.28/-0.17LSB and
integral-nonlinearity of the converter is +0.42/-0.41LSB. The phase Φ 2 , CLK2 is high. During the Φ1 period, the first stage
proposed 10-bit, 50MS/sec pipelined ADC consumes 24.5mW acquires the signal and in the next half cycle, it generates the
amount of power from 1.8V supply. reconstructed residue for the second stage. The second stage
Keywords- Analog-to-digital Sub Converter (ADSC), Signal-to- acquires the signal during the conversion state of the first
noise distortion ratio (SNDR), Spurious Free Dynamic Range
stage. In this paper, Section II discusses the design of THA,
(SFDR), Dynamic Range (DR), Operational Transconductance
MDAC and OTA. Section III discusses the low power circuit
Amplifier (OTA).
techniques to optimize the performance of the ADC. Section
IV shows the performance of the ADC followed with the
I. INTRODUCTION conclusion in Section V.
High-speed and medium-resolution Analog-to-Digital II. DESIGN OF A THA, MDAC and OTA
Converters (ADCs) are widely used in commercial
applications including data communication and image signal A. THA Design
processing. In such applications, the reduction of power
consumption associated with high speed sampling and high The capacitor flip-around THA is shown in Figure 2. No
linearity is one key design issue in enhancing the portability charge-transfer occurs in this scheme and only two capacitors
and battery operation. Among many ADC architectures, are used. During the track phase (Φ1-phase), the differential
pipelined ADC is proved to be the most suitable for high- input signal is sampled by the input capacitors. During the
speed, medium-resolution and low-power consumption [1]. A hold phase (Φ2-phase), the input capacitors are flipped over by
generic pipelined ADC is shown in Figure 1. First stage of the connecting their bottom plates to the output of the amplifier.
pipelined ADC is front-end track-and-hold amplifier (THA). It By doing this, both the common-mode and differential-mode
is followed by ‘m’ number of cascaded pipeline stages except charges are transferred [2].
the final stage contains a simple flash ADC.
Front End
Q(Φ1 ) = Q(Φ 2 ) (1)
THA Ф1-acquire Ф2- convert -CS (VIN-VCMI) = -CS (VOUT -VCMI) (2)
Ф2-convert Ф1- acquire Hence VOUT = VIN (3)
VIN
THA Stage 1 Stage 2 Stage m
When parasitic capacitance is ignored, the feedback factor
CLK1 β of a flip-around THA is 1, whereas the feedback factor of a
DFF
CLK2 charge-transferring THA [3] is 0.5. As the feedback factor of
DFF DFF
the flip-around THA is twice as large compared to the charge-
transferring THA, it requires only half of OTA gain-
DFF DFF DFF
bandwidth to produce the same closed-loop bandwidth. Thus,
the same performance can be achieved with much less power
Digital Error Correction Logic by using the flip-around architecture. The nonlinearity error
Einput_ref produced by the pipelined ADC is given as
D1 D2 Dm-1 Dm
CLK1 Ф1 m-1
E i+1
CLK2 Ф2
Einput_ref = E1 + ∑ Gi
i=1
(4)
Figure 1. Generic Pipeline ADC
978-1-4244-8971-8/10$26.00 c 2010 IEEE

2. used to select the DASC output voltage according to the
Φ2 ADSC input.
VIN+ Φ1 CS CS + CF CS
X VOUT-
+ VO U T = VIN - D VR E F (6)
- CF CF
VCMI Φ 2e VCMI Φ1e Φ1 VIN+
VCMO
VIN- Φ1 Φ 2e Φ1e Φ1 CF
+ Φ1
X
- VOUT+ VDASC+ -
CS Φ2 VIN+ Φ1 CS Φ
Φ2 VOUT
Bootstrap +
Switch VCMI Φ2 VCMI Φ1e - Φ1 V
CMOS
VIN- Φ1 Φ2 Φ1e
CMO
Switch + Φ
- 1
CS Φ2 VOUT+
CMOS SWITCH VDASC- Φ2
Figure. 2 Switched Capacitor Flip-around THA
CF Φ1
Note-Ф1 and Ф2 are non-overlapping clock phases used for track
and hold operations. Ф1e and Ф2e are the early clock phases of Ф1 Note CS=CF VIN-
and Ф2 respectively. Early clock phases are used to perform bottom VDASC+
plate sampling which minimizes the charge injection error [4] [5]. VIN+ B-bit Reference
1.5-bit Selector
The thermal noise contribution of the pipelined ADC is VIN- ADSC VDASC-
VDASC =DVREF
2
Vni 2
Vn i 2 stage2 2 VREF V B-bit
Vn i =
THA
+ Vni stage1
2
+ 2 2
+........... Vni stagem
m-1
(5) -
4 + 4
REF
-VREF +VREF
1 G1 G1 G 2
∏
j=1
Gj
2
Figure 3 1.5-bit per stage MDAC section
Based on Equations (4) & (5), it has been observed that the C. OTA Design
performance of the track-and-hold (T/H) circuit dominates the
overall ADC dynamic characteristics and plays a major role in The OTA is implemented using telescopic architecture.
determining the Spurious Free Dynamic Range (SFDR) and One of the tradeoffs of telescopic architecture is less output
the Signal-to-Noise and Distortion Ratio (SNDR) of the voltage swing. Another tradeoff is that the input and output
system [6]. Therefore improving the performance of the THA common-mode levels cannot be set independently of one
can improve the SFDR and SNDR. The nonlinearity caused by another or equal to one another. The first tradeoff reduces the
the input sampling switches at low supply voltage lowers dynamic range of OTA. Dynamic Range (DR) of OTA can be
SFDR, SNDR and DR. Using an NMOS switch as a sampling maintained high by reducing thermal noise contribution of
switch in the proposed T/H circuit has two limitations: input- OTA. Selecting the larger value of sampling capacitors
dependent ON-resistance and input-dependent charge minimize thermal noise and capacitor mismatch nonlinearity
injection. They will lead to nonlinear signal distortion. The errors. Thermal noise contribution of OTA can be further
signal dependent nonlinearity error associated with switches reduced by selecting lesser gm value for cascode transistors
can be reduced by using bootstrap switches. However, the and larger gm value for signal transistors. Larger value of gm
design of bootstrap switch is complicated. Hence it is used in of signal transistors also pushes the Unity-Gain Frequency
some critical places of the proposed ADC circuit. The other (UGF) to the higher value. The second tradeoff produces
switches are CMOS switches which give better performance nonlinearity error. The nonlinearity error can be minimized by
than NMOS switches. high loop gain of OTA. To achieve larger loop-gain, gain-
boosting is used with the cascode transistors, as shown in
B. Design of MDAC Section Figure 4. Normally gain-boosting amplifier has pole-zero
doublet, which reduces settling speed of OTA. This can be
The MDAC combines the functions of a track-and-hold, overcome by setting the bandwidth of the gain-boosting
a DASC, a subtractor and a gain amplifier. Each MDAC amplifiers relative to that of the main amplifier. The unity-
section is implemented using the switched capacitor circuit gain-bandwidth of the gain-boosted amplifier is designed to
with the resolution of 1.5-bit-per-stage and an interstage gain satisfy the following criterian [8] [9].
of 2 as shown in Figure 3. [7]. During the track phase
( Φ1 =HIGH), the input signal VIN is applied to the set of βωMain < ωgain-boosted < ω2Pole-Main (7)
capacitors CS and CF and simultaneously quantized per-stage Where ωMain and ω2Pole-Main are the unity-gain-frequency and
resolution of Beff +1 bit through the ADSC function which has second pole of a main amplifier. ωgain-boosted is the unity-gain-
V V frequency of gain boosted amplifier. The gain-boosting
the threshold value of + REF and - REF . At the end of amplifiers, represented by amplifiers A1 and A2 in Figure 4,
4 4 are also implemented with the telescopic topology to provide
the track phase, VIN is tracked across CS and CF and output of the largest possible gain by scaled replica of the Main
the ADSC is latched. During the hold phase ( Φ 2 =HIGH), CF amplifier. Switched-capacitor common mode feedback
closes negative feedback path around the OTA, the top plate controls stability of OTA. The unity-gain-frequency of gain-
of CS is switched to the DASC output. The output of ADSC is boosted telescopic architecture achieves 400MHz which is

3. suitable for 50MS/sec sampling rate applications. The The charge-sharing type comparator with output latch
differential output voltage swing of the OTA is 0.9V. The consumes the power of 55µW.
OTA consumes the power of 3.6mW. The gain and phase
angle versus frequency plots of OTA used in THA is shown in IV SIMULATION RESULTS
Figure 5. VDD
The layout of proposed low-power 10-bit, 50MS/sec
VBIAS pipelined ADC is shown in Figure 7. The total power
M7 M8
+ - consumption of the ADC is 24.5mW. For measuring the
+ A1 INL/DNL performance of the ADC a slow moving ramp input
- + M6 of 24 KHz is applied to the ADC input. The post-layout
M5 simulated differential nonlinearity and integral nonlinearity for
M3 M4 24 KHz full scale ramp signal at 50MS/s sampling rate are
- + illustrated in Figures 8 and 9 respectively. The dynamic
A2
VIN-
linearity of the ADC is characterized by analyzing a fast
VIN+
M1 + - M2 Fourier transform (FFT) of the output codes with a single-tone
input. The simulated output FFT spectrum with 4 MHz and
VCMFB Nyquist rate single-tone sinusoidal inputs are shown in Figure
M9
10(a) and 10(b) respectively. The input is 0.9V at the
Figure 4 Gain-boosted telescopic OTA sampling rate of 50MS/sec. Performance of the pipelined
ADC is summarized in Table 1.
Digital
Error THA MDAC1 MDAC2
Correction
Logic
MDAC3 MDAC4 MDAC5
ADSCs
Figure 5 Gain and phase angle Vs frequency MDAC6 MDAC7 MDAC8
CLK
III. LOW POWER CIRCUIT TECHNIQUES
Figure 7 Layout of 10-bit 50MS/s pipelined ADC
A. Regenerative Latch Comparator
Resistive divider type regenerative latch uses a positive
feedback to implement comparator (ADSC) block [10] [11].
The architecture of proposed comparator is same as resistive
divider comparator except the presence of active restore
transistor, M5 connected in between the output nodes as shown
in Figure 6. M5 transistor brings the VOUT+ and VOUT- in Figure 8 Differential nonlinearity code
common-mode voltage level during reset phase. Hence it is
named as charge-sharing comparator. The charge-sharing
comparator takes the decision from common-mode voltage
(Vcommon) to the output logic level which reduces the dynamic
power dissipation and settling time of the comparator
compared to the conventional regenerative latch comparators.
In reset phase, normally the charge sharing comparator output
will be in meta-stable state. But to drive the digital circuit, Figure 9 Integral nonlinearity code
either a logic high or logic low is required. Hence the output
latch is added to the comparator.
VDD
CLK
M6
VOUT+
M4 M4’ VDD
VOUT - VOUT+ Vcommon
M5 ’
VOUT-
M8 M8
CLK M3’ Reset
M3
CLK Phase
Comparison
VREF- VIN + VIN - VREF + Phase
M2 M1 M1’ M2’ Figure 10 (a) Figure 10(b)
CLK M7 Figure 10 (a) & (b) 1024 points FFT spectrum for 4MHz and 24
MHz
Figure 6 Charge sharing comparator

4. Figure of merit is the unit used to evaluate the ADC by consuming less amount of power. Bootstrap and
performance of the ADC. More recently normalizing for the bottom-plate sampling techniques are incorporated to
supply voltage is added to the Figure of Merit (FOM), minimize nonlinearity errors. A modified dynamic
especially meaningful for the CMOS cores [12]. regenerative comparator and stage scaling further optimizes
the overall power consumption. The FOM reveal that the
Power VDD performance of the proposed ADC is better compared to the
Figure of Merit (FOM) = (8)
2ENOB fS previous published works.
The performance of this work is compared with that of
other pipelined ADCs referred to in publications based on REFERENCES
Equation (8) is shown in Table 2. The FOM of the proposed [1]. Annema A.J., Nauta B., van Langevelde R. and Tuinhout H., “Analog
ADC is lower than the reported ADCs. Circuits in Ultra-Deep-Submicron CMOS”, IEEE Journal of Solid-State
Circuits, Vol. 40, No. 1, pp. 132-143, 2005
[2]. Yang W., Kelly D., Mehr I., Sayuk M.T. and Singer L.,
Table 1 ADC performance summary “A 3-V 340-mW 14-b 75-MSample/s CMOS ADC With 85-dB SFDR at
Nyquist Input”, IEEE Journal of Solid-State Circuits, Vol. 36, No. 12, pp.
UMC-180nm digital CMOS 1931-1936, 2001.
Technology technology [3]. Lewis S.H. and Gray P.R., “A Pipelined 5-Msamples/s 9-bit Analog-to-
Digital Converter”, IEEE Journal of Solid-State Circuits,Vol. 31, No. 22, pp.
Resolution 10 bits 954-961, 1987.
[4]. Allstot D.J. and Black W.C. Jr., “Technological Design Considerations
Architecture Pipelined for Monolithic MOS Switched-Capacitor Filtering Systems”, Proceedings of
the IEEE Vol. 71, No. 8, pp. 967-986, 1983.
Conversion rate 50MS/s
[5]. Lee K.L. and Meyer R.G., “Low-Distortion Switched-Capacitor Filter
Supply voltage 1.8V Design Techniques”, IEEE Journal of Solid-State Circuits,
Vol. 20, No. 6, pp. 1103-1113, 1985.
DNL +0.28/-0.17 [6]. Jiang. S., Manh .A.D and K.S. Yeo, “An 8-bit 200-MSample/s Pipelined
ADC With Mixed-Mode Front-End S/H Circuit”, IEEE Transcations on
INL +0.42/-0.41 Circuits and Systems - I: Regular Paper, Vol. 55, NO. 6, pp-1430-1440, 2008.
SNR @ 4MHz/Nyquist rate 60.2dB/59.7dB [7]. Picolli L., Rossini A., Malcovati P., Maloberti F., Borghetti F. and
Baschirotto A. “A Clock-Less 10-bit Pipeline-Like A/D Converter for Self-
SNDR @ 4MHz/Nyquist rate 59.8dB/57.9dB Triggered Sensors”. IEEE Journal of Solid-State Circuits, Vol. 43, No.2, pp.
312-320, 2008.
THD @ 4MHz/Nyquist rate 83.2dB/81.8dB
[8]. Ingino J.M and Wooley A, “A Continuously Calibrated 12-b, 10-MS/s,
SFDR @ 2MHz/Nyquist rate 89dB/86.6dB 3.3-V A/D Converter”, IEEE Journal of Solid-State Circuits, IEEE, Vol. 33,
No. 12, pp.1920-1931, 1998.
ENOB @ 4MHz/Nyquist rate 9.64/9.33 bits [9]. Chuang S.Y. and Sculley T.L., “A Digitally Self-Calibrating 14-bit 10-
MHz CMOS Pipelined A/D Converter”, IEEE Journal of Solid-State Circuits,
Dynamic range @ 4MHz 59.8dB Vol. 37, No. 6, pp. 674-683, 2002.
Analog:19.6mW [10]. Byung-Moo Min, Kim P., Bowman F.W., Boisvert D.M. and Aude A.J,
“A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC”, IEEE Journal of
Power dissipation Digital:4.9mW Solid-State Circuits, Vol. 38, No. 12, pp. 2031-2039, 2003.
Total power:24.5mW [11]. Cho T.B. and Gray P.R., “A 10-b, 20 Msample/s, 35-mW Pipeline A/D
converter”, IEEE Journal of Solid-State Circuits, Vol. 30, No. 3, pp. 166-172,
1995.
[12]. Honda K., Furuta M. and Kawahito S., ‘A Low-Power Low-Voltage 10-
bit 100-MSample/s Pipeline A/D Converter using Capacitance Coupling
Table 2 Performance Comparison Techniques’, IEEE Journal of Solid-State Circuits, Vol. 42, No. 4, pp.757-
765, 2007.
Sl. Year of Authors FOM [13]. Ray .S, and Song. B.S, “A 13-b Linear, 40-MS/s Pipelined ADC With
No publication Self-Configured Capacitor Matching”, IEEE Journal of Solid-State Circuits,
Vol. 42, No. 3,pp. 463-474, 2007.
1. 2007 Sourja Ray, and Bang-Sup 6.13
Song , [13] [14]. Byung-Geun Lee B.G, Min B.M, Manganaro G. and. Valvano J.W, “A
14-b 100-MS/s Pipelined ADC With a Merged SHA and First MDAC” IEEE
2. 2008 Byung-Geun Lee et al., [14] 2.03 Journal of Solid-State Circuits, Vol. 43, No. 12,pp. 2613-2619, 2008.
3. 2009 Haoyue Wang et al., [15] 14.41
4. 2009 Naga Sasidhar et. al [16] 2.17 [15]. Wang H. Wang. X. Hurst P.J and Lewis S. H., “ Nested Digital
Background Calibration of a 12-bit Pipelined ADC Without an Input
5. 2010 Jin-Fu Lin 1.38 SHA”,IEEE Journal of Solid-State Circuits, Vol. 44, No. 10, pp.2780-2789,
et al., [17] 2009.
6. 2010 This Work (Post-Layout 1.10 [16]. Sasidhar N, Kook Y.J , Takeuchi .S Hamashita .K, Takasuka. K,
Simulation Results) Hanumolu P.K , Moon U.K, “A Low Power Pipelined ADC Using
Capacitorand Opamp Sharing Technique With a Scheme to Cancel the Effect
of Signal Dependent Kickback”, IEEE Journal of Solid-State Circuits, Vol.
V. CONCLUSION 44, No. 9, pp.2392-2401, 2009,
The systematic design approach of a low-power, medium- [17]. Lin J.F, Chang S.J., Liu. C.C and Huang C.H., ‘‘A 10-bit 60-MS/s Low-
Power Pipelined ADC With Split-Capacitor CDS Technique’’, IEEE
resolution and high-speed ADC is presented. The performance Transcations on Circuits and Systems -II: Express Briefs, Vol. 57, No. 3, , pp-
of the THA is improved by low-power high-gain, high- 163-167, 2010.
bandwidth OTA. This improves the overall performance of the