Peripheral Interface

1. Architecture of 8255

2. 8255 - Programmable Peripheral Interface
• To communicate with the outside world, Microprocessor use
Peripherals (I/O devices).
• Commonly used input devices are Keyboards, A/D converters etc.,
and output devices are CRT, Printers, LEDs etc.
• These input and output devices are called Peripherals (or) I/Os.
• Peripherals are connected to the microprocessor through electronic
circuits known as interfacing circuits.

3. 8255 - Programmable Peripheral Interface
• Generally, each I/O devices requires a separate interfacing circuit.
• The interfacing circuits convert the data available from an input device into
compatible format for the computer.
• The interface associated with the output device converts the output of the
microprocessor into the desired peripheral format.
• To simplify the work, the designers of microprocessor manufacturers have
developed a number of general purpose and special purpose single chip
interfacing devices.

4. Main functions of the interfacing devices
(i) To relieve the processor from time-consuming activities like
keyboard scanning and display refreshing.
(ii) To interface slow I/O devices to the fast microprocessor unit
and the data transfer between them can be effected more efficiently.

5. Block Diagram of 8255

6. 1. Data Bus Buffer
• This three-state bi-directional 8-bit buffer is used to interface the
82C55A to the system data bus.
• Data is transmitted or received by the buffer upon execution of input
or output instructions by the CPU.
2. Read/Write and Control Logic
• Read- This control signal enables the Read operation. When the signal
is low, the CPU reads data from a selected I/O port of the 8255.
• Write- This control signal enables the Write operation. When the
signal is low, the CPU writes data or controls word into 8255.
• Control Logic- The control logic block, accepts control bus signals as
well as inputs from the address bus and generates the commands to
the individual group control of Group A and Group B.

7. i. (A0 and A1) Port Select 0 and Port Select 1 :
• These input signals, in conjunction with the RD and WR inputs,
control the selection of one of the three ports.
ii. (CS) Chip Select :
• A "low" on this input pin enables the communication between the
82C55A and the CPU.
iii. (RD) Read :
• A "low" on this input pin enables 82C55A to send the data or status
information to the CPU on the data bus.

8. • Group A and Group B Controls
• The Group A and Group B Control Blocks receives control words from
the CPU and issues appropriate commands to the ports associated
with it.
• The Group A Control block controls port A and PC7, — PC4, while the
Group B Control block controls Port B and PC3, — PC0.
• Port A: It has an 8-bit latched and buffered output and an 8-bit input
latch. It can be programmed in three modes; Mode 0, Mode 1 and
Mode 2.
• Port B: It has an 8-Bit data I/O latch/buffer and an 8-bit data input
buffer. It can be programmed in Mode 0 and Mode 1.
• Port C: It has one 8-Bit unlatched input buffer and an 8-bit output
latch/buffer,

9. The 8255 can operate in three I/O modes :
• Mode 0: Simple input/ output
• Mode 1: Input/ output with handshake
• Mode 2 : Bi-directional I/O data transfer