2. COMPUTER
ARCHITECTURE

3. Presented To:
Sir Arslan Ali Mansab
Presented By:
• Tariq Ahmed (20-Arid-4421)
• Muhammad Tayyab (20-Arid-4405)
• Saddam Hussain (20-Arid-4399)

4. Contents
• Main Memory Performance Issues
• Performance Measurement
• Semiconductor Main Memory
• Error Correction
• Advanced DRAM Organization

5. Main Memory
Performance Issues

6. Main Memory
• The main memory is the fundamental storage unit in a computer system.
• It is associatively large and quick memory and saves programs and information
during computer operations.
• The technology that makes the main memory work is based on semiconductor
integrated circuits.

7. Main Memory Performance Issues
• Usually, not all data can be stored in the processor's caches.
• Some cache misses are inevitable for large applications. Therefore, the
performance of a system's memory subsystem is the next area that can impact an
application's performance.
• Both physical and virtual memory issues can cause problems.

8. Physical Memory
The amount of physical main memory available on a particular system depends on
four criteria:
• The number of physical slots available for memory boards
• The density of RAM chips used to build the memory boards
• The number of bits used to address physical memory
• The amount of memory supported by the operating system

9. Performance
Measurement

10. Clock Speed
• The time between pulses is called the cycle time.
• A3GHz Processor has 3000 million cycles per second
However it cannot be taken for granted that the computer with the highest clock speed is the
faster system as the number of cycles needed to carry out an instruction may vary between
the processors.
Which is faster – 3GHz Pentium processor or 3.2 GHz Pentium processor?
Which is faster – 3GHz Pentium processor or a 3 GHz AMD processor?

11. MIPS
• Millions of Instructions per Second = MIPS
• MIPS are a measure of how many millions of instructions the processor can
execute in one second.
• It cannot be taken for granted that the computer with the highest MIPS rate is the
faster system
Because
• There is no standard set of instructions and so some processors use simpler and
faster instructions than others.

12. FLOPS
• Floating Point Operations per Second = MIPS
• This is a measure of the arithmetic speed of a processor.
• The procedures involved in carrying out floating point multiplication are
basically the same in every processor
So
• FLOPS is a better measure than clock speed or MIPS when comparing system
performance.

13. Benchmarks
• Benchmarks are a standard set of a computer tasks designed to allow a
computer’s performance to be measured.

14. Semiconductor
Main Memory

15. Semiconductor Memory
• Semiconductor memory is an digital
electronic data storage device often
used as computer memory.
• Semiconductor memory is a type of
semiconductor device .

16. Semiconductor Memory Storage:
• There are two electronic data storage device used in semi conductor,
• Magnetic storage .
• Optical Storage.

17. Examples of Semiconductor Memory
• Examples of semiconductor memory includes Non-volatile memory such as
Read Only Memory (ROM), and Random Access Memory (RAM).
• It also includes volatile memory such as Static Random Access Memory (SRAM)
Or (DRAM) Dynamic Random Access Memory.

18. Read-Write Memories
Dynamic (DRAM)
• Stand for Dynamic Random Access Memory. It is a type of memory that is used
in most computer .
• DRAM required electric current to maintain it electric state.
• The Electric charge of DRAM decreases with time that may result in loss of data.
• DRAM is recharged or refreshed again and again to maintain it data.

19. Read-Write Memories
Static (SRAM)
• Stand for Static Random Access Memory. The memory cell are made from digital
gates.
• CPU does not need to wait to access data from SRAM during processing.
• That is why it is faster than DRAM. It utilize less power than DRAM.
• SRAM is more expensive.

20. Error
Correction

21. Error Correction
• Error correction: are used to detect and
correct the errors when data is
transmitted from the sender to receiver.

22. Error Correction Techniques
There are two types of Error Correcting Techniques :
• Single Bit Error Correction
• Burst Error Correction.

23. Types of Errors
• Single Bit Error Correction:-
Only one bit in the data unit has changed.
• Burst Error Correction :-
It means that two or more bits in the data unit has changed.

24. Advanced DRAM
Organization

25. DRAM
• DRAM stands for Dynamic Random
Access Memory.
• It is a type of volatile memory used in
computers and electronic devices.
• DRAM provides temporary storage for
data that can be accessed randomly.
• It plays a vital role in computer
performance and data handling.

26. Cont..
Importance of DRAM
• Primary Memory
• Fast Data Access
• Multitasking
• System Performance
• Bridging CPU and Storage
• Real-time applications

27. Traditional DRAM Organization
• Traditional DRAM consists of an array of memory cells organized into rows and columns.
• Each memory cell stores a single bit of data, represented by a charge in a capacitor.
• The memory cells are accessed by specifying a row address and a column address.
• Row address: It refers to the specific row in the memory array where data is stored or
retrieved.
• Column address: It points to the column within the selected row where data is
accessed.
• Data storage: DRAM stores data in the form of electrical charges in capacitors within
memory cells. The presence or absence of charge represents the binary values of 1 and 0.

28. Advanced DRAM Organization Techniques
• Advanced DRAM organization techniques optimize memory access and enhance
performance.
• These techniques include bank and sub-bank architecture, address mapping, rank
interleaving, parallelism, caching, and error correction mechanisms.
• They aim to overcome limitations such as access latency, limited bandwidth, and power
consumption in traditional DRAM.
• Advanced DRAM organization techniques improve data access speed, memory
bandwidth, and overall system performance.
• These techniques play a crucial role in high-performance computing, data centers, and
other memory-intensive applications.

29. Bank and Sub-bank Architecture
• Bank and sub-bank organization improves memory performance by increasing
parallelism and reducing access latency.
• Dividing the memory array into multiple banks allows for simultaneous access to
different memory locations.
• This increased parallelism enables higher memory bandwidth, leading to faster data
transfer and processing.
• Concurrent access to different rows or addresses within the memory array reduces
the overall access latency.
• The combination of increased parallelism and reduced access latency enhances
system performance, responsiveness, and overall efficiency.

30. Address Mapping and Rank Interleaving
• Mapping multiple addresses to physical memory locations involves the technique of
translating logical addresses to physical addresses in DRAM.
• It allows for efficient utilization of memory space by mapping different logical addresses to
specific physical locations.
• By mapping multiple addresses, the memory system can handle a larger address space,
accommodating more data and improving overall memory capacity.
• Utilizing multiple DRAM ranks involves using multiple independent memory modules within
a single DRAM package or across multiple packages.
• Multiple ranks enable parallelism, allowing for simultaneous data access and storage
operations across different ranks.
• This utilization of multiple ranks enhances memory bandwidth and overall system
performance, particularly in memory-intensive tasks.

31. Caching and Prefetching Mechanisms
• Caching in DRAM involves the use of small and fast memory caches, such as level 1 (L1) and level 2
(L2) caches, to store frequently accessed data.
• Caching helps reduce memory access latency by providing quicker access to frequently used data,
bypassing the slower main memory.
• Prefetching in DRAM is a technique that anticipates future memory accesses and proactively fetches
the data into the cache ahead of time.
• Prefetching aims to reduce latency by ensuring that the requested data is already available in the
cache when it is needed, avoiding delays in fetching it from the main memory.
• Other techniques for reducing memory access latency include burst mode access, where multiple
data items are transferred in a single burst, and pipelining, which allows for overlapping of memory
access and data processing operations.

32. Error Correction and Redundancy
• Error detection and correction methods in DRAM aim to ensure data integrity and improve the
reliability of memory operations.
• Error detection techniques, such as parity checking and cyclic redundancy check (CRC), detect
errors during data read and write operations.
• Error correction methods, like Error Correcting Code (ECC), go beyond error detection by
correcting single-bit errors and detecting multiple-bit errors in memory data.
• Utilizing redundancy in DRAM involves adding additional memory cells or storage elements
to provide redundancy for error recovery.
• Redundancy can be used for error correction, allowing for the restoration of data in case of
errors or failures in the main memory cells.
• By employing error detection and correction methods and leveraging redundancy, DRAM
systems can improve data integrity, enhance system reliability, and mitigate the impact of
errors on overall system performance.