Asus notebook training_actre_l3-2

ASUS Confidential 1
NB_MB Level 3-2
Training Materials

ASUS Confidential 2
Overview
 Chapter 1. NB Frame Structure P5~P34
 Chapter 2. POWER P35~P95
 Chapter 3. CHARGE P96~P121
 Chapter 4. CLOCK P122~P145
 Chapter 5. HDMI P146~P154
 Chapter 6. Touch Pad P155~P170
 Chapter 7. Keyboard P171~P183
 Chapter 8. AUDIO P184~P214

ASUS Confidential 3
Overview
 Chapter 9. MODEM P215~P225
 Chapter 10. USB P226~P235
 Chapter 11. PCMCIA P236~P241
 Chapter 12. IEEE 1394 P242~P259
 Chapter 13. Card Reader P260~P270
 Chapter 14. SATA P271~P276
 Chapter 15. ODD P277~P282
 Chapter 16. LAN P283~P298

ASUS Confidential 4
Overview
 Chapter 17. VGA P299~P309
 Chapter 18. LCD P310~P342
 Chapter 19. BIOS P343~P367
 Chapter 20. MEMORY P368~P437
 Chapter 21. POST CODE P438~P484
 Chapter 22. NEW CARD P485~P491

ASUS Confidential 5
Chapter 1
NB Frame Structure Repair
Guide

ASUS Confidential 6
Overview
 Introduction
 Diagram
 Q & A (Repair Experience)

ASUS Confidential 7
Introduction
 Intel Product
 AMD Product

ASUS Confidential 8
Intel Centrino Evolution
Centrino Centrino 2
Carmel Sonoma Napa Santa Rosa Montevina
CPU
Banias
(130nm)
Dothan
(90nm)
Yonah
(65nm, Dual
Core)L2=2MB
Merom
(65nm, Dual
Core)L2=4MB
Penryn
(45nm,Dual/Four
Core)L2=6MB
GMCH
(FSB)
Odem+
Montara-
GM
(400MHz)
Alviso
(533MHz)
Calistoga
(667MHz)
Crestine
(800MHz)
Cantiga GM/PM
(1066MHz)
ICH ICH4-M ICH6-M ICH7-M ICH8-M ICH9-M
Wi-Fi
Calexico
(b)
Calexico2
(a/b/g)
Golan
(a/b/g)
Golan 2
(n)
Echo peak
(n)

ASUS Confidential 9
Intel Chip Family & Comparison

ASUS Confidential 10

Diagram
 Sonoma Platform
 Napa Platform
 Santa Rosa Platform
 Montevina Platform

Sonoma Platform Diagram-1

Sonoma Platform Diagram-2

Napa Platform Diagram-1

Napa Platform Diagram-2

Santa Rosa Platform Diagram

Santa Rosa Platform Crestline / ICH8M Chipset

Montevina Platform

 Montevina vs. Santa Rosa
Montevina vs. Santa Rosa

Intel Centrino technology family

Sonoma Diagram – M51A Sample
Alviso
(GMCH)
915GM
ICH6-M
• GMCH Core Frequency 333MHz
• 12.1” active matrix TFT,
• XGA 1024x768 resolution,
CPU
Dothan
•400/533 MHz FSB •DDR2 SDRAM 400/533 MHz
•DDR1 SDRAM 333 MHz
•Dual Channel support DDR2
•Single Channel support DDR1
Memory
DIMM
•1 x SODIMM socket
for expansion up to
768GB DDR2-400/533
DRAM support
•DMI Link ,100MHz
•On board 256M
DDR2 SDRAM
400 MHz design
•PCI BUS ,33MHz
Cardbus
R5C841
4 IN 1
Card
Reader
IEEE
1394
PCMCIA
type II
LAN Controller
RTL 8101L
RJ-45
MINI PCI
Slot
USB 2.0
X3 port
•USB 2.0
LCD Con.&
Inverter
CRT
•LVDS
•D-Sub 15 pin
•IDE BUS
•Ultra ATA 100/66
•2.5” 30/40/60/80 GB
•4200/5400RPM
•Combo drive
•Dual drive
•Super multi drive
•MMC
•SD
•MS
•MS-Pro
Audio CODEC
ALC861
Modem
Module
Headphone -out Jack
/ Int. SPK
Int. & Ext.
MIC
•Azalia Link
FWH
SST 49LF004A
•LPC BUS ,33MHz
KBC
M38857
Int.
KB & T/P
• Intel Pentium M Processor
• Speed at 1.6G~2.13GHz (Dothan)
• 2MB On-Die L2 Cache

Napa Diagram - W5F Sample
Calistoga
(GMCH)
945GM
ICH7-M
CPU
Yonah
•667 MHz FSB
•1 x SODIMM socket for
expansion up to 1GB
DDR2-533/667 DRAM
support
•DDR2 SDRAM 533/667 MHz
•Single or Dual Channel support
Memory
DIMM
•On board 512M
DDR2 SDRAM
533/667 MHz
design
• Intel Yonah dual core
• T2300/2400/2500/2600
• 1.66/ 1.83/ 2.0/ 2.16G Processor
• 2MB On-Die L2 Cache
Cardbus
R5C832
•PCI BUS 3.3V ,33MHz
LAN Controller
RTL 8101
Audio CODEC
ALC660
USB 2.0
X3
CMOS Module
1.3 mega pixels
Bluetooth
V2.0
LCD Con.&
Inverter
5 IN 1
Card
Reader
•USB 2.0
•IDE BUS ,Ultra ATA 100/66
IEEE
1394
RJ-45
•Azalia Link
MINI CARD
802.11 a/b/g
Intel 3945 ABG
NEW
CARD
•PCIE-E
•DMI Link ,100MHz (Direct Media Interface)
CRT
TV
•LVDS
• GMCH Core Frequency 400MHz
• 12.1” Wide active matrix TFT,
1280x768resolution,
• Support EDID
Int.
KB & T/P
KBC
M38857
TPM
1.2
•LPC BUS ,33MHz
FWH
SST 49LF004A
Int.
SPK
Int. & Ext.
MIC
SPDIF
or
Line out
•S-Video
•D-Sub 15 pin
Modem Module
•2.5” 60/80/100/120 GB
•4200/5400RPM
•Combo drive
•Super multi drive
•MMC
•SD
•MS
•MS-Pro
•XD

Santa Rosa Diagram – A8Se Sample

Montevina Diagram –N80V Sample

Intel Platform

AMD Platform

AMD Puma platform

Puma platform architecture

AMD Puma Diagram –N50Tr Sample

Q & A (Repair Experience)

Chapter 2
POWER Repair Guide

Overview
 Introduction
 Diagram
 Repair Flow Chart

Introduction
 Classification of the power circuit
 Linear & Switching Regulator
 Switching Buck Converter
 Voltage & Current Mode Control
 Multiple Output Controller
 Multi-Phase Operation

Power Classification Type
 ACDC: Rectification.
 DCDC: DC Converter.
 DCAC: Inverter.
 ACAC: AC Converter.
@ DC Converter  Linear & Switch
@ IC in Power circuit, generally call “Regulator”

Linear Regulator
• Linear Regulator
– Advantages
• Simple
• Low Cost
– Issues
• Power Dissipation
OUTPUTINPUT
REF
- +

Switching Regulator
• Switching Regulator
– Advantages
• Efficient
– Issues
• Noise
• Layout
The Basics of Switching Regulator

VCC
VIN
VCC
VIN
UGATE
PHASE
GNDFB
PWM
CONTROLLER
PWM
CONTROLLER
VOUT
UGATE
PHASE
LGATE
PGND
GND
FB
VOUT
Synchronous Buck Converter is More Efficient
STANDARD BUCK CONVERTER SYNCHRONOUS BUCK CONVERTER
Switching Buck Converter

• Current Mode Control
– Immediate Response
to Changes in Input
Voltage
– Inherent Current
Limiting
VOUT
VIN
PWM
LOGIC
VOLTAGE
CONTROL
CONTROL IC
PWM
LOGIC
VOLTAGE
CONTROL
CONTROL IC
CURRENT
CONTROL
VOUT
VIN
Voltage Mode vs. Current Mode Control
• Voltage Mode Control
– Single Control Loop
– No Current Sense
Resistor
– Better Noise
Immunity
– Less Sensitive to
Layout

Diagram
 Sonoma Power Plane Standard Diagram
(M5A,W3A/V,W1V,W2V,W5A,W6A,V6V,M7V,M9A/V…..etc.)
 Napa Power Plane Standard Diagram
(W5F,W6F,V6J,V1J,A6J…..etc.)
 Santa Rosa Power Plane Standard Diagram
(A8S,A8E,F3E…..etc.)
 Montevina Power Plane Standard Diagram
(F6V,N80Vc,N80Vr,M51Va,N20A…..etc.)
 Voltage Detail Distribution Sample - M9V
 Voltage Detail Distribution Sample - V6J

Diagram
 Sonoma Power Plane Standard Diagram
(M5A,W3A/V,W1V,W2V,W5A,W6A,V6V,M7V,M9A/V…..etc.)
 Napa Power Plane Standard Diagram
(W5F,W6F,V6J,V1J,A6J…..etc.)
 Voltage Detail Distribution Sample - M9V
 Voltage Detail Distribution Sample - V6J

Diagram-1 (Sonoma)
LTC 3728
(Regulator)
TPS 5130
(Regulator)
MAX 1987
(Regulator)
AC_BAT_SYS
+5VAO
+5VO
+3VO
Regulator +12VO +12V
+3Valways
+5V
+3V
Main Power IC
System Power IC
Vcore Power IC
Regulator +3VAO
+VCORE
+1.5VS
+2.5VS
+1.05VO
VREF5
+VCCP
+1.8VO +1.8V
+5Valways
+12VS
+5VS
+3VS
+1.8VS
+0.9VSRegulator
Regulator +1.5Valways
Regulator +1.2VSP
Regulator +ATI_VCORE

M9V Power Block Diagram

M9V System Power Plane

M9V DC/DC Module Spec.

M9V System ON Sequence
S.B
(ICH-6)
U62
PLT_RST#_3
N.B
(MCH-915PM)
U48
CPU Socket
U49
H_PWRGD
H_CPURST#
VRM_PWRGD
PWROK_ICH
Multi-
circuit
CLK_EN#
CLK Gen.
(ICS954213)
U16
CLK_MCH_BCLK/#
CLK_MCH_3GPLL/#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_ICHPCI
CLK_PCIE_ICH/# KBC
(M38857)
U12
2
1
3
5
4
4
4
6
7
8
+VCCP
+VCCP
VR_PWRGD
ATI
(M24-P)
U9
PCI_RST#_ICH ROICH
(R5C841)
U18
LAN
(RTL8101)
U1
Mini PCI
CN7

LTC 3728-Feature

LTC3728-Package

LTC 3728-Function Diagram

LTC 3728-Pin Function-1

LTC 3728-Pin Function-2

TPS 5130-Feature

TPS 5130-Pin Assignment

TPS 5130-Functional Diagram

TPS 5130-Pin Function-1

MAX 1987-Feature

MAX 1987-Pin Assignment

MAX 1987-Pin Description-1

Operating mode truth table

Output Voltage VID DAC Code (SUS=low)

Diagram-2 (Napa)
TPS 51020
MAX 8743
ISL 6227
NCP 5214
ISL 6262
+1.5VO
+5VO
+3VO
Regulator +12VSUS +12V
+5V
+3V
+VCORE
+1.8VO
+0.9VS
+VGA_VCORE_O
+VRAM_O
+1.05VO
+5VS
+3VS
Regulator
+VGA_VCORE
+VRAM
+5VSUS
+3.3VSUS
AC_BAT_SYS
+12VS
Regulator +3VAO +3VA
+1.5VS
+1.05VS
+0.9VO
+1.8V
+1.8VSRegulator
+1.2VSPO
+2.5VS+2.5VO
+1.2VSPMain Power IC
System Power IC
Vcore Power IC

Power Block Diagram-V6J

V6J System Power plane

V6J DC/DC module spec.

TPS 51020-Feature

TPS 51020-Package

TPS 51020-Function Diagram

ISL 6227-Feature

ISL 6227-Package

ISL 6227-Pin Description-1

NCP 5214-Feature

NCP 5214-Package

TPS 51020-Function Diagram

NCP 5214-Pin Description-1

NCP 5214-Pin Description-2

MAX 8743-Feature

MAX 8743-Pin Configuration

Repair Flow Chart(1)
Start
Visual Inspection A/D & BATT
Connector/Measure voltage
Finished
COMS Voltage between 3V~3.3V
X’tal CLK signal is correct 32.768kHz
Confirm the symptom problem is
Power to GND or No Power
No Power / Power On error
Check PWR_SW# &
PWR_BTN# circuit is OK
Measure AC_BAT_SYS signal
(AC mode : 19V,BATT mode 16.8V)
Check Always/
stand-by Voltage is OK ?
Measure & Check Control
Signal PM_SUSC# / PM_SUSB# /
PM_SUSA# /CPUVR_ON
Trace the circuit,
V.I Check & change
NG related Component
Trace and confirm the circuit to Check
1.PWR_SW# status Hi->Lo->Hi and
Lid_SW# signal must be always Hi
2.PWR_BTN# signal status Lo->Hi->Lo (to S.B)
(all status Hi or Lo will be by RD Design spec.)
Confirm the circuit,
Check All Always/ Stand-by Voltage
(ex. +3V/+5V always) (by RD design)
Measure COMS battery/
X’tal CLK for S.B is OK ?
1.PM_SUSC#
+3V , +5V +12V ………etc (by model request)
2.PM_SUSB#
+12Vs , +3Vs , +5Vs…..etc (by model request)
3.CPUVR_ON
Vcore , VRM_PWRGD , CLK_EN#
Change NG
Component
Change NG CMOS BATT
& X’tal Component
/trace related circuit
Trace related circuit,
Change Defect Component
Trace related component,
compare with the circuit
Change NG Component

Start
Confirm the TSICT program, Check
what kind voltage of ICT Power jump
(+3V or +3Vs / +5V or +5Vs ….)
Finish
Confirm the symptom problem is
Power to GND or No Power
Power GND
Confirm & check to separate which
power circuit cause AC_BAT_SYS to GND
Visual Inspection
All Component is OK ? Check component have short or burn
Power circuit can differentiate to 4 section :
(一)Main Power IC circuit
Check MOS-FET ,Capacitor ,Power IC
(二)BATT charge circuit
Check MOS-FET ,Capacitor ,Diode ,Charge IC
(三)CPU Vcore Power circuit
Check MOS-FET ,Capacitor ,Diode ,CPU power IC
(四)LCD Inverter Power supply circuit
Check Capacitor or Inductance
Confirm the problem AC_BAT_SYS Signal GNDICT jump Power Voltage GND
(一)Separate ICT power Jump solder, Use multi-Meter to
measure which side voltage to GND
(二)Confirm the circuit and use TSICT program to Find
out all the connection component
Check Item as follow:
(1)Check MOS-FET component (G-S gate is no short)
(2)Check Capacitor (V.I capacitor surface is no rift)
(3)Change voltage to GND of BGA component

Chapter 3
CHARGE Repair Guide

Overview
 Introduction
 Diagram
 Signal Description

Introduction
 Battery Pack:
-Battery cell
-Protection Board
Protection circuit
Gas Gauge IC : BQ2060H
BQ20Z90
-Outer Casing

Rechargeable Battery
 Li-Ion Battery
 NiMH Battery
 NiCad Battery
Li-Ion Ni-Cad Ni-MH
Energy Density (W-Hr/Kg) 90 40 60
Operating Voltage 3.6 1.2 1.2
Lifetime (approx. cycles) 1000 1000 800
Self Discharge 6%/month 15%/month 20%/month

Features of Li-Ion Battery
 Smaller
 Lighter
 Lower Self-Discharge Rate
 No Memory Effect
 Pollution-Free
 Overcharging or Overdischarging will Cause
Permanent Damage

Charging Characteristics (Li-Ion)
•CC(Constant current) & CV(Constant voltage)
C.C.
C.V.

Glossary #1
 Nominal Capacity:
- mAH
- AH
 Nominal voltage:
- Ni-MH : 1.2v/cell
- Li-Ion : 3.6v/cell (or 3.7v/cell)
ex: 400mAH = 0.4AH (1A= 103mA)

Glossary #2
 Series & Parallel:
Series Parallel
I V V

Glossary #3
 Over discharge
-for battery spec.
(ex:3.6v Li-Ion, over discharge: under 2.75v~2.5v /cell)
 Over charge
-for battery spec.
(ex:3.6v Li-Ion, 4.3v ~4.35v /cell)
 Self discharge
 Cycle life
-500~1000 (fullemptyfull)

Battery Label
Li-Ion
Ni-MH
Li-Polymer
Norman Voltage:14.8v
- 3.7 v/cell
- 4S :4 x 3.7 =14.8v
Battery Capacity
-4000mAH
-2P: 2 x 2000(mAH)
2000mAH/cell

Connecter(Old)
1 2 3 4 5 6
Pin Signal Description Type
1 GND Ground
2 TS Battery Type I
3 HDQ_BAT HDQ Bus I/O
4 BAT_EDV End of discharger I
5 NC No Connection
6 BAT_S Battery
input/output
voltage
PWR(I/O)

Connecter(New)

Battery Pack
Protection BoardGas Gauge Board
Battery
connecter

Gas Gauge IC –BQ20Z90H
Battery Parameter Record
Charge and discharge counting
Voltage
Temperature
Auto calibration
Battery Status register
Auto calibration
Wake function

Gas Gauge IC –BQ2050H
1 2 3 4 5 6
BQ2050H
HDQ
PIC16C54 HDQ Bus

Battery Learning
 Charge  Full Discharge NAC=0 (Discharge
complete) Charge Full

Charge Circuit Sample-F3H(Bq20Z90)

DCIN & LDO & REF

ACIN & ACOK
AC_APR_UC

MODE Select Setting

EC Circuit Sample-F3H)
EC
EC

Repair Flow Chart
Start
Visual Inspection
check Charge IC & EC & related component
are no damage
Measure Voltage & CLK
Finish
Check PIC IC signal ,
AC_APR_UC ->Hi (A/D in)
TS# ->Lo (BATT in) ,
CHG_EN ->Hi , CHG_LED ->Hi
Check charge IC signal ,
BAT_CHG_OUT
Check Charge IC Voltage,
Vcc Pin = A/D_VIN ->19V
Check EC IC Voltage & CLK,
+3VA_EC, 2.5VREF
CLK, 32.768MHz
Change NG X’tal & RLC
Component and fix any trace
open
Change defect Charge IC & EC & N.G Component
Fix any trace open & BAD solder problem
OK
NG
OK
NG
NG
OK
Trace the related circuit,
Change NG related Component/fix any trace open
Confirm circuit,
Change NG related component
fix any trace open
NG
Change ECat firstly
, and then Charge IC
OK
Check which Control signal
for device is wrong
Check C.C & C.V Setting

Chapter 4
CLOCK Repair Guide

Overview
 Diagram
 Repair Technique

Diagram-1
CLOCK
Generator
(1)
CPU
CLK_CPU_BCLK
CLK_CPU_BCLK#
MCH
(Hub/DMI)
(PCI-E)
(GMCH)
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_MCH66 (AGP/Hub-link)
CLK_MCH_3GPLL (PCI-E x16 /with DMI-link)
DREFCLK (for GMCH)
DREFCLK# (for GMCH)
CLK_MCH_3GPLL# (PCI-E x16/with DMI-link)
VGA
(AGP/PCI-E)
CLK_AGP66 (AGP)
CLK_PCIE_PEG# (PCI-E)
CLK_PCIE_PEG (PCI-E)
CLK_VGA27
ICH
(HUB)
(PCI-E)
CLK_ICHPCI
CLK_PCIE_ICH (PCIE x1)
CLK_PCIE_ICH# (PCIE x1)
CLK_USB48
CLK_ICH14
CLK_ICHHUB
CLK_REQ_MCH#

Diagram-2
CLOCK
Generator
(2)
X’tal
14.318MHz
FWH
KBC
CARDBUS
MINIPCI
CLK_CBPCI
CLK_MINIPCI
LAN
CLK_LANPCI
SIO
CLK_SIOPCI
CLK_SIO_14M
CLK_KBCPCI
CLK_FWHPCI
+3V_CLK
CLK_EN#
CPU_BSEL0~2
depends on CPU type
SMB_CLK
SMB_CLK
NEWCARD
MINICARD
CLK_PCIE_NEWCARD
CLK_PCIE_NEWCARD#
CLK_PCIE_MINICARD
CLK_PCIE_MINICARD#
CLK_REQ_NEWCARD#
CLK_REQ_MINICARD#

Generator Distribution-W5F Sample
Yonah-CPU
(Dual Core)
Calistoga
GMCH
(945GM)DREFCLK
DREFCLK#
ICH7-M
CLK_ICHPCI
CLK_PCIE_ICH
CLK_USB48
BCLK
133/166 MHz
FSB
533/667 MHz
CLK_CPU_BCLK
CLK_CPU_BCLK#
51
52
ICS 954310BGLFT
CLK_MCH_BCLK
CLK_MCH_BCLK#
43
44
38
39
CLK_REQ_MCH#
19
20
22
23
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
40
14
15
DREFCLK
99 MHz for graphics
MCH_3GPLL
100 MHz for PCIE/DMI
CLK_ICH14
ICHPCI
ICH7 PCI Bus 33 MHz
USB48
USB 48MHz
ICH14
ICH7 14 MHz
PCIE_ICH
S.B PCIE(x1) 100MHz
FWH
49LF004A
CLK_PCIE_MINICARD/MINICARD#
CLK_PCIE_NEWCARD/NEWCARD#
9
12
60
KBC M38857
CLK_CBPCI
CARDBUS R5C832
LAN
RTL 8101
CLK_LANPCI
CLK_KBCPCI
TPM
Device
CLK_TPMPCI
CLK_FWHPCI
5
8
3
64
4
CLK_PCIE_ICH#
CLK_REQ_MINICARD#
CLK_REQ_NEWCARD#
MINICARD
NEWCARD
CBPCICARDBUS 33 MHz
LANPCILAN 33 MHz
KBCPCIKBC 33 MHz
TPMPCITPM 33 MHz
FWHPCIFWH 33 MHz
X’tal
14.318MHz
+3VS_CLK
VTT_PWRGD#
10
1,7,11
21,28,42
45,50,56
57
58
1
2
2,6,13
29,37,46
53,59
16
BSEL1

Generator Distribution-W6A Sample
Dothan-CPU
Alviso
GMCH
(915GM)DREFCLK
DREFCLK#
ICH6-M
CLK_ICHPCI
CLK_PCIE_ICH
CLK_USB48
BCLK
100/133 MHz
F.S.B
400/533 MHz
CLK_CPU_BCLK
CLK_CPU_BCLK#
43
44
ICS 954213
CLK_MCH_BCLK
CLK_MCH_BCLK#
34
35
26
25
32
31
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
14
15
DREFCLK
99 MHz for graphics
MCH_3GPLL
100 MHz for PCIE/DMI
CLK_ICH14
ICHPCI ICH6-M PCI Bus
33 MHz
USB48 USB Controller
48MHz
ICH14 ICH6-M
14 MHz
PCIE_ICH ICH6-M PCIE(x1)
100MHz
9
11
53
KBC
M38857
CLK_CBPCI CARDBUS
R5C841
LAN
RTL 8100CL
CLK_LANPCI
CLK_KBCPCI
56
54
3
FWH
49LF004A
4
CLK_PCIE_ICH#
LANPCI
for LAN Controller 33 MHz
X’tal
14.318MHz
+3VS_CLK
VTT_PWRGD#
16
1,7,8,13
22,29,33
37,42,48
49
50
1
2
2,6,12,30
38,45,51
FSLC
FWHPCI
for BIOS CLK 33 MHz
KBCPCI
for Keyboard Controller 33 MHz
CLK_FWHPCI
CBPCICARDBUS 33 MHz
R219
680 ohm
MINIPCI
(WLAN)
CLK_MINIPCI
55 MINIPCI for WLAN Card 33 MHz

Frequency Programming

ICS954213 Datasheet (for Sonoma platform standard)

ICS954213-Block Diagram

Pin Description(1)

Pin Description(2)

ICS954310 Datasheet (for Napa platform standard)

ICS954310-Block Diagram

Pin Description(1)

Pin Description(2)

Pin Description(3)

Ordering Information

Repair Flow Chart
Start
Visual Inspection
check CLK Gen. and related component
are no damage
Measure CLK Gen. Voltage
Measure X’tal 14.318 MHz
Check which CLK signal
for device is wrong
Finish
Change Defect X’tal
or related Capacitor Component
Check CLK Gen. Voltage,
+3V_LAN
Measure & Check X’tal
14.318MHz
Change NG RLC Component
and fix any trace open
Change Defect CLK Gen.& N.G Component
Fix any trace open & BAD solder problem
OK
NG
OK
NG
NG
OK
Confirm circuit, Check related
trace & resistor, capacitor
Change NG RLC Component
/fix any trace open
OK
Measure CLK Gen. Controller Signals
Check CLK Gen. Controller Signals,
VTT_PWRGD#
Confirm circuit,
Change NG related component
fix any trace open
NG
NG
Change CLK Generator
OK

Repair Technique-Visual Inspection
Visual Inspection
To check Clock Generator and
X’tal and related components are
not damaged.
Fix any trace open & BAD solder
problem.
X’tal 14.318MHz CLK Gen.
1

Repair Technique-Measure Voltage
Use Multi-Meter or Oscilloscope to
measure :
Clock Gen. voltage (+3V_CLK) =3.3V is
ok.
+3V_CLK=3.3V
2

Repair Technique-Measure CLK X’TAL
Use Oscilloscope to measure :
X’TAL clock =14.318MHz is ok.
X’tal CLK=14.318MHz
3-1
3-2

Repair Technique-Measure Control Signal
measure Clock Gen. Control Signal
voltage (VTT_PWRGD#) =0V is ok.
Ps: (when press power bottom
the VTT_PWRGD# signal status is
from 3.3V0V)
VTT_PWRGD# 4-1
CPU Power IC
CLK Gen.
4-2

Repair Technique-Check Individual NG signal
Use Oscilloscope to measure every
individual CLK signal. If find error
please trace the circuit to find it’s
connection.
If related RLC components are ok but
CLK still is NG please try to change
CLK generator at last.
5

Chapter 5
HDMI Repair Guide

Overview
 Diagram
 Theorem

Interpret
 The HDMI architecture consists of at least one HDMI source and sink.
 HDMI is composed of four TMDS channels responsible for sending
out information from the HDMI transmitter to the HDMI receiver. The
three TMDS data channels are responsible for transmitting the video,
audio, and auxiliary data and the TMDS clock channel is responsible
for transmitting the video pixel clock data, used for data recovery on
the three TMDS data channels.
 The DDC channel provides the communication gateway to exchange
the status and E-EDID information between the HDMI source and the
HDMI sink.
 The optional CEC channel provides the high-level control functionality,
used for infrared remote control usage.
 Limitations include:
 The optional CEC channel is unsupported

Integrated and SDVO HDMI
 The digital display port on the GMCH supports two HDMI
options: Integrated and SDVO HDMI.
 Integrated HDMI uses the integrated HDMI transmitter on the
digital display port
 SDVO HDMI uses the integrated SDVO transmitter on the digital
display port, and then uses the third party HDMI transmitter on
either the motherboard or ADD2 card

Integrated HDMI Option
 For Integrated HDMI, the integrated HDMI transmitter receives both the
digital video and audio data which it synchronizes before it transmits the
data across a single cable connection to the HDMI receiver on the HDMI
sink.

SDVO HDMI Option
 For SDVO HDMI, the integrated SDVO transmitter receives the digital
video data and transmits the data to a third party HDMI transmitter on
either the motherboard or an ADD2 card. The third party HDMI
transmitter receives both the digital video and audio data which it
synchronizes before it transmits the data across a single cable connection
to the HDMI receiver on the HDMI sink.

Intel® Integrated Chipset Support
 Intel® 945GM Express Chipset Family Features Support
 Intel® G965 Express Chipset Family Features Support

Chapter 6
Touch Pad Repair Guide

Overview
 Diagram
 Theorem

Diagram
KBC
+3V
LPC
X’TAL
8MHZ
CLK
DATA
GND
+5V
33MHz
CLK_KBCPCI
SB

Circuit
CONNECT
KBC

M38857 Pin Define

M38857 Pin Describe 1

Repair Flow Chart
Start
Check Fun. setting
Measure Voltage & Clock
Finish
Trace circuit,
Change NG Component
and fix any trace open
Be sure the function is no disable in O.S
Check KBC Voltage & CLK,
+3V , CLK_KBCPCI = 33MHz
X’tal = 8MHz .
Check T/P Connector Voltage,
+5V
Change Defect Connector &
damaged RLC components
NG
OK
Check T/P signals,
INTCLK_Q3
INTDATA_Q3
Change NG related R.L Component
or fix trace open problem
OK
Change KBC Controller Chip
NG
NG
OK
OK
NG
Visual Inspection
Check Connector & RLC components
is OK
Use meter to measure
Signal’s bias voltage value is ok
Change South Bridge
OK
NG

Visual Inspection
1.check TOUCH PAD connector
is OK or not
2.R.L.C. components is not miss
or damage
CID CONNECTOR
1

Repair Technique-Function Setting
2-1
2-2
Function Setting
check TOUCH PAD Function is
no disable in OS.

Use multi-meter or Oscilloscope to
measure KBC Voltage.
+3V is ok.
Use multi-meter or Oscilloscope to
measure T/P Connector Voltage.
+5V is ok.
3-1
3-2

Repair Technique-Measure CLK
KCB X’tal =8MHz
Use Oscilloscope to measure KBC CLK.
CLK_KBCPCI = 33MHz,
X’tal = 8MHz,
4-1
4-2

Repair Technique-Measure T/P signals
If the problem is still existing, please
change Touch Pad Controller K/B Chip
Check T/P Signal
1. Use multi-meter to measure
INTCLK_Q3, INTDATA_Q3 are correct
2.if the value is high please check resistor
or Inductance and circuit of the trace is no
damage and no open.
test pointGND
5

PIN Signal name Diode value
1 +5VS_TP 591
2 +5VS_TP 591
3 INDTATA_5S 602
4 INTCLK_5S 602
5 GND 0
6 GND 0
Repair Technique-Diode Value of T/P Pin
PIN1,2,3,4,5,6 6

 If signal are all correct, please remember enable
function of internal pointing device in BIOS
 Due to connect with Touch Pad and Main-board by
FPC made sure non oxide of pin or non broken for
integer

Chapter 7
Keyboard Repair Guide

Overview
 Diagram
 Circuit

Diagram-1
Ex:
M38857M8
KEYBOARD
CONNECTOR
KSO0 ~KSO15
KSI0 ~ KSI7
KEYDETECT1
KEYDETECT2 +3VS
Keyboard
Controller
IC
LPC
Array
resistor
+3V
X’TAL
8MHZ 33MHz
CLK_KBCPCI
SB

Diagram-2
 Embedded Keyboard controller -Matrix
 PS : Maybe there is no Super IO in new NPI model, because there are no
PS/2 Port, COM Port or Print Port etc. on those model.

Diagram-2

Circuit-W6A

Repair Flow Chart
Start
Check Connector Pin & KB FPC
Check KBC power(+3V) &
CLK(8MHz/33MHz) is OK ?
Finish
or fix trace open
Check Connector Pin no short & open
/change new one KB to testing
Confirm the circuit, Check
array Resistor & trace is OK
Change Defect Connector &
damaged Resistor component
NG
Check NG signal connect to which
capacitor & resistor & Trace
or fix trace open problem
Change KBC Controller Chip
NG
NG
OK
OK
NG
Visual Inspection
Check Connector & Resistor component
no damage
Use meter to measure
Signal’s bias voltage value is ok
OK
OK

Visual Inspection
1.check K/B connector is OK and
Fix any trace open.
2.Array Resistor are no damage or
miss and Fix any trace open.
3.Check KBC and related
component are OK.
If V.I check is OK, and problem still
is exit.
Please change New one K/B to Test
at first.
1-1
1-2

Repair Technique-Measure K/B signals
Use multi-meter to measure K/B
connector Pin signal is normal of Diode
value.
If the problem is still existing
please change S.I.O (super I/O)
controller.
If the value is NG, please trace and
confirm the circuit to fix any trace or
array resistor problem.
4test
point
GND

Repair Technique-Diode Value of K/B Pin
W6A K/B
1
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
24
25
26

Repair Technique-Diode Value of K/B Pin
A3N K/B
28~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1
2930

Chapter 8
AUDIO Repair Guide

Overview
 Diagram
 Theorem

Diagram(1)
5-pin serial data transaction :
(1) BIT_CLK
(2) SYNC
(3) RESET
(4) SDATA_IN
(5) SDATA_OUT
Pin1,Pin9 :
+3VS_Code
Pin25,Pin38,Pin43 :
+5VS_AUDIO
Internal Speaker
External Speaker
For ASUS NB general form:
AC97:ALC650 , AD1885
Azalia:ALC660 , ALC861 , ALC880 , AD1986
AD1885
Pin2,Pin3 :
24.576MHz
AC97 Model
SB

Diagram(2)
5-pin serial data transaction :
(1) BIT_CLK
(2) SYNC
(3) RESET
(4) SDATA_IN
(5) SDATA_OUT
Pin1,Pin9 :
+3VS_Code
Pin25,Pin38 :
+5VS_AUDIO
Internal Speaker
External Speaker
For ASUS NB general form:
AC97:ALC650 , AD1885
Azalia:ALC660 , ALC861 , ALC880 , AD1986
ALC880
Azalia Model
SB

HD Audio Code Circuit-1 sample F50N

HD Audio Code Circuit-2 sample M51A
ALC663

HD Audio AMP Circuit-2 sample M51A

Signal Description
 Azalia Interface Code IC:
1.ALC269
2.ALC663

Pin Assignment-(HD-ALC269)

Signal Description-1(HD-ALC269)

Pin Assignment-(HD-ALC663)

Theorem
 HD link (Azalia link)

H/W Architecture
AC-Link bus is the pathway that codec communicate with controller.

HD link (Azalia link)
 Azalia is an enhanced replacement for AC’97
 Designed for a range of audio, modem, and communications
functionalities
 Targeted for PC’s and other devices like consumer electronics (CE)
 Improves on AC’97 design limitations
 Provides bandwidth for future audio and communication needs
 First Intel product intercept: ICH6
Azalia Enables High Quality Integrated Audio
Link
Codecs Controller
PCI Express
Azalia Bus Driver
Audio Modem
Filters Filters
Software

Intel® ICH6 Azalia and Legacy AC ’97
ICH6
Audio
Codec
Azalia Link
Dock Codec
Dock
Modem
Codec
• AC ’97 & Azalia controller use is mutually exclusive
• 1 Serial Data Out (SDO), 3 Serial Data In (SDI) pins:
support up to 3 codecs
• 8 Independent DMA operations
• 4 Input, 4 output streams
• 24 MHz BITCLK is driven by the Intel® ICH6
AC ’97
Legacy
AC Link
Codecs must ALL
be either AC ’97 or
Azalia
or
Azalia
Controller
PHY

Audio Bandwidth with Azalia
 With AC’97: Consumer with analog output
 Multi-channel Out: 6 channel, 20bit, 96kHz = 11.5Mb
 Total Out: ~11.5Mb (of about 11.5Mb available)
 Azalia designed to support multiple streams
 With Azalia: Consumer with analog output
 High Quality Audio Out: 8 channel, 24bit, 192kHz stream =
36.9Mb
 Modem Out: 1 channel, 16b, 48kHz = 0.77Mb
 Telephony Out: 2 channel, 16b, 48kHz = 1.54Mb
 Total Out: ~39Mb (of about 46Mb available)
 With Azalia: Laptop with integrated array microphone
 Array Mic Input: 8 channel, 16bit, 96kHz = 12.2Mb
 Independent Telephony Input: 2 channel, 16bit, 48kHz = 1.54Mb
 Total In: ~14Mb (of about 23Mb available)
Lots of Bandwidth to Support Current and Future Audio

Azalia improvement Over AC’97
AC’97 Azalia Benefit
 20-bit, 96 kHz multi-channel  32-bit, 192 kHz multi-channel  More accurate, better quality sound
 11.5 Mb/s max bandwidth  48 Mb/s per SDO, 24 Mb/s per
SDI
 Bandwidth for more channels and mic
array inputs at higher sample rates
 Fix bandwidth assignment,
fix slot base protocol
 Dynamic bandwidth assignment  Bandwidth delivered where it’s needed
 Pre-defined DMA useage  General purpose DMA’s  Support for multi-streaming / multiple
similar device types can be supported
 Single stream support (in &
out)
 Support for multiple streams (in &
out)
 Support for new Digital Home / Digital
Office useage models
 Clock provided by primary
codec
 Clock provided by the Intel® ICH  Single, high-quality, stable clock source
for synchronization
 Stability depending on SW
provider (IHV’s drivers)
 Unique Microsoft bus driver  Single bus driver for more OS stability
& base functionality
 Limited device sensing /
jack retasking
 Full device sensing / jack
retasking
 Support for full audio PnP
 2-element (stereo) array
mic support
 16-element array mic support  More accurate, better quality voice
input & recognition
Azalia Improves on Current AC’97 Spec

Repair Flow Chart
Check BIOS setting
Check Audio Voltage
Measure other Audio signals
Check Audio Clock
Start
Change damaged component
/ fix any trace open
Visual Inspection
check Int.&Ext. SPK Con. and damage
RLC & AMP. component
Change Audio Code chip
Change S.B
Finished
Use multi-meter to compare other
Audio signal with Good M/B
Change any NG component
related to NG signals
Measure Audio Code CLK:
24.576MHz (only AC’97 model)
related to X’tal.
Check Setting in the BIOS,
The Audio Function must be is UNLOCK
Measure Audio Code Voltage:
+3VS_Code and +5VS_Audio
Measure Audio AMP. Voltage:
+5VAMP
Fix or change any R.C.L.Q
component related to Voltage
Check Audio Control signal
Measure Audio AMP. SE/BTL# :
H: for Int. SPK ; L: for Ext. SPK
related to NG signals
NG
OK
NG
NG
OK
NG
OK
OK
NG
NG
NG
OK
OK
OK

Visual Inspection
1.check External/Internal audio
connector is OK
2.Related R.L.C/AMP ..etc
components is not miss or damage
3.AC’97/Azalia Code & nearby
component is no damage or burn1-1
NG OK
Connector
Broken
External Speaker Connector
Internal Speaker Connector
1-2
CID Case
CID Case

Repair Technique-Check BIOS Setting
Check Setting in BIOS
1.Firstly ,load BIOS default setting
2.Please check Audio/Modem
Interface function is not Locked
status.
2

Repair Technique-Measure Audio Voltage(1)
Measure AC’97 Code Voltage :
Pin 1/9: +3VS_Code
Pin 25/38/43: +5VS_Audio
Pin 4/7:GND ( Digital )
Pin 26/40/44:GND ( Analog )
+3VS_Code +5VS_Audio
3

Repair Technique-Measure Audio Voltage(2)
Measure Azalia Code Voltage :
Pin 1/9 : +3VS_Code
Pin 25/38 : +5VS_Audio
Pin 4/7 : GND ( Digital )
Pin 26/42 : GND ( Analog )
+3VS_Code +5VS_Audio
4

Repair Technique-Measure AMP Voltage
Measure Audio AMP Voltage :
Pin 7/18 : +5VAMP
5

Repair Technique-Measure Audio CLK
Only for AC’97:
Measure AC’97 Code CLK :
Pin 2/3 : 24.576MHz
24,576MHZ
6

Repair Technique-Measure Audio Signal
Use Multi-Meter to measure other
Audio signals’ bias voltage value.
(This method should be compared
with good MB)
If the symptom is still existing
please try to change Audio chip.
After change Audio chip the
problem is still constant please try
to change SB at last.
P.S.
AC97 Audio chip through AC97
link connect to SB.
HA Audio chip through Azalia link
connect to SB.
7

Chapter 9
MODEM Repair Guide

Overview
 Diagram
 Circuit

Diagram
Azalia BUS
RESET# & SYNC
BIT_CLKTIP & RING
RJ-11
Modem Board
Modem Board
CON. SB

Repair Flow Chart
Start
Visual Inspection
Check Modem Board is OK ?
Check Modem CON. VCC(+3V)
And RJ-11 CON. Signal is OK ?
Finish
/Repair open trace
Check Modem Type (by model)
/Change New one Modem Board
1.Check Power source to Modem
CON. Resistor and Trace
2.Check RJ-11 TIP / RING signal
& Re-solder
OK
NG
OK
NG
NG
OKUse multi meter to measure1.BIT_CLK
& SYNC 2.SDATA_IN/OUT 3.RESET#
Change audio Codec or
audio controller (S.B)
OK
Check1.RJ-11 CON.
2.Modem CON. (on the M/B)
3.Connection RLC component
Check AUDIO Link BUS Signal is OK ?
(AC97/Azalia)
Verify Software and Ass’y problem
OK
NG
Check Driver and Re-Ass’y
and MDM cable
NG

Visual Inspection
1.check RJ-11 connector is no
Damage or Pin bend or Pin bad
solder.
2.check Modem connector is no
Damage or Pin bend or Pin bad
solder.
3.R.L.C. components is not miss
or damage
4.Check PCB trace is no open or
scratch
1-1
1-2
CID
CID
RJ-11
Modem Connector (M/B)

Repair Technique-Software Skill
Software Skill
1.check Hardware Device is OK or not.
2.Check Device is working and
software driver is correct.
3.Check Device Setting up is correct
2-2
2-1

Repair Technique-Assemble Problem
Assemble Problem
Check Assemble MDM Board
connector to M/B connector is
close ,and Cable is no scratch or
damage
If problem still exist,
1.Please Check Modem Board is correct for
testing model,
2.change new one to test.
3-1
3-2

Repair Technique-Measure Modem Signals
Use multi-meter to measure Modem
signal is normal of Diode value.4
If the value is NG,
Please check Audio codec and Audio
Controller release circuit.

Modem Board CON.
Signal Name Diode Value
BIT_CLK 391
SYNC 426
RESET# 391
SDATA_IN 391
SDATA_OUT 391
RJ-11
TIP OL
RING OL
Repair Technique-Diode Value

Chapter 10
USB Repair Guide

Overview
 Diagram
 Theorem

Signal Description
Pin Define Signal Description
1 VSUS Power signal
2 D- Data signal
3 D+ Data signal
4 GND Ground signal

Repair Flow Chart
Start
1.Visual Inspection
2.Check Connector & Pins is OK ?
Check USB Vcc(5V)
is OK ?
Use multi-meter to measure
Check USB- & USB+ Signal is OK ?
Check USB 48MHz is OK ?
Finish
Check Fuse or Inductor and Trace
Check Resistor or Inductor and
Capacitor and Trace and S.B
& Re-solder
OK
NG
OK
NG
NG
OK
Check Resistor and CLK Gen.
and Trace
OK
Change S.B
NG

•Check USB connector is ok or not
•Check FERRITE BEAD is open or broken
1-2
1-1
USB
Connector
Broken

Repair Technique-Measure Voltage & GND
•Check GND
•Check +5V_USB
2-1
2-2

Repair Technique-Measure USB Signals
•Check USBP+
3-1
•Check USBP-
3-2

Signal Name Diode Value Between
1 +5V_USB 701 +/- 5
2 USBP- 604
+/- 5
3 USBP+ 605 +/- 5
4 GND 0
Pin 1,2,3,4
4
Repair Technique-Diode Value of USB Pin

Chapter 11
PCMCIA Repair Guide

Overview
 Diagram
 Theorem

Diagram
+3V
Power Controller
(R5531V002)
+3V +5V
VCC
VPP
X’TAL
24.576MHZ
CFRAME#
CAD[0:31]
CRESET#
CCLK#
VCC3_EN
VCC5_EN
CLK_CBPCI
(33MHZ)
PCI BUS
SB

Slot Pinout (F3H)

CardBus Power Circuit (F3H)

Chapter 12
IEEE 1394 Repair Guide

Overview
 Diagram
 Theorem

Diagram
R5C841
PCI Clock:33MHz
1394 Connector
EEPROM
+3V
SMBus
+3V
X’tal : 24.576Mhz
SB

Circuit
R5C841

Pin Define
R5C841

1394a Connector
6 Pin
4 Pin

1394b Connector
9 Pin

EEPROM Pinout
AT24C02N

Repair Flow Chart-(1)
Start
Visual Inspection
Check 1394 Connector/Related Component
no damage
Check 1394 ID is OK ?
Measure 1394 Voltage
Use multi-meter to
measure 1394 signals
Finish
Check 1394 CLK
24.576/33MHz
NGOK
OK
Change IEEE 1394 Controller Chip
NG
NG
OK
OK
NG
Re-write 1394 ID Address
PASS
Change NG
Component
Change NG X’tal
/CLK Gen. Component Measure 1394 Clock
Check 1394 +3V Voltage,
Change NG Component
/Fix any trace open
Check 1394 Signals
TPA0+/TPA0- , TPB0+/TPB0-
Change NG Component
/Fix any trace open
Next Page
Fail
1394 ID Error Can Write 1394 ID ?
Check BIOS setting
Check 1394 setting is unlock
in the BIOS.
OK

Check EEPROM Voltage
EEPROM signal
Finished
NG
OK
Change NG Component/
Fix any trace open
Change EEPROM Chip
1394 ID Address Error
NG
OK
OK
NG
Visual Inspection
check EEPROM/Connector/connection
components is no damage
Re-write 1394 ID and
check ID number is available ?
Check EEPORM Voltage,
+3V
Fix any trace open
Check EEPORM Signals,
1394_SCL,1394_SDA
Fix any trace open

CID
CID
Visual Inspection to check 1394
connector, controller & related
component is not damaged.
1-2
1-1

Repair Technique-Check Bios setting
Check 1394 setting is Unlock
in the Bios.
2

Measure IEEE 1394 controller voltages:
(RICOH R5C841)
Pin : +3V
3

Repair Technique-Measure 1394 Clock
Use Oscilloscope to check
1:1394 X’TAL 24.576Mhz
2:33.3Mhz (PCI_CLK) are ok.
4

Repair Technique-Measure 1394 Signals
Use Multi-Meter to measure 1394
signals bias voltage value.
TPA0+/TPA0- ,TPB0+/TPB0- (Fig.
5-2).
If still cannot find any abnormal
please try to change 1394 controller
and check other device under PCI
bus.
If the problem is still existing after
change 1394 controller, please
change SB at last.
TPB0+
TPB0-
TPA0+
TPA0-
GND
Test Pin
5-1
5-2

Repair Technique-Diode Value 1394 Pin
TPB0+
TPB0-
TPA0+
TPA0-
6

Repair Technique-Diode Value EEPROM
7
1394_SCL
1394_SDA

Chapter 13
Card Reader Repair Guide

Overview
 Diagram

Diagram
PCI BUS
+VCCA
SDCLK/MSCLK
CD
CMD
CE#
DA0~DA3
+3V
X’TAL
24.576MHZ
CLK_CBPCI
(33MHZ)
CD  Card Detect
CMD  Command
WE#  Write Enable
CE#  Card Enable
CLK  Clock
PC  Power Control
WP  Write Protect
DA0~3  Data 0~3
SB

Circuit-1

Circuit-2

Repair Flow Chart
Start
Finish
& Re-solder
Change Card reader
Controller Chip
Confirm the problem Is
MMC/SD error or MS/MS-pro error
Check MSCLK/SDCLK is OK ?
Measure clock,
Check related Resister 0 ohm
Check Voltage is OK ?
1.Visual Inspection
Measure Voltage, VCCA = +3V is OK
(Control signal MCVCC3EN# is
Low active)
Check Resister and
Capacitor and MOS-FET
Check DATA0~ DATA3(CD) & CMD
signal is OK ?
Change Defect
Component
Change Defect
Component
Change Defect
Component

Visual Inspection:
1.check Card Reader connector is
no damaged and bend.
1Pin
bend
Check MSCLK & SDCLK:
1.Use multi-meter to measure MSCLK
& SDCLK Pin(24) is correct
2
GND

Repair Technique-Check VCC & CMD
3
Check VCC(3V)
1.Use multi-meter to measure VCCA
Pin(14,19,26)is correct
GND
4
Check CMD
1.Use multi-meter to measure CMD
Pin(23)is correct
GND

Repair Technique-DATA0~3
5 Check DATA 0~3
1.If memory type is disordered or data transfer
fail please Use multi-meter to measure
DATA0~ 3
Pin13 -> DATA0
Pin11 -> DATA1
Pin27 -> DATA2
Pin25 -> DATA3
GND
GND

Repair Technique-Diode Value of Card Reader Pin
PIN
Signal
Name
Diode
Value
1 GND 0
2 GND 0
3 GND 0
4 GND 0
5 GND 0
6 SD_WP OL
7 NC OL
8 NC OL
9 FUNCSEL0 497
10 GND 0
11 SDDATA1 497
12 SMCD3 503
13 SDDATA0 497
14 VCCA 596
15 GND 0
16 SMCD2 503
PIN
Signal
Name
Diode
Value
17 SDCLK/MSCLK 492
18 SMCD1 503
19 VCCA 596
20 MSCD# 598
21 GND 0
22 SMCD0 503
23 SDCMD 496
24 SDCLK/MSCLK 492
25 SDDATA3 498
26 VCCA 596
27 SDDATA2 498
28 GND 0
1
6
78
9 28
2
3
4
5

Chapter 14
SATA Repair Guide

Overview
 Diagram
 Theorem

Diagram
SATA BUS
CLK_SATA_ICH
Clock GEN
SATA HDD SB

Circuit
South Bridge
SATA HDD

Repair Flow Chart
Start
Finish
Check BIOS set up and
Update latest BIOS version
& Re-solder
OK
NG
NG
OK
OK
Check SATA pin Diode is OK ? Change Defect Component
OK
NG
Visual Inspection/
Check Connector & Pins is OK ?
Load BIOS set up default/
update bios to latest version
Check CLK_SATA_ICH is ok?
Check SATA VCC is OK ? Check Power+5VS & +3VScircuit Change Defect Component
OK
NG

Chapter 15
ODD Repair Guide

Overview
 Diagram
 Theorem

Diagram
IDE BUS
S.B
ODD Connector
ODD Device
M/B
SATA BUS
CLK_SATA_ICH
Clock GEN
SB

Repair Flow Chart
Visual Inspection to check
Connector is no damaged,
Soldering is ok.
Load set up default
in the bios/ update bios
to latest version
ODD signal’s diode value, compare
with good MB.
Start
Measure ODD Voltage
Change NG connector,
re-solder NG soldering point,
Change new CD/DVD-ROM FPC
Load setup default and
update to latest bios.
Check ODD Vcc Voltage :
Vcc=+5V
Check CLK_SATA_ICH is ok?
Change S.B
Finished
OK
OK
OK
OK
NG
NG
NG
Change NG component
NG

Chapter 16
LAN Repair Guide

Overview
 Diagram
 Theorem

PCI_BUS
EEPROM
+3V_LAN
SMBus
Diagram
LAN
Controller
IC
+3V_LAN
PCI_Reset
#
+2.5V_LAN
Clock :
1.25MHz
2.CLK_LANPCI
Transformer
10/100MB
RTL 8100CL
SB

Signal Description

Theorem-EEPROM Pinout
93C46

What is MAC Address?
 Each device connected to a standard LAN needs a Data Link Layer
address (or called hardware address), providing a means of unique
identification.
 Each NIC has its unique, hard-coded MAC (Media Access Control)
address. It is a 48 bits (6 bytes) address written in a hexadecimal format.
The first 3 bytes represents for vendor ID and the remaining 3 bytes
are serial number.
MAC: 000C6E 7D3D0F
Vender ID Serial Number

START
Visual Inspection
Check LAN Connector and
Component is OK ?
Measure LAN Clock & RST#
Finished
Change NG X’tal/Clock Gen.
Re-write LAN ID Address
/Load BIOS default
Check Lan Voltage,
+3V_LAN,+2.5V_LAN…
Change Defect
Connector/Component
Fail
NG
OK
OK
Use multi-meter,
to measure signal is 150 ohm ?
LAN_RDP/RDN & LAN_TDP/TDN
Change NG Transformer
/Related R.C Component
Fix any trace open
OK
Change LAN Controller Chip
Next Page
LAN ID Error
Can Write LAN ID ?
NG
NG
OK
OK
Measure LAN Voltage
Check LAN MAC ID address/
BIOS setting up
Change Defect connection R,L,C
or Transistor Components.
Check Lan X’tal 25MHz,
CLK_LanPCI 33MHz ,PCI_RST#
Measure LAN Transformer
Fix any trace open/
Check NG device on PCI_Bus
Measure LAN AD signals Use multi-meter to measure
PCI_Bus AD signals AD0~AD31
Change S.B
OK
OK
OK
NG
NG
NG

Check EEPROM VCC(+3V) is OK ?
SEEDI/SEECLK/SEECS signal
Finish
Check Power to EEPROM VCC pin
Connection or Trace is OK .
NG
OK
Check EEPROM to LAN Controller
Trace is open?
Fix any trace open
Change EEPROM Chip
LAN ID Error
NG
OK
OK
NG
Visual Inspection the EEPROM and
related components is OK ?
Re-write LAN ID and
check ID number is available ?
Repair Defect open Trace

Visual Inspection to check
1.LAN(RJ-45) Connector/Pin is OK.
2.Related components is no miss and
damage or burned
CID
CID
1-1
1-2

Check LAN port setting is
UNLOCKED mode in the BIOS.
2

Repair Technique-LAN ID Check
Check LAN MAC ID address is correct/available
(Not 000000 000000)
If LAN MAC ID fail,
Please Re-write LAN MAC address first.
If the problem still exist,
check Voltage is OK and then use multi-meter to measure diode
value of EEPROM
3
LAN MAC ID

Repair Technique-Measure Voltage & CLK
Measure LAN controller voltages & CLK:
1: +3V_LAN
2: +2.5V_LAN
3: 25MHz
4: PCI_Reset#
5: CLK_LANPCI (33MHz)
4-1
LAN
Controller
IC
+3V_LAN PCI_Reset#
+2.5V_LAN
Clock :
25MHz
&
CLK_LANPCI
Measure EEPROM voltages:
Pin 8: +3V_LAN
Pin 5: GND
4-2
93C46
+3V_LAN

Repair Technique-Measure Transformer Signals(1)
Use Multi-Meter to measure
Transformer signals.
Some signals should be connected
together (Show as Fig.5-2, the signals
marked Green color)
If Transformer NG, please change it .
LAN_TX+
LAN_TX-
LAN_RX+
LAN_RX-
TDP
TDN
RDP
RDN
5-1
5-2

Repair Technique-Measure Transformer Signals(2)
Use Multi-Meter to measure
Transformer signals. TX’ signals and
RX’ signals should be 150 diode value
(Show as Fig.6-2, the signals marked
black color)
If NG , Please confirm related Resistor
(75 ohm) component.
LAN_TX+
LAN_TX-
LAN_RX+
LAN_RX-
TDP
TDN
RDP
RDN
6-1
6-2

Repair Technique-Diode Value EEPROM
93C46

Chapter 17
VGA Repair Guide

Overview
 Diagram

Diagram
RED
GREEN
BLUE
PIN1
PIN2
PIN3
DDCDA
HSYNC
VSYNC
DDCCL
PIN12
PIN13
PIN14
PIN15
+12VS
+3VS
NB

Signal Description
1 ~ 5
6 10
11 ~ 15

Start
Finish
& Re-solder
OK
NG
Change North Bridge or Graphics Chip
CRT No display/Other problemCRT Color error
Clear CMOS/ Bios check
Clear CMOS and Load
Default or Update new Bios
Check Voltage is OK ?
1.Visual Inspection
Confirm the problem Is color
error or No display
Check MOS +12VS is OK
Check HSYNC/VSYNC(+3.3V) is OK
Check DDCDA(+3.3V)/DDCL(+5V) is OK
(plug in CRT Connector)
Check Resister and
Next Page
Check HSYNC/VSYNC/DDCDA/DDCCL
signal is OK ?
Change Defect
Component
NG
OK
NG
OK
OK
NG
Change Defect
Component

Start
Finish
OK
NG
Change North Bridge/VGA
CRT Color error
Check Diode of +3VS
is OK
Check diode Voltage is OK ?
1.Visual Inspection
Confirm the problem Is color
error or No display
Check R/G/B signal is OK ?
Change Defect Diode and
RLC Component
NG
OK

Visual Inspection:
1.check VGA connector is no
damaged and bend.
2.Be sure VGA connector Pin
Solder no open or short.
CID-
Connector bend
CID
1-1
1-2

Repair Technique-Clear CMOS / Check Bios
2 If CRT is no display, please clear
CMOS and load Bios default at first.
And then,
If problem still exist, please try to
change Bios or update Bios.

Repair Technique-Measure VGA signals
Check the problem belongs to
(i) RGB color error problem
(ii) No display or display error problem.
(i) RGB color error problem please use multi-meter
to measure which color (R.G.B.) signal is error.
Trace the connection to confirm related inductor
or capacitor is ok. If it’s not caused by R.L.C.Q.
small components please change NB or
Graphics Chip.
(ii) No display or display error (not included color
error). Use the meter to measure Diode value on
DDCCL &DDCDA, VSYNC & HSYNC. Trace
the connection to confirm related R.C.L.Q. is ok.
If all check items are no problem please change
NB or Graphics Chip
GND
test point
Pin 5,10,14,3,8,12,1,6
Pin 15,4,9,13,2,7,11
3-1
3-2

Pin 5,10,14,3,8,12,1,6
Pin 15,4,9,13,2,7,11
Repair Technique-Diode Value of VGA Pin
4
Pin Name Diode Value Pin Name Diode Value

Chapter 18
LCD Repair Guide

Overview
 Diagram
 Theorem

Diagram-1
System Board Side LCD Module Side
GMCH
Display panel
LVDS
LVDS Bus
Inverter Board
FFC
LVDS
Connector
Inverter board
Connector
Cable
AC_BAT_SYS
+3Vs
LCD_BACK_ADJ
LCD_ENBACK
LID_RSM#
LID
Switch
ADJ_BL
KBC
BACK_OFF#
LCD_ENVDD
SB

Diagram-2
LCD Module Side
Display panel
Inverter Board
FFC
Cable
System Board Side
AGP Bus/
PCI-Express
MCH
ATI VGA
LVDS
LVDS Bus
LVDS
Connector
Inverter board
Connector
LID
Switch
+3Vs
LCD_ENVDD
LCD_ENBACK
KBC AC_BAT_SYS
LID_RSM#
BACK_OFF#
ADJ_BL
SB

Circuit-1
GMCH

Circuit-2
LVDS
Connector

Circuit-3
Inverter board
Connector

Signal Define-1

Signal Define-2

Signal Define-3

LVDS Basic-1
 LVDS is short for "Low Voltage Differential Signaling" and is a
high speed, low power data transmission standard.
 LVDS is standardized in the ANSI/TIA/EIA-644-1995 Electrical
characteristics standard titled: "Electrical Characteristics of Low
Voltage Differential Signaling (LVDS) Interface Circuits“
 The LVDS standard is an electrical standard only defining driver
output characteristics and receiver input characteristics.
Guideline are also given on bus configuration, cables, and
termination. Protocol, connectors, and bus structure is not defined
in this standard, as they are application dependant. It is intended
that these parameters are specified by the referencing standard.

LVDS Basic-2
 LVDS is envisioned to be forward looking and does not define a
maximum data rate within the standard. As maximum data rate is
design, technology, and application dependant (required signal
quality). Current LVDS parts operate from DC to Giga bits per
second range.
 Power dissipation is minimized in a number of ways. This
includes the CMOS process, the current mode driver design, and
also the small load current.
 Noise generation is minimized in a number of ways. The signal
swing is only 300mV, and also a true balanced differential data
transmission scheme, and the current mode driver all limit noise
generation.

LCD (Liquid Crystal Display)
 TN(90º)
-Twisted Nematic
 STN(240 º~270 º)
-Super TN
 DSTN
-Dual Scan Tortuosity Nomograph
 TFT (90º↑)
-Thin Film Transistor (FET)
 LTPS
-Low Temperature Poly-Si TFT LCD
Early
G
S
D
LCD Types

TFT-LCD
 TFT-LCD
-Thin Film Transistor LCD
Column Driver
RowDriver
Cs
Cs
Cs
Cs
FET

TFT-LCD
 One Pixel & Sub-pixel:
One pixel
Column Driver
RowDriver
Sub-pixel

Bright & Dark Pixel #1
One control circuit
to control 3 Gates

 Bright point(dot):
-Red / Blue / Green / White / Others
Bad
Red
Bad
Green
Bad
Blue
Bad
White
short

 Dark point(dot)
Bad (open)
Dark(Black)

Resolution

Start
Visual Inspection
Check connector and related component
are no damage
Separate the symptom problem
LCD display too Dark
Finish
LCD No display/turn to white LCD display abnormal
1 2 3
Check / Clear
CMOS BIOS setting &Fn
key problem
1.Clear CMOS and Load Default
2.Check Fn + F5 or F6….etc.
(depend on model request)
OK
Change damaged Connector &
any N.G RLC components
NG
NG
OK

LCD display too Dark
Finish
Start1
Measure
Inverter Con. Voltage
Measure
Inverter Connector Control
signal
Change North Bridge
or Graphics Chip
Check AC_BAT_SYS signal= is 19V.
1.Check “BACK_OFF#” ,
Voltage = 3V (from S.B)
2.Check “LCD_ENBACK” ,
Voltage = 3V (from N.B or Graphic)
3.Check “LID_RSM#” ,
Voltage = 3V
4.Check KBC “ADJ_BL” ,
Voltage = between 0~3V (from KBC)
(depend on model different)
Change any NG related
L&C Component
Trace the related circuit,
RLC Component and
control IC
NG
NG
OK
OK

Finish
LCD No display/turn to white
Start2
Measure
LVDS Con. Voltage
Check LVDS connector Voltage,
+3Vs
R&C Component
Measure
LVDS Voltage
LCD_VCC
Check LVDS Voltage LCD_VCC,
LCD_VCC =+3V
And check control signal voltage,
LCD_ENVDD = +3V
(signal from NB or Graphic IC)
Trace LCD_VCC signal’s
related circuit,
Change NG RLC and MOS-
IC Component
Change North Bridge
or Graphics Chip
NG
NG
OK
OK

Finish
LCD display abnormal
Start3
Measure Voltage
Measure Clock
Change North Bridge
or Graphics Chip
Check LVDS Voltage ( GMCH / Gfx ),
+2.5V
Check VGA Core Voltage ( GMCH / Gfx ),
+1.5V or +1.05V / ATi_Vcore 1.0~1.2V
(depend on RD design request)
R&C Component
Change any NG RLC
Component or CLK Gen./
Fix any trace open
AGP / PCI-E:
Check LVDS Clock for GMCH,
1.DREFCLK(#) 48MHz
2.DREFCLK(#) 96MHz
Check LVDS Clock for Gfx,
1.CLK_MCH66/AGP66 66MHz
2.CLK_PCIE_PEG(#) 100MHz
Use multi-meter
to measure LVDS signal
is OK ?
Check LVDS Data,
LADATAP[0:2] & LADATAN[0:2]
Check LVDS Clock,
LACLKP & LACLKN
Change NG GMCH or
Gfx IC/ Fix any trace open
OK
OK
OK
NG
NG
NG

Visual Inspection
1.check Inverter/LVDS connector is
no NG or BAD solder
2.R.L.C. components & Trace is no
damage or miss or openInverter Connector
LVDS Connector
CID
1-1
1-2

Check BIOS Setting:
1.Check display mode is OK,
not only CRT mode
2.Load BIOS default setting
and test again
2-2
2-1

Repair Technique-Check Fn Key
Check Fn Key Setting:
1.Fn + F5 is brightness Down
2.Fn + F6 is brightness Up
3.Fn + F7 is LCD Back Light On/Off
4.Fn + F8 is LCD/CRT/TV Mode switching
(all function key is depend on designer)
+
+
3-1
3-2

Repair Technique-Measure Voltage(1)
measure Voltage:
1.If problem is LCD too Dark,
Check AC_BAT_SYS (on Inverter
Con.) signal = 19V
2.If problem is LCD No display or turn
white
Check LCD_VCC (LVDS Con.) signal
= 3.3V
4-1
4-2

Repair Technique-Measure Voltage(2)
measure Voltage:
3.If problem is LCD display abnormal,
一.Check LVDS voltage = 2.5V
二.Check VGA Core voltage =
GMCH: 1.5V or 1.05V
Gfx: ATi_Vcore 1.0 ~ 1.2V
5

Repair Technique-Measure Control Signal
measure Control Signal voltage:
1.If problem is LCD too Dark
Check BACK_OFF#
= 3.3V
Check LCD_ENBACK
=3.3V
Check LID_RSM#
=3.3V
Check ADJ_BL
=0~3V
2.If problem is LCD No display or
turn white
Check LCD_ENVDD
=3.3V
6

Repair Technique-Measure CLK
Use Oscilloscope to measure Clock:
GMCH platform:
DREFCLK(#) = 48MHz (AGP Bus)
DREFCLK(#) = 96MHz (PCI-E Bus)
Gfx platform:
CLK_MCH66/AGP66 = 66MHz
(AGP Bus)
CLK_PCIE_PEG(#) = 100 MHz
(PCI-E Bus)
96MHz
7-1
7-2

Repair Technique-Measure LCDS signals
Use multi-meter to measure LVDS Con.
Pin signal is correct of Diode value and
compare with GOOD M/B.
Check LCDS Data signals,
LADATAP[0:2]
LADATAN[0:2]
Check LCDS Clock signals,
LACLKP / LACLKN
8

Repair Technique-Diode of LVDS Signal
LVDS Connector Signal
LADATAP[0:2]
L1_TX0+ 443
L1_TX1+ 442
L1_TX2+ 443
LADATAN[0:2]
L1_TX0- 443
L1_TX1- 442
L1_TX2- 443
LACLKP L1_TXC+ 441
LACLKN L1_TXC- 441
Ps (short for) :
LADATAP[0:2] / LADATAN[0:2]
L: LVDS
A: LVDS channel A Data output
P: positive
N: negative

Chapter 19
BIOS Repair Guide

Overview
 Diagram
 Introduction

BIOS LPC Bus
Clock
PCIRST#
+3VS
SIO
Diagram
INIT#
Clock Gen.
LFRAME#
DIS_SYSBIOS#
LAD[0~3]
SB

Signal Description-(1)

Introduction
 Memory Map
 SST 49XXX series Block Diagram
 Theorem

49xxx - Block Diagram

49xxx – Pin/Signal Names-1

49xxx – Pin/Signal Names-2

49xxx – Reset-1
FWH Mode

49xxx – Reset-2
PP Mode

49xxx – Chip Read

49xxx – Chip Write

49xxx – Block Erase

49xxx – Chip Erase

Product Ordering Information

Repair Flow Chart
Start
Finish
1.Change Defect Component &Re-solder
2.Update Bios image file
1.Visual Inspection
2.Use external Bios Boot up
Measure LPC LAD[0~3] signal diode
value is OK
Check Power signal VDD(+3VS)
Confirm circuit of Power IC,
Check connection RLC/diode
Components
Check CLK signal CLK(33MHZ) 1.Confirm circuit of CLK Gen.
1.Check Reset signal RST#
2.Check Control signal LFRAME#/INIT#
DIS_SYSBIOS#
Change BIOS Chip / South Bridge
1.Confirm PCB Trace
Confirm related circuit,
Check Resister and
Fix any trace open

Visual Inspection
1.check BIOS pins is open or
short
Use External BIOS Boot up
1.If External BIOS can Boot up
computer ,we can try to update
BIOS image file first
External
BIOS
1-1
1-2
Jump Setting :
1. 2. 3. 4.
on off on off --- Boot from debug card
off off on off --- Boot from M/B
on off off off --- Update M/B Bios From Debug Card

2
Check VDD Voltage:
Check BIOS VDD(+3VS) Voltage :
Pin 1 : +3V
Pin 25: +3V
Pin 27: +3V
Pin 32: +3V
VDD
25
32
VDD
3
Check CLK Frequency
Check BIOS CLK Frequency:
Pin 31: 33MHZ
CLK
1
27
VDD31

Repair Technique-Measure BIOS Signal
Measure BIOS Controller Signal:
Pin 2 : RST#
Pin 11: DIS_SYSBIOS#
Pin 23: LFRAME#
Pin 24: INIT#
4
24
RST#
11DIS_SYSBIOS# 23 LFRAME#
INIT#
2
Measure BIOS Pin signal of Diode value is
normal or not?
Pin 13: LAD[0]
Pin 14: LAD[1]
Pin 15: LAD[2]
Pin 17: LAD[3]
5
14
13
15
17
LAD[0]
LAD[3]
LAD[2]
LAD[1]

PIN
Signal
Name
Diode
Value
1 VPP 431
2 RST# 778
3 FPG13 OL
4 FPG12 OL
5 FPG11 OL
6 FPG10 OL
7 WP# 807
8 TBL# 807
9 NC OL
10 NC OL
11 DIS_SYSBIOS# OL
12 NC OL
13 LAD0 690
14 LAD1 690
15 LAD2 690
16 GND 0
PIN
Signal
Name
Diode
Value
17 LAD3 690
18 NC OL
19 NC OL
20 NC OL
21 NC OL
22 NC OL
23 LFRAME# 683
24 INIT# 607
25 VCC 431
26 GND 0
27 VCC 431
28 GND 0
29 IC OL
30 FPG14 OL
31 CLK 758
32 VCC 431
Repair Technique-Diode Value of BIOS Pin
1234
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20
21
22
23
24
25
26
27
28
29
303132

Chapter 20
MEMORY Repair Guide

Overview
 Diagram
 Introduction
1.DDR
2.DDRII
3.DDR3

Diagram(1)
Main Clock Gen.
Memory Bus
Memory Module (DDR)
Type 1
GMCH
/MCH
MA0~13
MD0~63
CLK
Gen.
+2.5V ( for DDR ) +1.25Vs (for DDR )
CLK
Gen.
DDR Clock Gen.
N.B

Diagram(2)
Main Clock Gen.
Memory Bus
Memory Module (DDR, DDR2)
Type 2
GMCH
/MCH
MA0~13
MD0~63
CLK
Gen.
+1.8V ( for DDR2 )
+2.5V ( for DDR )
+0.9Vs ( for DDR2 )
+1.25Vs (for DDR )
N.B

Diagram(3)
Main Clock Gen.
Memory Bus
Memory Module (SDR)
Type 3
GMCH
/MCH
MA0~13
MD0~63
CLK
Gen.
+1.5Vs ( for DDR3 )
CLK
Gen.
DDR Clock Gen.
N.B

Introduction
 What is memory anyway?
 All computer functions have common features
 Data processing (CPU, GPU….)
 Data storage (CDR, HDD, Memory…)
 Data movement (FSB, PCI-E, USB….)
 Control (North Bridge, South Bridge…)
 Why memory improve performance?
 CPU runs much more faster than HDD.
If all data & application were stored in HDD.
CPU will always wait for HDD to pass data.
 Bottle neck in HDD, CPU idle most of the time
 Memory enhance the usage of CPU.

RAM Family
 Static RAM (SRAM)
 Faster, more expensive
 Need not to be recharged regularly like DRAM
 Cache
 Dynamic RAM (DRAM)
 Less expensive, need to be refreshed
 DRAM subtypes to be introduced
– Synchronous DRAM (SDRAM)
Please refer to SDRAM(New).ppt for details.
– Double Data Rate Synchronous DRAM (DDR)
Please refer to DDR (New).ppt for details.
– Double Data Rate 2 Synchronous DRAM (DDR2)
Please refer to DDR II(New).ppt for details.
– Rambus DRAM(RDRAM)
not being used anymore, not being discussed here.
Please refer to RDRAM(New).ppt for details.

DRAM Family

DDR I vs DDR II

DDR3 Introduction
DIMM with eight DDR3 SDRAM devices

SO-DIMM Type
 SO-DIMM
 144 pins
 200 pins
 200 pins
 Micro-DIMM
 172 pin
 214 pin Micro DDR2-DIMM
214 pins
SDR SO-DIMM
144 pins
DDR SO-DIMM
200 pins
DDR2 SO-DIMM
200 pins
Micro DDR-DIMM
172 pins

What memory looks like?

Performance release terms
 Performance related terms
 Access Time (Nano seconds)
 measuring from when the memory module receives a
data request to when that data becomes available.
lower numbers indicate faster speeds.
 CAS latency
the number of clock cycles it takes before a column
can
be addressed on the DRAM chip.
Latency is a measure of delay
 Dual channel mode
please refer to the picture next page.

Other important terms
 MEMORY BANKS
Most computer systems have two or more memory banks –
usually called bank A, bank B
 Error Correction Code (ECC)
data integrity checking method used primarily in high-end PCs
and file servers. Please refer to ECC(New).ppt for details.
 Serial Presence Detect (SPD)
store information about the memory module.
 Please visit
http://www.webopedia.com/quick_ref/dram_memory.asp &
http://www.webopedia.com/Hardware/Memory/ for more info.

SPD
 When a computer is booted (started), serial presence detect
(SPD) is information stored in an electrically erasable
programmable read-only memory (EEPROM) chip on a
synchronous dynamic random access memory (SDRAM)
memory module that tells the basic input/output system
(BIOS) the module's size, data width, speed, and voltage
SPD Chip Serial EEPROM
256 Bytes

DDR Basic
 Short for Double Data Rate-Synchronous DRAM,
a type of SDRAM that supports data transfers on
both edges of each clock cycle (the rising and
falling edges), effectively doubling the memory
chip's data throughput.
 DDR-SDRAM also consumes less power, which
makes it well-suited to notebook computers.
DDR-SDRAM is also called SDRAM II and
DDRAM.

DDR Naming
Naming conventions and theoretical bandwidths of DDR
SDRAM

Throughput
 DDR 266 operating clock is 266MHz，if the data bus
width is 64bit，in other word it’s 8bytes，thus DDR 266
memory bandwidth is 266MHz x 8=2100MB/s，i.e. PC
2100.
Double Data Rate
X 2
Clock Freq.
133MHz
Data Freq.
266 MHz
266 MHz
266 x 8= 2100MB/s64 bit = 8bytes

Throughput
 PC1600 (DDR200)
 100(MHz)×2×8(Byte) = 1.6GB/S
 PC2100 (DDR266)
 133(MHz)×2×8(Byte) = 2.1GB/S
 PC 2700 (DDR333)
 166(MHz)x2x8(Byte) = 2.7GB/S
 PC 3200 (DDR400)
 200(MHz)x2x8(Byte) = 3.2GB/S
100 / 133 / 166 / 200MHz
200 / 266 / 333 / 400 MHz
Data strobe signal
(Double Data Rate)

DDR Electrical Interface
 Double Data Rate IC's use 2.5 volt SSTL_2
compatible I/O [class II], how ever the supply
voltage may be higher. The main supply
voltage [VDD] is 3.3v or 2.5v for DDR 200,
DDR266, and DDR333, while 2.6v for
DDR400. The output drive supply [VDDQ] is
3.3v or 2.5v for DDR200, DDR266, and
DDR333, while it's 2.6v for DDR400. DDR
uses a bi-directional data strobe to indicate
valid data [DQS].
 STL-2: Stub Series Terminated Logic for 2.5v
[JESD8-9]. Class II provides for higher power
dissipation, Higher drive and a maximum
current of 15.2mA. DDR, Double Data Rate.
[JESD79] defines two data transfers per clock
cycle. The Clocks are differential. Power
Supply [VDD = 3.3v + 0.3v or 2.5v + 0.02v for
DDR 200, DDR 266, or DRR 333; and 2.6v +
0.1v for DDR 400]. Inputs and outputs are
compatible with SSTL_2. These DIMMs are
184 Pin in size and are not interchangeable
with older 168 on SDRAM modules.

DDR2 Basic
 DDR2 SDRAM (Double Data Rate Two Synchronous
Dynamic Random Access Memory)
 The advantage of DDR2 over DDR SDRAM is its ability
to run at much higher clock speeds due to an improved
electrical interface.
 Like DDR, DDR2 will transfer data on every rising and
falling edge of the clock (double pumped), achieving an
effective rate of 200 MHz with the same clock frequency

DDR2 Basic count.
 DDR2 DIMM memory modules are not backward-
compatible with DDR DIMM , due to incompatible pin
configurations, core voltage, and memory chip
technology.
 DDR2 modules are designed with a different "key" in the
edge connector to prevent insertion into incompatible
memory sockets such as DDR motherboard. A DDR2
SDRAM DIMM will not fit into a standard SDRAM
DIMM socket or a DDR DIMM socket.
 DDR2 modules use a 1.8V power supply, providing a big
power saving over the 2.5V DDR modules.

DDR I /DDR II
 In this scenario, the core is running at 100 MHz, for DDR I, the I/O
buffers is synchronous with the core.
 Only the protocol varies and in the case of DDR II, the I/O buffers
are clocked at twice the core frequency. In order to satisfy the
output
 DDR I prefetches 2 bits, DDR II needs to prefetch four bits with
every read command and pipeline them for time multiplexed output.

DDR vs. DDR II
Read Latency-11TWrite Latency
3+, 4, 51.5, 2, 2.5CAS Latency
Differential Strobe: DQS,
/DQS***
Single DQSData Strobe
4/8**2/4/8Burst Length
4 bit2 bitPrefetch Size
100/133/(166) MHz100/133/166/200 MHz
DRAM Core
Frequency
200/266/(333) MHz100/133/166/200 MHzBus Frequency
400/533/(667)
Mbps*
200/266/333/400
Mbps*
Data Rate
Frequency Specs
DDR IIDDR

DDR vs. DDR II count.
Power Specs
Core Voltage (VDD) 2.5V++ 1.8V
I/O Voltage (VDDQ) SSTL_2 (2.5V) SSTL_1.8 (1.8V)
Format
Packaging TSOP (II), TBGA FBGA
Compatibility With DDR I
Command Set Same as DDR I
Basic Timing
Parameters
Same as DDR I
Bus Utilization and Signal Integrity
New Features
ODT
OCD-calibration
Posted CAS
Additive Latency+++

Dual Channel
 The two channels handle memory-processing more
efficiently by utilizing the theoretical bandwidth of the two
modules, thus reducing system latencies, the timing delays
that inherently occur with one memory module.
 Matched DIMM configuration in each channel
 Same Density (128MB, 256MB, 512MB, etc.)
 Same DRAM technology (128Mb, 256Mb, or 512Mb)
 Same DRAM bus width (x8 or x16)
 All either single-sided or dual-sided
Rules to Enable Dual Channel Mode

DDR2 Electrical Interface
 Double Data Rate II IC's use 1.8
volt SSTL_18 compatible I/O [class
II], how ever the supply voltage may
be higher.
SSTL-18: Stub Series Terminated
Logic for 1.8v [JESD 8-15A]. Class
II provides for higher power
dissipation, Higher drive and a
maximum current of 15.2mA

DDR2 Termination
 DDR2 modules contain the require resistor termination located on the
memory chips using a technique called On-Die Termination [ODT].
While DDR1 modules have the necessary resistive termination located
on the motherboard. Using ODT, DDR2 are able to reduce the parts
count required for mother board while at the same time locate the
terminations closer the the signal destination. The ODT termination
can be turned on or off by the DRAM controller. Normally the
terminations are turned on for Writes and disable for Reads. The value
of the ODT termination is selectable based on the number of modules
in the system. With one DIMM module the ODT value is set at 150
ohms [300Ω pull-up and 300Ω pull-down]. When two modules are
loaded into the system the ODT value is changed to 75 ohms [150Ω
pull-up and 150Ω pull-down] for the DIMM not being written to while
the DIMM being accessed has its ODT turned off. Writing to the
Extended Mode Register [EMR] controls the ODT presence and value.
Three combinations are allowed; termination disabled, 75 ohms, and
150 ohms [ also 50 ohms]. The newest revision adds 50 ohm
termination values. ODT improves the eye-diagram over SSTL for
either Single-Rank or Dual-Rank modules.

DDR 3
 DDR3 SDRAM(Double Data Rate Three Synchronous
Dynamic Random Access Memory)
 DDR3 SDRAM improves on DDR2 SDRAM in several
significant ways:
1.Higher bandwidth due to increased clock rate
2.Reduced power consumption due to 90nm fabrication
technology
3.Pre-fetch buffer is doubled to 8 bits to further increase
performance
4.The voltage of DDR3 SDRAM DIMM's was lowered from
1.8V to 1.5V. This reduces power consumption and heat
generation, as well as enabling more dense memory
configurations for higher capacities.

Standard DDR3 SDRAM DIMM's
 DDR3 SDRAM is normally packaged in DIMM
modules.

DDR 3 Front View

DDR 3 Back View

DDR SO-DIMM
Signal Description

DDR Pinout

Pin function

Pin Description-1

Pin Description-2

DDR2 SO-DIMM
Signal Description

DDR2 Pinout

Pin function

Pin Description-1

Pin Description-2

Pin Description-3

Pin Description-4

Pin Description-5

Pin Description-6

Pin Description-7

DDR Micro-DIMM

Micro-DDR Pinout

Pin function

DDR2 Micro-DIMM

Micro-DDR2 Pinout

Pin function

Pin Description-1

Pin Description-2

Pin Description-3

Pin Description-4

Pin Description-5

Repair Flow Chart
Start
Visual Inspection
check memory slot is no bent pin
or damaged.
Measure memory Voltage
Measure memory
Data /Address signals and control signals
,RAS#,CAS#,WE#
Finish
Fix any trace or RLC damaged/
change NG CLK Generator
Check Memory Voltage,
1.8V or 2.5V or 1.5V (depend on Memory type)
Check Memory Vtt Voltage,
0.9Vs or 1.25Vs (depend on Memory type)
Check Memory Clock,
100 / 133 / 166 …MHz
Fix any voltage regulator IC
or related RLC component,
Fix any trace open
OK
NG
OK
NG
NG
OK
Use Multi-Meter to measure,
Trace NG signals and compare
with good MB
Fix any trace open
or resistor damaged
OK
Change any damaged memory slot or component/
Fix any bad solder or trace open
Measure memory Clock
Change
N.B
NG

Visual Inspection
1.Check memory slot / Pin is not
damaged or bent pin inside.
2.Check related resistor , capacitor
component no damage.
3.Fix any trace open or BAD solder
CID
CID
1-1
1-2

Repair Technique-Measure Memory Voltage
Use Multi-Meter or
Oscilloscope to measure
Memory Voltage & Vtt
Voltage .
Memory Voltage:
SDRAM: 3Vs
DDR :2.5V
DDR2: 1.8V
Memory Vtt Voltage:
DDR :1.25Vs
DDR2: 0.9Vs
DDR Vtt Voltage
=2.5V
DDR Vtt Voltage
=1.25V
2-1
2-2

Repair Technique-Measure Memory Clock
Use Oscilloscope to measure Memory
Clock
(100Mhz,133Mhz,166Mhz…depends on
different chipset & memory)
Memory CLK=
100,133,166…MHz
3-1
3-2

Repair Technique-Measure Memory Signals
Plug Memory measure card into slot.
Use Multi-Meter to measure memory
signals’ bias voltage value. Compare
with good MB if you find any
unusual.
Diode Mode 4

Memory DIMM Measure Tools(1)
SDRAM Signal Measure tool
DDR Signal Measure tool
DDR2 Signal Measure tool
1. GSENG_FB SODIMM PINNAME R1.00
P/N: 08-900028700
2. ENG_TSNB DDR PIN Board R2.00
P/N: 08-900029500
3. ENG_FAE_DDR2 TEST R1.00
P/N: 08-900042700
5-1
5-2
5-3

Memory DIMM Measure Tools(2)
1. ENG_TSNB_MICRODDR/B Rev2.0
P/N: 08-900033000
Micro DDR Signal Measure tool
6

Repair Technique-Diode Value (DDR-DIMM Sample)

Chapter 21
POST CODE Repair Guide

Overview
 What is POST CODE
 Using POST Code to Debug
 Appendix:
(1)BIOS CODE Definition
(2)BIOS Beep Code

What is POST Code
 POST : Power On Self Test
 The tag thrown out by BIOS
– Usually, BIOS would output some number through
80ports. Using I/O access card (debug card), user could
read those number.
– The POST codes used by Award, Phoenix, and AMI are
different.
– These numbers mean something was executing in the
system.

What is POST Code
 POST Code as BIOS executing process
 Standard POST Code
– These numbers were used as standard process.
 BIOS Debug Code
– These numbers depend on various project.

POST “00”, “FF”
POST Code “00”,”FF” or Debug card shows all dots(……) / all 00
(1)Check Voltage:
a.) Vcore ,if no Vcore check from power block circuit diagram
b.) 1.5v,if no 1.5v check from power block circuit diagram
c.) 2.5v,if no 2.5v check from power block circuit diagram
d.) 3.3v,if no 3.3v check from power block circuit diagram
e.) check for N/B,S/B voltage is ok or not
(2)Check CLK:
a.) CPU CLK,if no CPU CLK check from CLK gen. circuit diagram
b.) N/B CLK,if no N/B CLK check from CLK gen. circuit diagram
c.) S/B CLK,if no S/B CLK check from CLK gen. circuit diagram
d.) 14.318MHz,if no 14.318MHz check from CLK gen. circuit diagram
e.) CLK generator.if all no CLK,change 14.318MHz,and then change CLK
gen. Before must check any open or short

(3)Check Power ok & Reset
a.) H/W reset,if low voltage check circuit diagram, normal is capacitor bad
b.) power supply power ok,if low voltage,normal is capacitor bad
c.) CPU power ok,if low voltage check circuit diagram,and above signal
d.) PCI reset,if low voltage check above signal and for S/B CLK,voltage
e.) CPU reset,if low voltage check above signal and for N/B CLK,voltage
f.) Check boot up sequence.
(4)Check control signal:
a.) Check CPU control signal(ADS#,BRDY#…) is ok or not
b.) Check PCI control signal(FRAME#,IRDY#,TRDY#…) is ok or not
c.) Check others control signal is ok or not

00(no data)
(1)Change BIOS
(2)Check bios voltage
(3)Check BIOS CLK
(4)Check LAD0~3
(5)Check BIOS control signal
(6)Check CPU control signal
00(Have address & data)
(1)CPU N/B:HD0~63,HA3~HA31,control signal open or short
(2)N/BS/B:PCI BUS(AD0~AD31,CBE0~CBE3) or HUB
Link(HL0~HL10) or V_link or LDT BUS open or short
(3)S/BBIOS:ISA BIOS(SA0~SA19,SD0~SD7) or LPC BUS
(LAD0~LAD3) open or short

POST “C0”, “D0”
C0 (Award)
D0 (AMI)
(1)Change BIOS
(2)Check HD0~63 signal open or short
(3)Check HA3~31 signal open or short
(4)Check AD0~31 signal open or short
(5)Check SM BUS is ok or not
(6)Check all Voltage is ok or not ,especially 2.5V,3VS
(7)Check all CLK is ok or not
(9)Check SB, especially for Intel ICH4

POST “C1”, “9F”, “D3”, “EF”….
C1, E1, 9F, 99, Ad (Award)
D3, D4, E0, E5, A4 (AMI)
EF, EE, 28 (Phoenix)
(1)Change BIOS
(2)Check Memory voltage is ok or not, especially 3V, 2.5V, 1.8V ,
1.25Vtt , 0.9Vtt
(3)Check Memory CLK is ok or not
(4)Check SM BUS is ok or not
(5)Check MA,MD,CAS,RAS,CKE… signal is Open or Short
(6)DIMM socket not clean or bad
(7)Check HA,AD,CPU control signal is open or Short

POST “C3”, “C5”, “05”
C3 (Award)
(1)Change BIOS
(2)Check memory problem
(3)Check frequency problem
C5 (Award)
(1)Change BIOS
(2)Check memory problem
(3)Check HA3~31 is open or short
05 (Award)
(1)Check KBC CLK is ok or not
(2)Check KBC voltage is ok or not
(3)Check KBC address,data,control signal is open or short
(4)Change KBC

POST “0B”, “13”, “20”
0B (Award)
(1)Change BIOS
(2)Check battery is ok or not
(3)Check all CLK signal(14.318MHz,25MHz,40MHz….)
(4)Check all voltage is ok or not
(5)Check INIT,TRDY#,RADY signal… is open or short
(6) Check C/BE0~3 is short or not
(7)Check all control signal(CPU,PCI,AGP) is open or short
13 (AMI)
(1) Check 1.5V to NB
20 (AMI)
(1) Check 2.5V , 1.25Vtt or 1.8V ,0.9Vtt
(2) Check Memory problems
(3) Check AGP signals

POST ”31”,”3D”,”41”
31,3D (Award)
(1)Check KBC CLK is ok or not
(2)Check K/B problem
(3)Check CPU control signal(HITM#,ITIN,ITNK#…)is
open or short
(4)Check N/B control signal… is open or short
41 (Award)
(1)Change BIOS
(2)Check SA0~SA16 is Open or short
(3)Check MEMR#,MEMW# is open or short
(4)Check HA3~31 is open or short

POST “4E”, “61”, “85”
4E (Award)
(1)Check TRDY#,DEVSEL# is open or short
(2)Check K/B problem
61 (Award)
(1)Check Cache problem
(2)Check CPU control signal is ok or not
(3)Check N/B control signal is ok or not
85 (AMI)
(1) Check Bios
(2) Check NB (No display problem)

POST CODE Definition
 AMI POST Code definition
 AWARD POST Code definition
 Phoenix POST Code definition

AMI Bios Code Definition-1

Award Bios Code Definition-1

Phoenix Bios Code Definition-1

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