The document describes a technique for timing-driven variation-aware nonuniform clock mesh synthesis. The technique involves four main stages: 1) deriving a timing constraint graph from static timing analysis, 2) generating a skew map of rectangular regions with different skew requirements, 3) removing overlapping rectangles to generate non-overlapping polygons, and 4) generating a clock mesh for each polygon where mesh density satisfies skew variations. The technique aims to generate a clock mesh that satisfies maximum skew variation requirements while considering process, voltage, and temperature variations.

1. Timing–Driven Variation–Aware Nonuniform Clock Mesh Synthesis Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, and Eby G. Friedman* Electronics Computers Communications This research was supported in part by the Technion ACRC and by the ALPHA research consortium * Also with Dept. of Electrical and Computer Engineering, University of Rochester Technion – Israel Institute of Technology Department of Electrical Engineering

3. Non-tree Clock Topologies (2) Pentium 4 spine [1] Tree with crosslinks [2] Leaf level global mesh Global mesh with local trees (MLT) [3] Global tree with local meshes (TLM) [3] [1] N. A. Kurd et al., “A Multigigahertz Clocking Scheme for the Pentium 4 Microprocessor,” JSSC 36(11):1647–1653, 2001. [2] A. Rajaram, J. Hu, and R. Mahapatra, “Reducing Clock Skew Variability Via Crosslinks,” Proc. DAC, pp. 18–23, 2004. [3] C. Yeh et al., “Clock Distribution Architectures: a Comparative Study,” Proc. ISQED, pp. 27-29, 2006.

4. Motivation mesh

5. Method

16. Results