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Placement and routing in full custom physical design
- 1. Seminar Placement and Routing options in Full Custom Shankardas Deepti Bharath CGB0911002 VSD528 M. Sc. [Engg.] in VLSI System Design Module Title: Full Custom Physical Design Module Leader: Mr. Chandramohan P.
- 3. Introduction Floor planning CTS Physical Design Partitioning Routing Placement Specification Architectural design Circuit design Physical design Test/Fabrication Logic design
- 7. (a) Diffusion sharing (b) Gate matrix layout (c) Tapering technique (f) Common centriod (e) Interdigitization (d) Fingering Analog custom design Mixed custom design Digital custom design Placement in Custom Design Figure 1. Placement techniques in custom design
- 8. After Placement Macros Standard Cells IO Pads Corner Cells VDD rails VSS rails Power & ground straps Figure 2 Chip level placement
- 14. After Routing Figure 7 Block level routing Figure 8 Magnified portion of the block
- 16. References [1] Jon Wateresian (2002) Fabricating Printed Circuit Boards. Massachusetts: Newnes [2] Linfu Xiao, et al. , ‘ Practical Placement and Routing Techniques for Analog Circuit Designs’ , IEEE, Dept. of CSE, Chinese Univ. of Hong Kong, Shatin, China, Dec 2010. [3] Chandramohan P., Digital circuit design and layout, Full custom physical design (VSD 528), session-2 MSRSAS, Bangalore [4] Shawki Areibi and Zhen Yang (2003), ‘Congestion Driven Placement for VLSI Standard Cell, Design’ , School of Engineering, University of Guelph, Ontario, Canada, Dec 2003.
- 17. Thank You
Notas del editor
- 1.Metal routes must meet minimum width and spacing “design rules” to prevent open and short circuits during fabrication. 2. Congestion can be reduced by adding blockages during floor planning. When a blockage is placed the router, routes around the blockage thereby reducing congestion.
- Detour – Routing takes a longer route instead of a shorter one. In GR no PHYSICAL connections are made only nets are assigned to specific metal layers.
- If TA can reduce the number of jogs and jumps in metal traces, this will generally improve timing (since each jump generally requires a via to jump to a higher or lower level metal layer). Reducing the number of vias is generally a plus for reliability and yield since their failure rate is slightly higher than that of a simple, straight metal track in a modern, planarized process.
- The detail route doesn’t work on the entire chip at a time but instead works, box by box (using a fixed size box called Sbox) until the routing pass is complete.
- Search and Repair divides the chip into SBoxes and works through each SBox sequentially trying to fix DRC violations by rerouting within the confines of the box. Droute – Detail Route…Sbox – Square Box.