Minimum Cost Fault Tolerant Adder Circuits in Reversible Logic Synthesis

Minimum Cost Fault Tolerant
Adder Circuits in Reversible Logic
Synthesis

Sajib Kumar Mitra*
Department of Computer Science and Engineering
Faculty of Engineering and Technology
University of Dhaka, Dhaka-1000, Bangladesh
E-mails: sajibmitra.csedu@yahoo.com, farhan717@cse.univdhaka.edu
*
Corresponding Author and Presenter

Purposes

• Minimization of Quantum Cost
• Fault Tolerant Circuit
• Reduction of Critical Path Delay
• Reduction of Number of Gates
• Garbage Outputs Optimization

Overview

• Reversible and Quantum Computing
• Quantum Realization of Reversible Circuits
• Fault Tolerant Mechanism
• Proposed Designs of Adder Circuits
• Performance Analysis
• Conclusion

Reversible and Quantum Computing

Reversible Computing

• Equal number of input states and output states
• Preserves an unique mapping between input and
output vectors for any Reversible circuit
• One or more operations can be united called
Reversible Gate
• (N x N) Reversible Gate has N number of inputs and
N number of outputs where N= {1, 2, 3, …}

[1] A. K. Biswas, M. M. Hasan, A. R. Chowdhury, and H. M. H. Babu, “Efficient approaches
for designing reversible binary coded decimalimplement in a single adders,”
Microelectronics Jounrnal, vol. 39, no. 12, pp. 1693–1703, December 2008.

Reversible Computing…

Fig. 1: Basic difference between Irreversible and
Reversible Circuits

• Limitation
• Feedback is strictly restricted
• Fan-out must be one always

Reversible Computing…

Fig. 2: Popular Reversible gates

Quantum Computing

In Quantum Computing, encode information as a series of
quantum-mechanical states such as spin directions of
electrons or polarization orientations of a photon that
might represent as or might represent a superposition of
the two values.

Encoded data is represented by qubits rather than bits
which can perform certain calculations exponentially
faster than conventional computing.

q =α 0 + β 1

[2]W. N. N. Hung, X. Song, G. Yang, J. Yang, and M. Perkowski, “Quantum logic synthesis by
symbolic reachability analysis,” in 41st Conference on (DAC’04), Design Automation
Conference, May 2004, pp. 838–841.

Quantum Computing…

Quantum Computation uses matrix multiplication rather
than conventional Boolean operations and the information
measurement is realized by calculation the state of qubits .

The matrix operations over qubits are simply specifies by
using quantum primitives. For example,

Fig. 3: Reversible behavior of Quantum matrix operation

Quantum Computing…

Input Output
A B P Q
0 0 0 0
0 1 0 1
1 0 1 1
1 1 1 0
Input/output Symbol
Pattern
00 a
01 b
10 c
11 d

Fig. 4: Working Principle of Unitary Controlled NOT (UCN)

Quantum Realization of Reversible
Circuits

Quantum Cost

• Quantum Cost (QC): Total number of 2x2 quantum
primitives (4x4 unitary matrices) which are used to form
equivalent quantum circuit of any Reversible Circuit.

Fig. 5: Several Quantum Primitives
[3] M. Perkowski and et al, “A hierarchical approach to computer-aided design of quantum
circuits,” in 6th International Symposium on Rep-resentations and Methodology of Future
Computing Technology, 2003, pp. 201–209.

Orientation of Quantum Gates

The attachment of SRN (Hermitian
Matrix of SRN) and EX-OR gate on the
same line generates symmetric gate
pattern has a cost of 1.
Here T= V or V+

Fig. 6: Difference interactions between Quantum Primitives

Quantum Cost of Reversible gates

Fig. 7: Equivalent Quantum Circuits of Reversible Gates

Working Principle of Quantum Circuit

How does
Quantum
circuit work?

Fig. 8: Toffoli Gate and corresponding Quantum Circuit

Working Principle of Quantum Circuit…

INPUT OUTPUT

A B R
0 0 C
0 1 C
1 0 C
1 1 C’

Fig. 9: Working Principle of Quantum Equivalent of TG


INPUT OUTPUT

A B R
0 0 C
0 1 C
1 0 C
1 1 C’

Quantum Cost of Toffoli Gate is 5

Alternate representation of Quantum
circuit of TG…

Proposed Quantum Circuit of NFT

Fig. 9: Quantum Realization of NFT Gate (QC= 5)

Proposed Quantum Circuit of NFT…

Fault Tolerant Mechanism

Preserves same parity between Input and Output vectors
over one to one mapping of Reversible circuit.

Fig. 10: Fault Tolerant circuit preserves same parity
between input and output vectors
[4] B. Parhami, “Fault tolerant reversible circuits,” in In Proc. of 40 th Asimolar Conference
Signals, Systems and Computers. Pacific Grove, CA, 2006, pp. 1726–1729.

Fault Tolerant Mechanism...

Let, Iv and Ov are input and output vectors of a reversible
circuit, so the relation is Iv↔Ov.
But to be a Reversible Fault Tolerant circuit, itself must
preserve following equation:

I1 ⊕ I 2 ⊕ ⊕ I n = O1 ⊕ O2 ⊕ ⊕ On

where Iv={I1, I2, I3, …, In} and Ov={O1, O2, O3, …, On}

Input Parity = Output Parity

Fault Tolerant Mechanism…

Fig. 11: Most Popular Fault Tolerant Gates


INPUT OUTPUT
A B C P Q R

0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 0
0 1 1 0 1 1
1 0 0 1 0 0
A ⊕ B ⊕C = P ⊕Q ⊕ R
1 0 1 1 1 0
1 1 0 1 0 1
1 1 1 1 1 1


Verification of the following equation:
A ⊕ B ⊕C = P ⊕Q ⊕ R

Circuit without Fault Circuit with Faulty Output

Fault detection of FRG gate


QC= 2 QC=5

QC= 5 QC= 7

Proposed Design of Adder Circuits

Proposed Design of Full Adder
Reversible Fault Tolerant Full Adder

2 2
2 5

2 2 5 2
Fig. 12: Proposed Design of Fault Tolerant Adder Circuit

Comparison with Existing Design
Comparison with Existing [5] Fault Tolerant Design

7 7
Single NFT Full Adder
2 SNFA
2 5 2
[5] M. S. Islam, M. M. Rahman, Z. begum, and M. Z. Hafiz, “Efficient approaches for designing
fault tolerant reversible carry look-ahead and carry-skip adders,” MASAUM Journal of Basic and
Applied Sciences, vol. 1, no. 3, 2009.

Proposed Design of Carry Skip Adder

Reversible Fault Tolerant Carry Skip Adder
(RFT-CSA)

Fig. 13: Proposed Design of Fault Tolerant Carry Skip
Adder

Delay Calculation of RFT-CSA

Delay Optimization of Fault Tolerant Carry Skip Adder

4

5
9 8 7 6

Fig. 14: Delay Calculation of RFT-CSA

Performance Analysis of RFT-CSA
140
Gates Garbage Delay Quantum Cost
120

100

80
U
n
s

60
)
(
t
i

40

20

0
Proposed Existing [5] Exising [6] Existing [7]

Fig. 15: Compare with existing designs of Carry Skip Adder
[6] P. K. Lala, J. P. Parkerson, and P. Charaborty, “Adder designs using reversible logic
gates,” WSEAS TRANSACTIONS on CIRCUITS and SYSTEMS, June 2010.
[7] J. W. Bruce et al., “Efficient adder circuits based on a conservative re-versible logic
gates,” in ISVLSI ’02: Proceedings of the IEEE Computer Society Annual Symposium on VLSI.
Washington, DC, USA, 2005, pp. 83–88.

Proposed Carry Look-ahead Adder
Reversible Fault Tolerant Carry Look-ahead Adder
(RFT-CLA) Circuit

Fig. 16: Proposed design of Fault Tolerant Carry Look-
ahead Adder

Delay Calculation of RFT-CLA

1 2 3

Delay 4
Calculation of
Fault Tolerant
Carry Look-
ahead Adder
5

6 7

Performance Analysis of RFT-CLA

70
60
50 Gates
40 Garbage
U
n
s

30
)
(
t
i

Delay
20
Quantum Cost
10
0
RFT-CLA RFT-CSA

Fig. 17: Performance Analysis between Fault Tolerant
Carry Look-ahead Adder and Carry Skip Adder

Conclusions

Reversible Circuit prevents power consumption caused by
input bit loose and tolerates bit error by using fault tolerant
mechanism. The operations of Quantum Computing are
fundamentally reversible and circuit performs multiple
operations in single cycle. We have presented the efficient
designs of fault tolerant reversible adder circuits, where the
designs are preferable for quantum computing because of
minimum quantum cost in the designs.

Minimum Cost Fault Tolerant Adder Circuits in Reversible Logic Synthesis

Recomendados

Recomendados

Más contenido relacionado

La actualidad más candente

La actualidad más candente (20)

Destacado

Destacado (8)

Similar a Minimum Cost Fault Tolerant Adder Circuits in Reversible Logic Synthesis

Similar a Minimum Cost Fault Tolerant Adder Circuits in Reversible Logic Synthesis (20)

Último

Último (20)

Minimum Cost Fault Tolerant Adder Circuits in Reversible Logic Synthesis