2. Devices’ Quality drive profitability
Big electronics players changed the game rules
Consumer mass production products like cell phones, Pads, laptops use dual strategy ingredients
Samsung S3 smart phone has 2 design wins for its cpu – nVidia’s Tegra & Qualcomm’s Snapdragon
Their BoM price is similar – what differentiates sellable quantities is Quality levels (RMA#s)
Excelling in quality became a big deal and a bottom line revenue differentiator
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3. Trends driving quality attention Wafer level packaging (WLCSP | WCSP | WLP | WLBGA)
For the last few years new Wafer Level Packaging technology is being used for many products like mobile phones, PDAs, laptop PCs, disk drives, digital cameras, MP3 players, GPS etc
After the FAB process the wafer goes through those steps:
wafer bumping, wafer level test, back grind, dicing, and
packing in tape & reel to support a full turn-key WLCSP solution
That means that THERE IS NO MORE FT/BI/SLT OPERATION !!! The tape is going directly to the customer after wafer sort for board level mounting… (i.e to Apple, Samsung, dell Sony etc)
Thus, Quality becomes critical since there is no other gate keeper
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4. The need
Handling potential escapes & outliers, requires a comprehensive system which covers the end-to-end supply chain:
Analysis and simulation tools to evaluate potential escapes and outlier algorithms on historical data
Rule generation and publication processes to deploy escape prevention and outlier rules at test houses
Execution of the escape prevention and outlier rules on OptimalTest's servers once testing is completed anywhere in the supply-chain
Fully integrated and automated modification of inkless bin maps for assembly or in Final-Test anywhere in the supply-chain
Monitoring and feedback tools to track the actual performance of the escape prevention and outlier detection
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5. Tight quality “safety net”
The solution should be an Escape Prevention Solution (EPS) enables a tight safety net that becomes the “escape gate- keeper” in any of your testing operations
The solution should offer Fabless or IDM Business-Units the ability to create & activate rules vis-à-vis their Foundry, OSAT or IDM Factory -The rules should be executed through a integrated supply chain infrastructure to provide full Quality & health control
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6. –Strategic supplier of top Fabless, IDM & OSAT
–Installed across whole world-wide Fabless/Foundry/OSAT supply chain at
-
Some facts… about OptimalTest
#1 Fabless
#2 Fabless
#3 Fabless
#5 IDM
#3 OSAT
2013: ~3,300 testers - over 25M units run on OT per day… ~10B per year…. and growing
#4 Fabless
#5 Fabless
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7. Escape Prevention Solution
OptimalTest’s Escape Prevention Solution consist of the following elements:
RMA database for thorough management of the escapes
3 families of Outlier Detection capabilities for Wafer Sort & Final Test: Parametric , Geographical & Cross-Operational
OT-Detect: an excursion prevention system that automatically tracks after ALL your products for ANY changes in BASELINE production (HB, SB, Params)
Dozens of unique algorithms that were “created with blood” following many escapes and thorough RMAs analysis
OptimalTest is the only Outlier Detection provider that has an infrastructure embedded into the Foundries & OSATs operation (like TSMC & ASE)
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8. WS - Parametric Outlier Detection
These algorithms detect outliers based on the behavior of specific parametric tests.
DPAT: "Dynamic Part Average Testing" is a standard industry algorithm for outlier detection which captures every die with a parametric characteristic falling outside of a statistically calculated boundary.
NNR: "Nearest Neighbor Residual" is the best algorithm to use for avoiding yield overkill caused by Fab-related geographical differences (Center – Edge & Reticle locations) and Influence of intrinsic Test site differences. The data is "smoothed" to eliminate peaks and then NNR automatically applies different coefficients to reticle locations and test sites if the algorithm reveals a significant difference between groups.
•It can also use "bivariate" tests - virtual tests created as a regression of the two real parametric tests.
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9. WS - Geographic Outlier Detection
These algorithms detect outliers by analyzing the location of the die on the wafer and the die's neighbors:
Z-PAT: "Z-Axis Part Average Testing" Looks at dice in the same X,Y coordinates across multiple wafers in a lot to "kill" dice in locations that fail too frequently
GDBN: "Good Die in Bad Neighborhood" calculates the yield of the neighboring die for each good die; the die surrounded by a cluster of failing neighbors is removed based on a weighting algorithmic recipe
Bad Reticule Detection: "Bad Reticule Detection" captures specific reticule X, Y locations which have low yield in the current lot
Zonal: "Bad Zonal Detection" captures a specific zone with low yield in the current lot
P#9
10. Final Test - Parametric Outlier Detection
OptimalTest’s Outlier Detection for Final Test is based on 2 type of algorithms:
1)Post Final-Test operation and Based on Die-ID (ULT/OTP/ECID)
a)Option a: Next Operation execution (i.e SLT or WH)
b)Option b: FT-PAT operation (Short TP that reads only Die ID)
2)In real-time at Final-Test operation without Die-ID
the downside of this method is the outlier baseline statistical size
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11. Cross Operational Outlier Detection
–Cross operational Quality based on Die-ID
–Contributing operations
•ETEST/PCM/WAT
•Wafer Sort
•Final-Test
•Burn-In
•System Level Test
•Example: E-Test based bin switching post WS The ability to identify potential bad devices based on E-test data geographical analysis – The bin switching post wafer sort - Requires data feed forward within the supply chain .
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12. RMA Database
The new RMA Database will provide detailed information about parts returned from customers.
–Data Entry: Users can identify parts by ECID and mark them as returned in the database, together with categorization data.
–Data Retrieval: The RMA database is searchable and is summarized in standard summary tables so that information about RMA’s can be analyzed in OT-Portal.
–Historical Analysis: Lots containing parts which are returned are flagged in the database as “unpurgable”. It impacts all operations in which the part or wafer was tested. Cross operation reports can be used to analyze the cause of the failure.
P#12
13. •Probe mark tracking The algorithm tracks probe marks per each die at wafer sort and compares with a spec value. The rule takes into account restests & multiple operations as well as “hidden” probe marks in parallel testing when dice are touched but not tested.
Example of Escape Prevention Rules
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14. •Good die/device with “out of spec” test results The algorithm catches parametric tests which are marked as “pass” despite having a result which is out of spec limits.
•Failing tests in good parts Except for some specific cases, tests should not fail in good units. This rule checks that no failing tests matching a specified signature exist in a good part.
•PRR validation (Part Results Record) For each good die/device, the rule checks that the number of tests reporting in the PRR records for good parts is above spec. This rule can use a baseline to calculate the limit.
•ULT validation For products identified as ULT enabled, the rule will check each good die/device for ULT value (ULT = OTP/ECID)
•Freeze detection The rule can monitor selected critical tests and detect freeze cases by comparing parametric test values across multiple devices.
•Parametric trend The rule can monitor selected critical tests and detect statistical trend patterns in the test results that may indicate process quality issues .
•Process capability (CPk) The rule can monitor selected critical tests and detect CPk related abnormal behavior in the test results that may indicate process quality issues.
Example of Escape Prevention Rules
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15. •OT-Detect automatically tracks after ALL your products for ANY changes in BASELINE production
•Description: These statistical rules allows the user to detect issues through monitoring baselines of “too Bad” or “too Good” performance that are statistically suspicious e.g. Yields, Bin & S-Bins occurrences (SBLs) & Parametric Tests (STLs) etc…
•Once triggered it provides a step-by-step ROOT-CAUSE ANALYSIS. This means that any extreme change in the products' manufacturing, test or assembly processes will be tracked, captured and assessed.
Leveraging massive data: OT-Detect
Lot level Analysis
Prod level Analysis
Bin level Analysis
Param level Analysis
Equp level
Analysis
Facility level Analysis
Note: The ability to do so many baselines on the fly is a huge technological breakthrough since it requires optimized algorithms to enable super fast computations
What is a “Baseline”? Preforming a “baseline” means that the system automatically identify the incoming product, scan the last 20-40 lots of that product and determine if the current lot signature significantly exceeds the value of the historical baseline that was created on the fly - Either in Real- Time or in Off-line
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P#15