1. CSE 490/590 Computer ArchitectureMIPS Review & Pipelining I Steve Ko Computer Sciences and Engineering University at Buffalo

2. 2 Last Time… An ISA can have multiple implementations (Briefly) CISC vs. RISC CISC: microcoded (macro instructions & microinstructions) RISC: combinational logic MIPS microarchitecture Good RISC example Fixed format instructions Load/store architecture with single address mode Simple branch Will continue on this today…

3. 3 MIPS Instruction Formats Register-Register 5 6 10 11 31 26 0 15 16 20 21 25 Op Rs1 Rs2 Rd Func Register-Immediate 31 26 0 15 16 20 21 25 immediate Op Rs1 Rd Branch (Same format as Reg-Imm) 31 26 0 15 16 20 21 25 immediate Op Rs1 Rs2/Opx Jump / Call 31 26 0 25 target Op

4. Reg-Reg Instructions Op (e.g., 0) encodes that this is a reg-reg instruction Func encodes the datapath operations (add, sub, etc.) Rd  (Rs1) Func (Rs2) ADD R1,R2,R3 Add Reg[R1]  Regs[R2] + Regs[R3] 4 Register-Register 5 6 10 11 31 26 0 15 16 20 21 25 Op Rs1 Rs2 Rd Func

5. Reg-Imm Instructions Rd  (Rs1) Op (Imm) ADDI R1,R2,#3 Add immediate Regs[R1]  Regs[R2] + 3 LD R1,30(R2) Load word Regs[R1]  Mem[30 + Regs[R2]] BEQZ R4, name Branch equal zero If (Regs[R4] == 0) PC  name 5 Register-Immediate 31 26 0 15 16 20 21 25 immediate Op Rs1 Rd

6. Jump / Call Rd  (Rs1) Op (Imm) J name Jump PC6…31 name JAL name Jump and link Regs[R31]  PC + 4; PC6…31 name 6 Jump / Call 31 26 0 25 target Op

7. 7 Implementing MIPS:Single-cycle per instructiondatapath & control logic

8. 8 RegWrite 0x4 clk Add inst<25:21> we inst<20:16> rs1 rs2 addr PC inst<15:11> rd1 inst ALU ws z wd rd2 Inst. Memory clk GPRs inst<5:0> ALU Control OpCode 6 5 5 5 5 6 0 rs rt rd 0 func rd  (rs) func (rt) 31 26 25 21 20 16 15 11 5 0 Datapath: Reg-Reg ALU Instructions RegWrite Timing?

9. 9 RegWrite 0x4 clk Add we inst<25:21> rs1 rs2 addr rd1 PC inst<20:16> inst ws ALU wd rd2 z Inst. Memory GPRs clk inst<15:0> Imm Ext inst<31:26> ALU Control ExtSel OpCode 6 5 5 16 opcode rs rt immediate rt  (rs) op immediate 31 26 25 2120 16 15 0 Datapath: Reg-Imm ALU Instructions

10. 10 clk we rs1 rs2 addr rd1 PC inst ws ALU wd rd2 z Inst. Memory GPRs Imm Ext ExtSel 6 5 5 5 5 6 0 rs rt rd 0 func rd  (rs) func (rt) opcode rs rt immediate rt  (rs) op immediate Conflicts in Merging Datapath RegWrite Introduce muxes 0x4 Add inst<25:21> inst<20:16> inst<15:11> clk inst<15:0> inst<31:26> ALU Control inst<5:0> OpCode

11. 11 clk we rs1 rs2 addr rd1 PC inst ws ALU wd rd2 z Inst. Memory GPRs 6 5 5 5 5 6 0 rs rt rd 0 func rd  (rs) func (rt) opcode rs rt immediate rt  (rs) op immediate Datapath for ALU Instructions RegWrite 0x4 Add <25:21> <20:16> <15:11> clk <15:0> Imm Ext <31:26>, <5:0> ALU Control BSrc Reg / Imm ExtSel OpSel RegDst rt / rd OpCode

14. Note: A Load or Store instruction requires accessing the memory more than once during its execution

15. 13 RegWrite MemWrite WBSrc ALU / Mem 0x4 clk Add we “base” clk rs1 rs2 we rd1 ws addr ALU addr PC wd rd2 z inst GPRs rdata Data Memory clk Inst. Memory disp Imm Ext wdata ALU Control RegDst ExtSel OpCode OpSel BSrc 6 5 5 16 addressing mode opcode rs rt displacement (rs) + displacement 31 26 25 21 20 16 15 0 Load/Store Instructions:Harvard Datapath rs is the base register rt is the destination of a Load or the source for a Store

16. 14 CSE 490/590 Administrivia Please purchase a BASYS2 board (100K) as soon as possible. Projects should be done individually. Quiz 1 Fri, 2/4 Closed book, in-class 10% Class cancelled on Fri, 4/15 Will update the schedule

18. Absolute jumps append target4 to PC<31:28> to calculate the target address: 256 MB range

20. 17 WBSrc MemWrite rind 0x4 clk we clk rs1 rs2 ALU Control we rd1 addr PC ws addr inst wd rd2 ALU GPRs z rdata Inst. Memory clk Data Memory Imm Ext wdata zero? RegDst ExtSel OpCode OpSel BSrc Register-Indirect Jumps (JR) PCSrc RegWrite br pc+4 Add Add

21. 18 0x4 clk we rs1 rs2 ALU Control rd1 addr PC ws inst wd rd2 ALU GPRs z Inst. Memory clk Imm Ext zero? RegDst ExtSel OpCode OpSel BSrc Register-Indirect Jump-&-Link (JALR) PCSrc RegWrite WBSrc MemWrite br rind pc+4 Add Add clk 31 we addr rdata Data Memory wdata

22. 19 WBSrc MemWrite 0x4 clk ALU Control we addr PC addr inst ALU rdata Inst. Memory clk Data Memory Imm Ext wdata Absolute Jumps (J, JAL) PCSrc RegWrite br rind jabs pc+4 Add Add clk we rs1 rs2 31 rd1 ws wd rd2 GPRs z zero? RegDst ExtSel OpCode OpSel BSrc

23. 20 WBSrc MemWrite 0x4 clk we clk rs1 rs2 ALU Control we rd1 addr PC ws addr inst wd rd2 ALU GPRs z rdata Inst. Memory clk Data Memory Imm Ext wdata zero? RegDst ExtSel OpCode OpSel BSrc Harvard-Style Datapath for MIPS PCSrc RegWrite br rind jabs pc+4 Add Add 31

25. 22 Pipelined MIPS

27. No sharing of resources between any two stages

28. Propagation delay through all pipeline stages is equal

29. The scheduling of an object entering the pipeline is not affected by the objects in other stages These conditions generally hold for industrial assembly lines. But can an instruction pipeline satisfy the last condition?

30. 24 Pipelined MIPS To pipeline MIPS: First build MIPS without pipelining with CPI=1 Next, add pipeline registers to reduce cycle time while maintaining CPI=1

31. 25 PC IR write -back phase fetch phase execute phase decode & Reg-fetch phase memory phase Pipelined Datapath 0x4 Add we rs1 rs2 rd1 we addr ws addr rdata ALU wd rd2 rdata GPRs Data Memory Inst. Memory Imm Ext wdata Clock period can be reduced by dividing the execution of an instruction into multiple cycles tC > max {tIM, tRF, tALU, tDM, tRW} ( = tDM probably) However, CPI will increase unless instructions are pipelined

33. Cycles per instructions (CPI) depends upon the ISA and the microarchitecture

36. Multiported Register files (slower!)Thus, the following timing assumption is reasonable tIMtRF tALUtDM tRW A 5-stage pipeline will be the focus of our detailed design - some commercial designs have over 30 pipeline stages to do an integer add!

37. 29 Acknowledgements These slides heavily contain material developed and copyright by KrsteAsanovic (MIT/UCB) David Patterson (UCB) And also by: Arvind (MIT) Joel Emer (Intel/MIT) James Hoe (CMU) John Kubiatowicz (UCB) MIT material derived from course 6.823 UCB material derived from course CS252