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1. JAGADEESH TALLURU
Email id: jagadish2990@gmail.com
Mobile Number: 9739893639
Career Objective:
Willing to work as a Physical Design Engineer in a VLSI company and looking forward to
take up challenging assignments in the related field of industry and to set new industry
benchmarks in everything I endeavour.
Core Competency:
 Excellent knowledge of IC Fabrication process.
 Good exposure to technology by undergoing additional training in VLSI
 Good understanding of the inputs and outputs of all the stages in the physical design
(Floor Planning, Placement, CTS, Routing, Physical Verification & DFM).
 Efficient in high count macro placement during floor-planning.
 Well versed in understanding and resolving timing violation.
 Hands on experience on Physical Verification like DRC, LVS using Caliber.
 Understanding of Reliability issues like EM, X-talk, and Antenna.
 Good understanding of fundamentals of Transistors and circuit theory.
 Good knowledge of Digital Design Concepts.
 Good knowledge of Verilog RTL coding.
 Good working knowledge of Linux, and C programming.
Projects:
Company: RV-VLSI Design centre
Title: Physical Design Flow for Torpedo Sub block
Duration: 6 Months
Role Physical Design Engineer Trainee
Description: Torpedo sub block is a project which incorporates 32 macros, 43275
standard cells with supply voltage of 1.85V working at a frequency
of 400MHz. It used a total of 5 clocks (3 propagated and 2
generated clock). Number of Metal Layers: 6, Fab: jazz
Semiconductor, 180 nm technology node is used.
Tools Used : ICC, Prime Time from Synopsys and Caliber from Mentor
Graphics.
Deliverable/Challenges
Faced:
Placed and Routed, Timing closure, DRC & LVS clean Block.
Creating floor-plan within available core area, Placement of macro
to meet the Area, Power and Timing constraints, Freezing the
number of Straps, width to get IR Drop (VDD+VSS) less than 5%
of 1.8

2. Work Experience:
Organization: JBT Food Tech, Pune
Designation: Operational Support Engineer
Duration of Project in
Mar 2012 to Oct 2013
Months:
Organization: RV-VLSI Design Centre
Designation: Physical Design Engineer Trainee
Duration of Project in
Nov 2013 to June 2014
Months:
Education :
 Completed PG Diploma in VLSI from RV-VLSI Design Centre, Bangalore.
 B.E., in Electronics and Communication Engineering from Vel Multi Tech
Engineering College affiliated to Anna University with First Class.
Co-Curricular Activities & Achievements:
 Worked as coordinator for the department, National level Technical Symposium
SCADZ’10
 Attended Workshop which was conducted by CYPRESS SEMICONDUCTORS in
Anna University.
 Won first place in 100meters running during zonal sports in the year 2003-2004
 Acted as School people leader in Rayalaseema high school in the year 2004.

 Won first place in Long jump during Zonal sports in the year2003-2004.
Personal Profile:
Name :JAGADEESH TALLURU
Date of Birth : 19/July/1990
Address :1-33/2,srinivasa puram,Tiruchanoor Road, ,Tirupati - 517503
Father Name : T Subbarao
Nationality : INDIAN
Sex : Male
Languages known : English, Telugu, Hindi, Tamil