Vlsi physical design

2013-5-13 1www.i-world-tech.blogspot.in
Department of Information Technology
School Of Technology, Assam University Silchar
Presented By
Deepak Gupta (31320025)
B.Tech (IT) 6th Sem
Assam University , Silchar
Guided By
Mr. A. K. Khan
Assistant Professor
Dept. of Information Technology

1. Introduction
2. VLSI Design Cycle
3. Physical Design
4. Physical Design Style
5. Physical Packaging Style
6. Physical Design Cycle
(A). Partitioning
(B). Floor Plan And Placement
(C). Routing
(D). Layout Optimization
(E). Extraction And Verification
7. Summary
8. Bibliography

 The VLSI ( Very Large Scale Integration ) Circuits is The
Collection of More Over 1 Million Small Chips Integrated on it.
 They are Initially Partitioned or Designed in Small Scale or
as Independent Module .
 After Designing and Testing Each Modules They are
Fabricated in a Single Chip To Form A Large Chip.
 That Large Chip is Known as VLSI Circuits.

System
Specification
Architectural
design
Functional
Design
Logic Design
Circuit
Design
Physical
Design
Fabrication
Packing and
Testing

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 Input :- A Net List of Gates (or blocks) and Their interconnections .
 Output :- A Geometrical Layout of the Net List Within an Area
Constraint .
 Goals :- Minimize Signal Delays, interconnection Area, Power
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In The Physical Design of VLSI ( Very Large Scale Integrated ) Circuits ,
The Logical Structure of a Circuit is Transformed into its Physical Layout.

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Circuit Partitioning
Floor Planning And Placement
Routing
Layout Optimization
Extraction And Verification

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 The Process of Decomposing a Circuit into Smaller Sub-Circuits,
Which are Called block, is Known as Partitioning.
 Objective :
1. The Size of Each Component is Within Prescribed Ranges
2. The Number of Connections between The Components is
Minimized .
 Good Partitioning :
1. Improve Circuit Performance ( Speeds up The Design
Process )
2. Reduce Layout Costs.

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 Three Types of Partitioning Levels.
1. System Level Partitioning
2. Board Level Partitioning
3. Chip Level Partitioning
A System is Partitioned into a Set of Sub Systems
Where by Each Sub System can be Designed and
Fabricated Independently on a PCB or MCM.

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If PCB is Too Large
 The Circuit Assigned To a PCB is Partitioned into Sub Circuits
Such That Each Sub Circuit Can be Fabricated as a VLSI Chip.
If Chip is Too Large
 The Circuit assigned to a Chip is Partitioned into Smaller Sub
Circuits.

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 Among All Algorithms , Group Migration Algorithm has been
The Most Successful heuristics For Partitioning Problems.
 Group Migration Algorithms belong To Class of Iterative
Improvement Algorithms.
1. These Algorithms Start With Some Initial Partitions
Usually Generated Randomly.
2. Local Changes are Then Applied To The Partition to
Reduce The Cut Size.
3. This Process is Repeated until no Further Improvement
is Achieved.

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 Time Complexity :
 The Partition Sizes have To be Specified before Partitioning.
 Let G(V,E) be a Graph
Where , V=Set of Nodes and E=Set of Edges
 This Algorithm Attempts To Find a Partition of V into Two Disjoint Subsets
A and B of Equal Size, Such That The Sum T of The Weights of The Edges
between Nodes in A and B is minimized .

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 Let L(a) be The Internal Cost of a ( The Sum of The Costs of Edges between a
and other Nodes in A ).
 Let E(a) be The External Cost of a ( The Sum of The Costs of Edges between a
and Nodes in B ).
D(a)=E(a)-L(a) Difference b/w External and Internal costs of a.
If a and b are Interchanged , Then The Reduction in Cost is
T(old)-T(new)=D(a)-D(b)-2C(a,b)
Where , C(a,b)=Cost of The Possible Edge between a and b.
 The Algorithm Attempts To Find an Optimal Series of Interchange Operations
between Elements of A and B Which Maximizes T(old)-T(new) and Then Executes
The Operations , Producing a Partition of The Graph To A and B

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Step-1. Function Kernighan-Lin (G(V,E))
Step-2. Determine a balanced initial Partition of The Nodes
into Sets A and B
Step-3. do
Step-4. A1 := A; B1 := B
Step-5. Compute D Values For All a in A1 and b in B1
Step-6. For (i := 1 to |V|/2)
Step-7. Find a[i] From A1 and b[i] From B1, Such That
g[i] = D[a[i]] + D[b[i]] - 2*c[a[i]][b[i]] is Maximal
Step-8. Move a[i] to B1 and b[i] to A1

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Step-9. Remove a[i] and b[i] From Further Consideration in
This Pass
Step-10. Update D Values For The Elements of A1 = A1 /
a[i] and B1 = B1 / b[i]
Step-11. End for
Step-12. Find k Which Maximizes g_max, The Sum of
g[1],...,g[k]
Step-13. if (g_max > 0) Then
Step-14. Exchange a[1],a[2],...,a[k] With b[1],b[2],...,b[k]
Step-15. Until (g_max <= 0)
Step-16. Return G(V,E)

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 Floor Planning :
Determination of The Approximate Location of Each
Module in a Rectangular Chip Area.
 Placement :
When Each Module is Fixed , That is , has Fixed Shape
and Fixed Terminals , is The Determination of The best
Position For Each Module.
 Good Floor Planning and Placement Algorithm :
1. Making The Subsequent Routing Phase Easy
2. Minimizing The Total Chip Area
3. Reducing Signal Delays.

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 Input : 1. A Set of blocks , both Fixed and Flexible
2. Pin Location of Fixed blocks
3. A Net List
 Requirement : 1. Find Location For Each block so That no Two
blocks Overlap
2. Determine Shapes of Flexible blocks
 Objectives : 1. Minimize Area
2. Reduce Net-Length For Critical Nets

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Rectangular Dual-Graph Approach
 Hierarchical Approach
 Simulated Annealing

 Output of The Partitioning Algorithm Represented by a
Graph.
 Floor Plan can be obtained by Converting The Graph into its
Rectangular dual.
 The Rectangular dual of a Graph satisfies The Following
Properties :
1. Each Vertex Corresponds To a distinct Rectangle.
2. For Every Edge, The Corresponding Rectangles are
Adjacent.

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 The Process of Finding The Geometric Layouts (horizontal
and vertical) of all The Nets is Called Routing.
 Routing :
1. Global Routing
2. Detailed Routing
 Minimize :
Area (Channel Width)
Wire Delays
Number of Layers
Cost of Implementation

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 Global Routing :
Decomposes a Large Routing Problem into Small ,
Manageable Problems For Detailed Routing .
 Method :
First Partitions The Routing Region into a Collection of
Disjoint Rectilinear Sub Regions.
 Detailed Routing :
Follows The Global Routing To Effectively Realize
Interconnections in VLSI Circuits.

 Input
 Two Vectors of The same Length to represent The Pins
on Two sides of the Channel.
 One horizontal Layer and one Vertical Layer.
 Output
 Connect Pins of The Same net Together such That There is
no Overlap Among horizontal Wires and There is no overlap
Among Vertical Wires.
 Minimize the channel width..

Given a channel instance
Solution

 Vertical Constraints determine The order in Which The intervals Should be
Assigned From Top to bottom Across The height of The Channel.

 The horizontal Constraints Determines Whether Two intervals Ii and Ij of Two
Different nets ni and nj respectively, are Assignable to The Same Track.

Problem : Given a Set of Segments (intervals) [ximin , ximax], Put non-Overlapping
Segments on The Same Track Such That The Number of Tracks is Minimal.

Example

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 Layout Optimization is a Post-Processing Step. In This Stage
The Layout is Optimized.
Ex. by Compacting The Area.
 Compaction is done by Three Ways :
(A). By Reducing space between blocks Without Violating
design space rule.
(B). By Reducing Size of Each block Without Violating Design
Size Rule.
(C). By Reducing Shape of blocks Without Violating Electrical
Characteristics of blocks.

 In This Method Compaction is done in both Dimension x-
dimension as Well as in y-dimension.
 2-D compaction is in General Much better Than Performing 1-D
Compaction.
 If 2-D Compaction, Solved Optimally, Produces Minimum Area
Layouts.

Example

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 Layout Verification is The Testing of a Layout To
Determine if It Satisfies Design and Layout Rules.
 This includes Verifying That The Layout
1. Complies With All Technology Requirement.
2. is Consistent With The Original Net List.
3. Complies With All Electrical Requirement

 Physical design is one of the Steps in the VLSI design Cycle.
 Physical design is Further divided into
Partitioning , Floor Plan and Placement , Routing ,
Compaction , Extraction and Verification.
 There are Four Major design Style :
Full Custom, Standard Cell , Gate Array , and FPGAs.
 There are Three Alternative For Packing of Chips :
PCB , MCM , and WSI.

 Comparison of Compaction Techniques in VLSI Physical Design.
By : Chetan Sharma and Shobhit Jaiswal
 VLSI Physical Design Automation
Introduction ,Partitioning , Floor-planning
By : Arnab Sarkar IIT Kharagpur
 A Genetic Algorithm for Channel Routing in VLSI Circuits
By:Jens Lienigt and K. Thulasiraman
 Simulated Annealing-Based Channel Routing on Hypercube
Computers
By: R Mall, L.M. Patnaik, and Srilata Raman

Vlsi physical design

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