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Vlsi physical design

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Vlsi physical design

  1. 1. 2013-5-13 1www.i-world-tech.blogspot.inDepartment of Information TechnologySchool Of Technology, Assam University SilcharPresented ByDeepak Gupta (31320025)B.Tech (IT) 6th SemAssam University , SilcharGuided ByMr. A. K. KhanAssistant ProfessorDept. of Information Technology
  2. 2. 2013-5-13 2www.i-world-tech.blogspot.in1. Introduction2. VLSI Design Cycle3. Physical Design4. Physical Design Style5. Physical Packaging Style6. Physical Design Cycle(A). Partitioning(B). Floor Plan And Placement(C). Routing(D). Layout Optimization(E). Extraction And Verification7. Summary8. Bibliography
  3. 3.  The VLSI ( Very Large Scale Integration ) Circuits is TheCollection of More Over 1 Million Small Chips Integrated on it.2013-5-13 3www.i-world-tech.blogspot.in They are Initially Partitioned or Designed in Small Scale oras Independent Module . After Designing and Testing Each Modules They areFabricated in a Single Chip To Form A Large Chip. That Large Chip is Known as VLSI Circuits.
  4. 4. 2013-5-13 4www.i-world-tech.blogspot.inSystemSpecificationArchitecturaldesignFunctionalDesignLogic DesignCircuitDesignPhysicalDesignFabricationPacking andTesting
  5. 5. 2013-5-13 5 Input :- A Net List of Gates (or blocks) and Their interconnections . Output :- A Geometrical Layout of the Net List Within an AreaConstraint . Goals :- Minimize Signal Delays, interconnection Area, Powerwww.i-world-tech.blogspot.inIn The Physical Design of VLSI ( Very Large Scale Integrated ) Circuits ,The Logical Structure of a Circuit is Transformed into its Physical Layout.
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  12. 12. 2013-5-13 12Circuit PartitioningFloor Planning And PlacementRoutingLayout OptimizationExtraction And Verificationwww.i-world-tech.blogspot.in
  13. 13. 2013-5-13 13 The Process of Decomposing a Circuit into Smaller Sub-Circuits,Which are Called block, is Known as Partitioning. Objective :1. The Size of Each Component is Within Prescribed Ranges2. The Number of Connections between The Components isMinimized .www.i-world-tech.blogspot.in Good Partitioning :1. Improve Circuit Performance ( Speeds up The DesignProcess )2. Reduce Layout Costs.
  14. 14. 2013-5-13 14 Three Types of Partitioning Levels.1. System Level Partitioning2. Board Level Partitioning3. Chip Level Partitioningwww.i-world-tech.blogspot.inA System is Partitioned into a Set of Sub SystemsWhere by Each Sub System can be Designed andFabricated Independently on a PCB or MCM.
  15. 15. 2013-5-13 15If PCB is Too Large The Circuit Assigned To a PCB is Partitioned into Sub CircuitsSuch That Each Sub Circuit Can be Fabricated as a VLSI Chip.www.i-world-tech.blogspot.inIf Chip is Too Large The Circuit assigned to a Chip is Partitioned into Smaller SubCircuits.
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  17. 17. 2013-5-13 17 Among All Algorithms , Group Migration Algorithm has beenThe Most Successful heuristics For Partitioning Problems. Group Migration Algorithms belong To Class of IterativeImprovement Algorithms.1. These Algorithms Start With Some Initial PartitionsUsually Generated Randomly.2. Local Changes are Then Applied To The Partition toReduce The Cut Size.3. This Process is Repeated until no Further Improvementis Achieved.www.i-world-tech.blogspot.in
  18. 18. 2013-5-13 18 Time Complexity : The Partition Sizes have To be Specified before Partitioning.www.i-world-tech.blogspot.in Let G(V,E) be a GraphWhere , V=Set of Nodes and E=Set of Edges This Algorithm Attempts To Find a Partition of V into Two Disjoint SubsetsA and B of Equal Size, Such That The Sum T of The Weights of The Edgesbetween Nodes in A and B is minimized .
  19. 19. 2013-5-13 19 Let L(a) be The Internal Cost of a ( The Sum of The Costs of Edges between aand other Nodes in A ). Let E(a) be The External Cost of a ( The Sum of The Costs of Edges between aand Nodes in B ).D(a)=E(a)-L(a) Difference b/w External and Internal costs of a.www.i-world-tech.blogspot.inIf a and b are Interchanged , Then The Reduction in Cost isT(old)-T(new)=D(a)-D(b)-2C(a,b)Where , C(a,b)=Cost of The Possible Edge between a and b. The Algorithm Attempts To Find an Optimal Series of Interchange Operationsbetween Elements of A and B Which Maximizes T(old)-T(new) and Then ExecutesThe Operations , Producing a Partition of The Graph To A and B
  20. 20. 2013-5-13 20Step-1. Function Kernighan-Lin (G(V,E))Step-2. Determine a balanced initial Partition of The Nodesinto Sets A and BStep-3. doStep-4. A1 := A; B1 := BStep-5. Compute D Values For All a in A1 and b in B1Step-6. For (i := 1 to |V|/2)Step-7. Find a[i] From A1 and b[i] From B1, Such Thatg[i] = D[a[i]] + D[b[i]] - 2*c[a[i]][b[i]] is MaximalStep-8. Move a[i] to B1 and b[i] to A1www.i-world-tech.blogspot.in
  21. 21. 2013-5-13 21Step-9. Remove a[i] and b[i] From Further Consideration inThis PassStep-10. Update D Values For The Elements of A1 = A1 /a[i] and B1 = B1 / b[i]Step-11. End forStep-12. Find k Which Maximizes g_max, The Sum ofg[1],...,g[k]Step-13. if (g_max > 0) ThenStep-14. Exchange a[1],a[2],...,a[k] With b[1],b[2],...,b[k]Step-15. Until (g_max <= 0)Step-16. Return G(V,E)www.i-world-tech.blogspot.in
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  23. 23. 2013-5-13 23 Floor Planning :Determination of The Approximate Location of EachModule in a Rectangular Chip Area. Placement :When Each Module is Fixed , That is , has Fixed Shapeand Fixed Terminals , is The Determination of The bestPosition For Each Module. Good Floor Planning and Placement Algorithm :1. Making The Subsequent Routing Phase Easy2. Minimizing The Total Chip Area3. Reducing Signal Delays.www.i-world-tech.blogspot.in
  24. 24. 2013-5-13 24 Input : 1. A Set of blocks , both Fixed and Flexible2. Pin Location of Fixed blocks3. A Net List Requirement : 1. Find Location For Each block so That no Twoblocks Overlap2. Determine Shapes of Flexible blocks Objectives : 1. Minimize Area2. Reduce Net-Length For Critical Netswww.i-world-tech.blogspot.in
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  26. 26. 2013-5-13 26Rectangular Dual-Graph Approach Hierarchical Approach Simulated Annealingwww.i-world-tech.blogspot.in
  27. 27. 2013-5-13 27www.i-world-tech.blogspot.in Output of The Partitioning Algorithm Represented by aGraph. Floor Plan can be obtained by Converting The Graph into itsRectangular dual. The Rectangular dual of a Graph satisfies The FollowingProperties :1. Each Vertex Corresponds To a distinct Rectangle.2. For Every Edge, The Corresponding Rectangles areAdjacent.
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  29. 29. 2013-5-13 29 The Process of Finding The Geometric Layouts (horizontaland vertical) of all The Nets is Called Routing. Routing :1. Global Routing2. Detailed Routingwww.i-world-tech.blogspot.in Minimize :Area (Channel Width)Wire DelaysNumber of LayersCost of Implementation
  30. 30. 2013-5-13 30 Global Routing :Decomposes a Large Routing Problem into Small ,Manageable Problems For Detailed Routing . Method :First Partitions The Routing Region into a Collection ofDisjoint Rectilinear Sub Regions.www.i-world-tech.blogspot.in Detailed Routing :Follows The Global Routing To Effectively RealizeInterconnections in VLSI Circuits.
  31. 31. 2013-5-13 31www.i-world-tech.blogspot.in Input Two Vectors of The same Length to represent The Pinson Two sides of the Channel. One horizontal Layer and one Vertical Layer. Output Connect Pins of The Same net Together such That There isno Overlap Among horizontal Wires and There is no overlapAmong Vertical Wires. Minimize the channel width..
  32. 32. 2013-5-13 32www.i-world-tech.blogspot.inGiven a channel instanceSolution
  33. 33. 2013-5-13 33www.i-world-tech.blogspot.in Vertical Constraints determine The order in Which The intervals Should beAssigned From Top to bottom Across The height of The Channel.
  34. 34. 2013-5-13 34www.i-world-tech.blogspot.in The horizontal Constraints Determines Whether Two intervals Ii and Ij of TwoDifferent nets ni and nj respectively, are Assignable to The Same Track.
  35. 35. 2013-5-13 35www.i-world-tech.blogspot.inProblem : Given a Set of Segments (intervals) [ximin , ximax], Put non-OverlappingSegments on The Same Track Such That The Number of Tracks is Minimal.
  36. 36. 2013-5-13 36www.i-world-tech.blogspot.inExample
  37. 37. 2013-5-13 37 Layout Optimization is a Post-Processing Step. In This StageThe Layout is Optimized.Ex. by Compacting The Area.www.i-world-tech.blogspot.in Compaction is done by Three Ways :(A). By Reducing space between blocks Without Violatingdesign space rule.(B). By Reducing Size of Each block Without Violating DesignSize Rule.(C). By Reducing Shape of blocks Without Violating ElectricalCharacteristics of blocks.
  38. 38. 2013-5-13 38www.i-world-tech.blogspot.in
  39. 39. 2013-5-13 39www.i-world-tech.blogspot.in In This Method Compaction is done in both Dimension x-dimension as Well as in y-dimension. 2-D compaction is in General Much better Than Performing 1-DCompaction. If 2-D Compaction, Solved Optimally, Produces Minimum AreaLayouts.
  40. 40. 2013-5-13 40www.i-world-tech.blogspot.inExample
  41. 41. 2013-5-13 41 Layout Verification is The Testing of a Layout ToDetermine if It Satisfies Design and Layout Rules. This includes Verifying That The Layout1. Complies With All Technology Requirement.2. is Consistent With The Original Net List.3. Complies With All Electrical Requirementwww.i-world-tech.blogspot.in
  42. 42. 2013-5-13 42www.i-world-tech.blogspot.in Physical design is one of the Steps in the VLSI design Cycle. Physical design is Further divided intoPartitioning , Floor Plan and Placement , Routing ,Compaction , Extraction and Verification. There are Four Major design Style :Full Custom, Standard Cell , Gate Array , and FPGAs. There are Three Alternative For Packing of Chips :PCB , MCM , and WSI.
  43. 43. 2013-5-13 43www.i-world-tech.blogspot.in Comparison of Compaction Techniques in VLSI Physical Design.By : Chetan Sharma and Shobhit Jaiswal VLSI Physical Design AutomationIntroduction ,Partitioning , Floor-planningBy : Arnab Sarkar IIT Kharagpur A Genetic Algorithm for Channel Routing in VLSI CircuitsBy:Jens Lienigt and K. Thulasiraman Simulated Annealing-Based Channel Routing on HypercubeComputersBy: R Mall, L.M. Patnaik, and Srilata Raman
  44. 44. 2013-5-13 44www.i-world-tech.blogspot.in

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