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Debugging Xilinx Zynq Project using ILA Integrated Logic Analyzer IP Block

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Vincent Claes
Vincent Claes

Tutorial (step-by-step guide) on howto integrate a Xilinx ILA IP block in a Zynq design. This tutorial uses a Minized board.

Tecnología
1 de 69
Hardware Debugging on Xilinx Zynq Devices (MiniZED board) Vincent Claes
Hardware Debugging • ILA IP • Integrated Logic Analyzer • Monitor the internal signals of a design • Includes advanced features of modern logic analyzers • Boolean trigger equations, edge transition triggers • For instance used for debugging AXI interface • https://www.xilinx.com/products/intellectual-property/ila.html Vincent Claes
Create new Vivado project Vincent Claes
Create new Vivado project Vincent Claes
Create new Vivado project Vincent Claes
Create new Vivado project Vincent Claes
Create new Vivado Project Vincent Claes
Create new Vivado project Vincent Claes
Create new Vivado project Vincent Claes
Create new Vivado project Vincent Claes
Create new Block Design Vincent Claes
Create new Block Design Vincent Claes
Create new block design • Add IP Vincent Claes
Create new block design • Add ZYNQ7 Processing System Vincent Claes
Create new block design • Add IP Vincent Claes
Create new block design • Add AXI GPIO IP Vincent Claes
Create new block design • Run Block Automation Vincent Claes
Change ZYNQ7 Processing System Parameters Vincent Claes
Change ZYNQ7 Processing System Parameters • Add Master AXI Interface • Add PS-PL Cross Trigger Interface • CPU0 DBG REQ • Enables PL Cross trigger signal 0 to PS CPU Debug Request Event • CPU0 DBG ACK • Enables PS CPU Debug Acknowledgement event to PL cross trigger event • https://www.xilinx.com/html_docs/xilinx2018_2/SDK_Doc/SDK_concepts/concept_cross_triggeri ng.html • https://www.xilinx.com/html_docs/xilinx2018_2/SDK_Doc/SDK_references/reference_cross- trigerring-zynq.html • https://www.xilinx.com/html_docs/xilinx2018_2/SDK_Doc/SDK_concepts/concept_cross_trigerri ng_zynq_fpgatocputriggering.html Vincent Claes
Change ZYNQ7 Processing System Parameters Vincent Claes
Run Connection Automation Vincent Claes
Run Connection Automation Vincent Claes
Block Diagram Overview Vincent Claes
Select AXI Interface to Debug Vincent Claes
Run Connection Automation Vincent Claes
Connection Automation Settings Vincent Claes
Change AXI GPIO Settings Vincent Claes
Change AXI GPIO Settings Vincent Claes
Change AXI GPIO Settings Vincent Claes
Change System ILA Settings Vincent Claes
Change System ILA Settings Vincent Claes
Change System ILA Settings Vincent Claes
Make gpio_io_o[3:0] connection to ILA Vincent Claes
Make gpio_io_o[3:0] connection to ILA Vincent Claes
Run Connection Automation Vincent Claes
Connection Automation Settings Vincent Claes
Final Block Design Review Vincent Claes
Create HDL Wrapper Vincent Claes
Let Vivado manage wrapper and auto-update Vincent Claes
Change ILA Settings Vincent Claes • Change ILA Settings, to reduce amount of BRAM slices
Generate Bitstream Vincent Claes
Generate Bitstream Vincent Claes
Open Hardware Manager Vincent Claes
Open Hardware Manager > Open Target Vincent Claes
Open Hardware Manager > Program Device Vincent Claes
Open Hardware Manager > Program Device Vincent Claes
Export Hardware from Vivado Vincent Claes
Launch Xilinx SDK Vincent Claes
Create new Xilinx Application Project Vincent Claes
Create new Xilinx Application Project Vincent Claes
Create new Xilinx Application Project Vincent Claes
Create new Xilinx Application Project Vincent Claes
Change C Code Vincent Claes • C Code that uses the AXI GPIO IP block • Code is on Github account
Change Debug Configuration Vincent Claes
Change Debug Configuration Vincent Claes
Create Cross Trigger Breakpoints Vincent Claes
Create Cross Trigger Breakpoints CPU0 => FTM Vincent Claes
Create Cross Trigger Breakpoints CPU0 => FTM Vincent Claes
Create Cross Trigger Breakpoints FTM => CPU-0 Vincent Claes
Create Cross Trigger Breakpoints Vincent Claes
Start Software Debug Session Vincent Claes
Start Software Debug Session Vincent Claes
Start Software Debug Session Vincent Claes
Open Vivado Hardware Manager > Debug Probes Vincent Claes
Open Vivado Hardware Manager > Debug Probes Vincent Claes
Open Vivado Vincent Claes
Open Vivado Trigger Setup > Add Probe Vincent Claes
Your Integrated Logic Analyzer is ready to use Vincent Claes
More information • vincent[at]cteq.eu • https://www.linkedin.com/in/vincentclaes/ • You can contact me for IoT, Embedded Systems (HW, SW, FPGA, ARM, …) and ML/AI Projects (R and Python) • https://github.com/pxltech Vincent Claes

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