Computer Architecture notes

1. Single Cycle CPU
Jason Mars
Tuesday, February 5, 13

2. The Big Picture: The Performance Perspective
Execute an
entire instruction
Tuesday, February 5, 13

3. The Big Picture: The Performance Perspective
• Processor design (datapath and control) will determine:
• Clock cycle time
• Clock cycles per instruction
Execute an
entire instruction
Tuesday, February 5, 13

4. The Big Picture: The Performance Perspective
• Processor design (datapath and control) will determine:
• Clock cycle time
• Clock cycles per instruction
• Starting today:
• Single cycle processor:
• Advantage: One clock cycle per instruction
• Disadvantage: long cycle time
Execute an
entire instruction
Tuesday, February 5, 13

5. The Big Picture: The Performance Perspective
• Processor design (datapath and control) will determine:
• Clock cycle time
• Clock cycles per instruction
• Starting today:
• Single cycle processor:
• Advantage: One clock cycle per instruction
• Disadvantage: long cycle time
• ET = Insts * CPI * Cyc Time
Execute an
entire instruction
Tuesday, February 5, 13

6. Processor Datapath and Control
Tuesday, February 5, 13

7. Processor Datapath and Control
• We're ready to look at an implementation of the MIPS simplified to contain
only:
• memory-reference instructions: lw, sw
• arithmetic-logical instructions: add, sub, and, or, slt
• control flow instructions: beq
Tuesday, February 5, 13

8. Processor Datapath and Control
• We're ready to look at an implementation of the MIPS simplified to contain
only:
• memory-reference instructions: lw, sw
• arithmetic-logical instructions: add, sub, and, or, slt
• control flow instructions: beq
• Generic Implementation:
• use the program counter (PC) to supply instruction address
• get the instruction from memory
• read registers
• use the instruction to decide exactly what to do
Tuesday, February 5, 13

9. Processor Datapath and Control
• We're ready to look at an implementation of the MIPS simplified to contain
only:
• memory-reference instructions: lw, sw
• arithmetic-logical instructions: add, sub, and, or, slt
• control flow instructions: beq
• Generic Implementation:
• use the program counter (PC) to supply instruction address
• get the instruction from memory
• read registers
• use the instruction to decide exactly what to do
• All instructions use the ALU after reading the registers
• memory-reference? arithmetic? control flow?
Tuesday, February 5, 13

10. Review: MIPS Instruction Formats
• All instructions 32-bits long
• 3 Formats:
opcode target
opcode rs rt rd shift
amount
funct
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
6 bits 5 bits 5 bits 16 bits
6 bits 26 bits
I-Type
J-Type
R-Type
Tuesday, February 5, 13

11. The MIPS Subset
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
opcode rs rt rd shift
amount
funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
Tuesday, February 5, 13

12. The MIPS Subset
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
opcode rs rt rd shift
amount
funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
• R-Type
• add rd, rs, rt
• sub, and, or, slt
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
Tuesday, February 5, 13

13. The MIPS Subset
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
opcode rs rt rd shift
amount
funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
• R-Type
• add rd, rs, rt
• sub, and, or, slt
• LOAD and STORE
• lw rt, rs, imm16
• sw rt, rs, imm16
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
Tuesday, February 5, 13

14. The MIPS Subset
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
opcode rs rt rd shift
amount
funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
• R-Type
• add rd, rs, rt
• sub, and, or, slt
• LOAD and STORE
• lw rt, rs, imm16
• sw rt, rs, imm16
• BRANCH:
• beq rs, rt, imm16 opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
Tuesday, February 5, 13

15. Basic Steps of Execution
Tuesday, February 5, 13

16. Basic Steps of Execution
• Instruction Fetch
• Where is the instruction?
Tuesday, February 5, 13

17. Basic Steps of Execution
• Instruction Fetch
• Where is the instruction?
• Decode
• What’s the incoming instruction?
• Where are the operands in an instruction?
Tuesday, February 5, 13

18. Basic Steps of Execution
• Instruction Fetch
• Where is the instruction?
• Decode
• What’s the incoming instruction?
• Where are the operands in an instruction?
• Execution: ALU
• What is the function that ALU should perform?
Tuesday, February 5, 13

19. Basic Steps of Execution
• Instruction Fetch
• Where is the instruction?
• Decode
• What’s the incoming instruction?
• Where are the operands in an instruction?
• Execution: ALU
• What is the function that ALU should perform?
• Memory access
• Where is my data?
Tuesday, February 5, 13

20. Basic Steps of Execution
• Instruction Fetch
• Where is the instruction?
• Decode
• What’s the incoming instruction?
• Where are the operands in an instruction?
• Execution: ALU
• What is the function that ALU should perform?
• Memory access
• Where is my data?
• Write back results to registers
• Where to write?
Tuesday, February 5, 13

21. Basic Steps of Execution
• Instruction Fetch
• Where is the instruction?
• Decode
• What’s the incoming instruction?
• Where are the operands in an instruction?
• Execution: ALU
• What is the function that ALU should perform?
• Memory access
• Where is my data?
• Write back results to registers
• Where to write?
• Determine the next PC
Tuesday, February 5, 13

22. Basic Steps of Execution
• Instruction Fetch
• Where is the instruction?
• Decode
• What’s the incoming instruction?
• Where are the operands in an instruction?
• Execution: ALU
• What is the function that ALU should perform?
• Memory access
• Where is my data?
• Write back results to registers
• Where to write?
• Determine the next PC
Instruction memory
address: PC
Tuesday, February 5, 13

23. Basic Steps of Execution
• Instruction Fetch
• Where is the instruction?
• Decode
• What’s the incoming instruction?
• Where are the operands in an instruction?
• Execution: ALU
• What is the function that ALU should perform?
• Memory access
• Where is my data?
• Write back results to registers
• Where to write?
• Determine the next PC
Instruction memory
address: PC
register file
Tuesday, February 5, 13

24. Basic Steps of Execution
• Instruction Fetch
• Where is the instruction?
• Decode
• What’s the incoming instruction?
• Where are the operands in an instruction?
• Execution: ALU
• What is the function that ALU should perform?
• Memory access
• Where is my data?
• Write back results to registers
• Where to write?
• Determine the next PC
Instruction memory
address: PC
register file
ALU
Tuesday, February 5, 13

25. Basic Steps of Execution
• Instruction Fetch
• Where is the instruction?
• Decode
• What’s the incoming instruction?
• Where are the operands in an instruction?
• Execution: ALU
• What is the function that ALU should perform?
• Memory access
• Where is my data?
• Write back results to registers
• Where to write?
• Determine the next PC
Instruction memory
address: PC
register file
ALU
Data memory
address: effective address
Tuesday, February 5, 13

26. Basic Steps of Execution
• Instruction Fetch
• Where is the instruction?
• Decode
• What’s the incoming instruction?
• Where are the operands in an instruction?
• Execution: ALU
• What is the function that ALU should perform?
• Memory access
• Where is my data?
• Write back results to registers
• Where to write?
• Determine the next PC
Instruction memory
address: PC
register file
ALU
Data memory
address: effective address
register file
Tuesday, February 5, 13

27. Basic Steps of Execution
• Instruction Fetch
• Where is the instruction?
• Decode
• What’s the incoming instruction?
• Where are the operands in an instruction?
• Execution: ALU
• What is the function that ALU should perform?
• Memory access
• Where is my data?
• Write back results to registers
• Where to write?
• Determine the next PC
Instruction memory
address: PC
register file
ALU
Data memory
address: effective address
register file
program counter
Tuesday, February 5, 13

28. Where We’re Going...
Tuesday, February 5, 13

29. Where We’re Going...
Instruction memory
address: PC
Tuesday, February 5, 13

30. Where We’re Going...
Instruction memory
address: PC
register file
Tuesday, February 5, 13

31. Where We’re Going...
Instruction memory
address: PC
register file
ALU
Tuesday, February 5, 13

32. Where We’re Going...
Instruction memory
address: PC
register file
ALU
Data memory
address: effective address
Tuesday, February 5, 13

33. Where We’re Going...
Instruction memory
address: PC
register file
ALU
Data memory
address: effective address
program counter
Tuesday, February 5, 13

34. Review: Two Type of Logical Components
Tuesday, February 5, 13

35. Review: Two Type of Logical Components
Combinational
Logic
A
B
C = f(A,B)
Tuesday, February 5, 13

36. Review: Two Type of Logical Components
State
Element
clk
A
B
C = f(A,B,state)
Combinational
Logic
A
B
C = f(A,B)
Tuesday, February 5, 13

37. Clocking Methodology
• All storage elements are clocked by the same clock edge
Clk
Don t Care
Setup Hold
.
.
.
.
.
.
.
.
.
.
.
.
Setup Hold
Tuesday, February 5, 13

38. Storage Element: The Register
• Register
• Similar to the D Flip Flop except
• N-bit input and output
• Write Enable input
• Write Enable:
• 0: Data Out will not change
• 1: Data Out will become Data In (on the clock edge)
Clk
Data In
Write Enable
N N
Data Out
Tuesday, February 5, 13

39. Storage Element: Register File
Clk
Write Data
RegWrite
32
32
Read Data 1
32
Read Data 2
32 32-bit
Registers
5
5
5
RR1
RR2
WR
Tuesday, February 5, 13

40. Storage Element: Register File
• Register File consists of (32) registers:
Clk
Write Data
RegWrite
32
32
Read Data 1
32
Read Data 2
32 32-bit
Registers
5
5
5
RR1
RR2
WR
Tuesday, February 5, 13

41. Storage Element: Register File
• Register File consists of (32) registers:
• Two 32-bit output buses
Clk
Write Data
RegWrite
32
32
Read Data 1
32
Read Data 2
32 32-bit
Registers
5
5
5
RR1
RR2
WR
Tuesday, February 5, 13

42. Storage Element: Register File
• Register File consists of (32) registers:
• Two 32-bit output buses
• One 32-bit input bus
Clk
Write Data
RegWrite
32
32
Read Data 1
32
Read Data 2
32 32-bit
Registers
5
5
5
RR1
RR2
WR
Tuesday, February 5, 13

43. Storage Element: Register File
• Register File consists of (32) registers:
• Two 32-bit output buses
• One 32-bit input bus
• Register is selected by:
Clk
Write Data
RegWrite
32
32
Read Data 1
32
Read Data 2
32 32-bit
Registers
5
5
5
RR1
RR2
WR
Tuesday, February 5, 13

44. Storage Element: Register File
• Register File consists of (32) registers:
• Two 32-bit output buses
• One 32-bit input bus
• Register is selected by:
• RR1 selects the register to put on
bus “Read Data 1”
Clk
Write Data
RegWrite
32
32
Read Data 1
32
Read Data 2
32 32-bit
Registers
5
5
5
RR1
RR2
WR
Tuesday, February 5, 13

45. Storage Element: Register File
• Register File consists of (32) registers:
• Two 32-bit output buses
• One 32-bit input bus
• Register is selected by:
• RR1 selects the register to put on
bus “Read Data 1”
• RR2 selects the register to put on
bus “Read Data 2”
Clk
Write Data
RegWrite
32
32
Read Data 1
32
Read Data 2
32 32-bit
Registers
5
5
5
RR1
RR2
WR
Tuesday, February 5, 13

46. Storage Element: Register File
• Register File consists of (32) registers:
• Two 32-bit output buses
• One 32-bit input bus
• Register is selected by:
• RR1 selects the register to put on
bus “Read Data 1”
• RR2 selects the register to put on
bus “Read Data 2”
• WR selects the register to be
written
Clk
Write Data
RegWrite
32
32
Read Data 1
32
Read Data 2
32 32-bit
Registers
5
5
5
RR1
RR2
WR
Tuesday, February 5, 13

47. Storage Element: Register File
• Register File consists of (32) registers:
• Two 32-bit output buses
• One 32-bit input bus
• Register is selected by:
• RR1 selects the register to put on
bus “Read Data 1”
• RR2 selects the register to put on
bus “Read Data 2”
• WR selects the register to be
written
• via WriteData when RegWrite is 1
Clk
Write Data
RegWrite
32
32
Read Data 1
32
Read Data 2
32 32-bit
Registers
5
5
5
RR1
RR2
WR
Tuesday, February 5, 13

48. Storage Element: Register File
• Register File consists of (32) registers:
• Two 32-bit output buses
• One 32-bit input bus
• Register is selected by:
• RR1 selects the register to put on
bus “Read Data 1”
• RR2 selects the register to put on
bus “Read Data 2”
• WR selects the register to be
written
• via WriteData when RegWrite is 1
• Clock input (CLK)
Clk
Write Data
RegWrite
32
32
Read Data 1
32
Read Data 2
32 32-bit
Registers
5
5
5
RR1
RR2
WR
Tuesday, February 5, 13

49. Inside the Register File
• The implementation of two read ports register file
• n registers
• done with a pair of n-to-1 multiplexors, each 32 bits wide.
FIGURE C.8.7 A register file with two read ports and one write port has five inputs and
two outputs. The control input Write is shown in color.
FIGURE C.8.8 The implementation of two read ports for a register file with n registers
can be done with a pair of n-to-1 multiplexors, each 32 bits wide. The register read number
signal is used as the multiplexor selector signal. Figure C.8.9 shows how the write port is implemented.
Writedata
Read register
number 1
Register 0
Register 1
. . .
Register n – 2
Register n – 1
M
u
x
Read register
number 2
M
u
x
Read data 1
Read data 2
AppendixC-9780123747501.indd 55AppendixC-9780123747501.indd 55 26/07/11 6:29 PM26/07/11 6:29 PM
Tuesday, February 5, 13

50. Storage Element: Memory
Clk
Write Data
MemWrite
32 32
Read Data
Address
MemRead
Tuesday, February 5, 13

51. Storage Element: Memory
• Memory
Clk
Write Data
MemWrite
32 32
Read Data
Address
MemRead
Tuesday, February 5, 13

52. Storage Element: Memory
• Memory
• Two input buses: WriteData, Address
Clk
Write Data
MemWrite
32 32
Read Data
Address
MemRead
Tuesday, February 5, 13

53. Storage Element: Memory
• Memory
• Two input buses: WriteData, Address
• One output bus: ReadData
Clk
Write Data
MemWrite
32 32
Read Data
Address
MemRead
Tuesday, February 5, 13

54. Storage Element: Memory
• Memory
• Two input buses: WriteData, Address
• One output bus: ReadData
• Memory word is selected by:
Clk
Write Data
MemWrite
32 32
Read Data
Address
MemRead
Tuesday, February 5, 13

55. Storage Element: Memory
• Memory
• Two input buses: WriteData, Address
• One output bus: ReadData
• Memory word is selected by:
• Address selects the word to put on ReadData
bus
Clk
Write Data
MemWrite
32 32
Read Data
Address
MemRead
Tuesday, February 5, 13

56. Storage Element: Memory
• Memory
• Two input buses: WriteData, Address
• One output bus: ReadData
• Memory word is selected by:
• Address selects the word to put on ReadData
bus
• If MemWrite = 1: address selects the memory
word to be written via the WriteData bus Clk
Write Data
MemWrite
32 32
Read Data
Address
MemRead
Tuesday, February 5, 13

57. Storage Element: Memory
• Memory
• Two input buses: WriteData, Address
• One output bus: ReadData
• Memory word is selected by:
• Address selects the word to put on ReadData
bus
• If MemWrite = 1: address selects the memory
word to be written via the WriteData bus
• Clock input (CLK)
Clk
Write Data
MemWrite
32 32
Read Data
Address
MemRead
Tuesday, February 5, 13

58. Storage Element: Memory
• Memory
• Two input buses: WriteData, Address
• One output bus: ReadData
• Memory word is selected by:
• Address selects the word to put on ReadData
bus
• If MemWrite = 1: address selects the memory
word to be written via the WriteData bus
• Clock input (CLK)
• The CLK input is a factor ONLY during write
operation
Clk
Write Data
MemWrite
32 32
Read Data
Address
MemRead
Tuesday, February 5, 13

59. Storage Element: Memory
• Memory
• Two input buses: WriteData, Address
• One output bus: ReadData
• Memory word is selected by:
• Address selects the word to put on ReadData
bus
• If MemWrite = 1: address selects the memory
word to be written via the WriteData bus
• Clock input (CLK)
• The CLK input is a factor ONLY during write
operation
• During read operation, behaves as a
combinational logic block:
Clk
Write Data
MemWrite
32 32
Read Data
Address
MemRead
Tuesday, February 5, 13

60. Storage Element: Memory
• Memory
• Two input buses: WriteData, Address
• One output bus: ReadData
• Memory word is selected by:
• Address selects the word to put on ReadData
bus
• If MemWrite = 1: address selects the memory
word to be written via the WriteData bus
• Clock input (CLK)
• The CLK input is a factor ONLY during write
operation
• During read operation, behaves as a
combinational logic block:
• Address valid => ReadData valid after
“access time.”
Clk
Write Data
MemWrite
32 32
Read Data
Address
MemRead
Tuesday, February 5, 13

61. RTL: Register Transfer Language
• Describes the movement and manipulation of data between storage
elements:
R[3] <- R[5] + R[7]
PC <- PC + 4 + R[5]
R[rd] <- R[rs] + R[rt]
R[rt] <- Mem[R[rs] + immed]
Tuesday, February 5, 13

62. Instruction Fetch and Program Counter
Management
Tuesday, February 5, 13

63. Overview of the Instruction Fetch Unit
• The common RTL operations
• Fetch the Instruction: inst <- mem[PC]
• Update the program counter:
• Sequential Code: PC <- PC + 4
• Branch and Jump PC <- “something else”
Tuesday, February 5, 13

64. Datapath for Register-Register Operations
opcode rs rt rd shift
amount
funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
Tuesday, February 5, 13

65. Datapath for Register-Register Operations
• R[rd] <- R[rs] op R[rt] Example: add rd, rs, rt
opcode rs rt rd shift
amount
funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
Tuesday, February 5, 13

66. Datapath for Register-Register Operations
• R[rd] <- R[rs] op R[rt] Example: add rd, rs, rt
• RR1, RR2, and WR comes from instruction’s rs, rt, and rd fields
opcode rs rt rd shift
amount
funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
Tuesday, February 5, 13

67. Datapath for Register-Register Operations
• R[rd] <- R[rs] op R[rt] Example: add rd, rs, rt
• RR1, RR2, and WR comes from instruction’s rs, rt, and rd fields
• ALUoperation and RegWrite: control logic after decoding instruction
opcode rs rt rd shift
amount
funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
Tuesday, February 5, 13

68. Control Logic??288 Chapter 5 The Processor: Datapath and Control
FIGURE 5.2 The basic implementation of the MIPS subset including the necessary multiplexors and control
Data
Register #
Register #
Register #
PC Address Instruction
Instruction
memory
Registers ALU Address
Data
Data
memory
AddAdd
4
MemWrite
MemRead
M
u
x
M
u
x
M
u
x
Control
RegWrite
Zero
Branch
ALU operation
Tuesday, February 5, 13

69. Control Logic??288 Chapter 5 The Processor: Datapath and Control
FIGURE 5.2 The basic implementation of the MIPS subset including the necessary multiplexors and control
Data
Register #
Register #
Register #
PC Address Instruction
Instruction
memory
Registers ALU Address
Data
Data
memory
AddAdd
4
MemWrite
MemRead
M
u
x
M
u
x
M
u
x
Control
RegWrite
Zero
Branch
ALU operation
Tuesday, February 5, 13

70. Datapath for Load Operations
• R[rt] <- Mem[R[rs] + SignExt[imm16]] Example: lw rt, rs, imm16
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
Tuesday, February 5, 13

71. Datapath for Load Operations
• R[rt] <- Mem[R[rs] + SignExt[imm16]] Example: lw rt, rs, imm16
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
Tuesday, February 5, 13

72. Datapath for Load Operations
• R[rt] <- Mem[R[rs] + SignExt[imm16]] Example: lw rt, rs, imm16
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
Tuesday, February 5, 13

73. Datapath for Load Operations
• R[rt] <- Mem[R[rs] + SignExt[imm16]] Example: lw rt, rs, imm16
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
Tuesday, February 5, 13

74. Datapath for Load Operations
• R[rt] <- Mem[R[rs] + SignExt[imm16]] Example: lw rt, rs, imm16
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
Tuesday, February 5, 13

75. Datapath for Load Operations
• R[rt] <- Mem[R[rs] + SignExt[imm16]] Example: lw rt, rs, imm16
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
Tuesday, February 5, 13

76. Datapath for Load Operations
• R[rt] <- Mem[R[rs] + SignExt[imm16]] Example: lw rt, rs, imm16
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
Tuesday, February 5, 13

77. Datapath for Load Operations
• R[rt] <- Mem[R[rs] + SignExt[imm16]] Example: lw rt, rs, imm16
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
Tuesday, February 5, 13

78. Datapath for Load Operations
• R[rt] <- Mem[R[rs] + SignExt[imm16]] Example: lw rt, rs, imm16
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
Tuesday, February 5, 13

79. Datapath for Store Operations
• Mem[R[rs] + SignExt[imm16]] <- R[rt] Example: sw rt, rs, imm16
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
Tuesday, February 5, 13

80. Datapath for Store Operations
• Mem[R[rs] + SignExt[imm16]] <- R[rt] Example: sw rt, rs, imm16
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
Tuesday, February 5, 13

81. Datapath for Store Operations
• Mem[R[rs] + SignExt[imm16]] <- R[rt] Example: sw rt, rs, imm16
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
Tuesday, February 5, 13

82. Datapath for Store Operations
• Mem[R[rs] + SignExt[imm16]] <- R[rt] Example: sw rt, rs, imm16
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
Tuesday, February 5, 13

83. Datapath for Store Operations
• Mem[R[rs] + SignExt[imm16]] <- R[rt] Example: sw rt, rs, imm16
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
Tuesday, February 5, 13

84. Datapath for Store Operations
• Mem[R[rs] + SignExt[imm16]] <- R[rt] Example: sw rt, rs, imm16
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
Tuesday, February 5, 13

85. Datapath for Store Operations
• Mem[R[rs] + SignExt[imm16]] <- R[rt] Example: sw rt, rs, imm16
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
Tuesday, February 5, 13

86. Datapath for Branch Operations
• Z <- (rs == rt); if Z, PC = PC+4+imm16; else PC = PC+4
• beq rs, rt, imm16
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
Tuesday, February 5, 13

87. Datapath for Branch Operations
• Z <- (rs == rt); if Z, PC = PC+4+imm16; else PC = PC+4
• beq rs, rt, imm16
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
Tuesday, February 5, 13

88. Datapath for Branch Operations
• Z <- (rs == rt); if Z, PC = PC+4+imm16; else PC = PC+4
• beq rs, rt, imm16
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
Tuesday, February 5, 13

89. Datapath for Branch Operations
• Z <- (rs == rt); if Z, PC = PC+4+imm16; else PC = PC+4
• beq rs, rt, imm16
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
Tuesday, February 5, 13

90. Datapath for Branch Operations
• Z <- (rs == rt); if Z, PC = PC+4+imm16; else PC = PC+4
• beq rs, rt, imm16
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
Tuesday, February 5, 13

91. Datapath for Branch Operations
• Z <- (rs == rt); if Z, PC = PC+4+imm16; else PC = PC+4
• beq rs, rt, imm16
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
Tuesday, February 5, 13

92. Datapath for Branch Operations
• Z <- (rs == rt); if Z, PC = PC+4+imm16; else PC = PC+4
• beq rs, rt, imm16
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
Tuesday, February 5, 13

93. Datapath for Branch Operations
• Z <- (rs == rt); if Z, PC = PC+4+imm16; else PC = PC+4
• beq rs, rt, imm16
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
Tuesday, February 5, 13

94. Datapath for Branch Operations
• Z <- (rs == rt); if Z, PC = PC+4+imm16; else PC = PC+4
• beq rs, rt, imm16
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
Tuesday, February 5, 13

95. Datapath for Branch Operations
• Z <- (rs == rt); if Z, PC = PC+4+imm16; else PC = PC+4
• beq rs, rt, imm16
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
Tuesday, February 5, 13

96. Datapath for Branch Operations
• Z <- (rs == rt); if Z, PC = PC+4+imm16; else PC = PC+4
• beq rs, rt, imm16
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
Tuesday, February 5, 13

97. Datapath for Branch Operations
• Z <- (rs == rt); if Z, PC = PC+4+imm16; else PC = PC+4
• beq rs, rt, imm16
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
Tuesday, February 5, 13

98. Datapath for Branch Operations
• Z <- (rs == rt); if Z, PC = PC+4+imm16; else PC = PC+4
• beq rs, rt, imm16
opcode rs rt immediate / offset
6 bits 5 bits 5 bits 16 bits
Tuesday, February 5, 13

99. Control Logic??288 Chapter 5 The Processor: Datapath and Control
FIGURE 5.2 The basic implementation of the MIPS subset including the necessary multiplexors and control
Data
Register #
Register #
Register #
PC Address Instruction
Instruction
memory
Registers ALU Address
Data
Data
memory
AddAdd
4
MemWrite
MemRead
M
u
x
M
u
x
M
u
x
Control
RegWrite
Zero
Branch
ALU operation
Tuesday, February 5, 13

100. Control Logic??288 Chapter 5 The Processor: Datapath and Control
FIGURE 5.2 The basic implementation of the MIPS subset including the necessary multiplexors and control
Data
Register #
Register #
Register #
PC Address Instruction
Instruction
memory
Registers ALU Address
Data
Data
memory
AddAdd
4
MemWrite
MemRead
M
u
x
M
u
x
M
u
x
Control
RegWrite
Zero
Branch
ALU operation
Tuesday, February 5, 13

101. Binary Arithmetic for the Next Address
Tuesday, February 5, 13

102. Binary Arithmetic for the Next Address
• In theory, the PC is a 32-bit byte address into the instruction memory:
• Sequential operation: PC<31:0> = PC<31:0> + 4
• Branch operation: PC<31:0> = PC<31:0> + 4 + SignExt[Imm16] * 4
Tuesday, February 5, 13

103. Binary Arithmetic for the Next Address
• In theory, the PC is a 32-bit byte address into the instruction memory:
• Sequential operation: PC<31:0> = PC<31:0> + 4
• Branch operation: PC<31:0> = PC<31:0> + 4 + SignExt[Imm16] * 4
• The magic number “4” always comes up because:
• The 32-bit PC is a byte address
• And all our instructions are 4 bytes (32 bits) long
• The 2 LSBs of the 32-bit PC are always zeros
• There is no reason to have hardware to keep the 2 LSBs
Tuesday, February 5, 13

104. Binary Arithmetic for the Next Address
• In theory, the PC is a 32-bit byte address into the instruction memory:
• Sequential operation: PC<31:0> = PC<31:0> + 4
• Branch operation: PC<31:0> = PC<31:0> + 4 + SignExt[Imm16] * 4
• The magic number “4” always comes up because:
• The 32-bit PC is a byte address
• And all our instructions are 4 bytes (32 bits) long
• The 2 LSBs of the 32-bit PC are always zeros
• There is no reason to have hardware to keep the 2 LSBs
• In practice, we can simplify the hardware by using a 30-bit PC<31:2>:
• Sequential operation: PC<31:2> = PC<31:2> + 1
• Branch operation: PC<31:2> = PC<31:2> + 1 + SignExt[Imm16]
• In either case: Instruction Memory Address = PC<31:2> concat “00”
Tuesday, February 5, 13

105. Putting it All Together: A Single Cycle Datapath
• We have everything except control signals
Tuesday, February 5, 13

106. GAME: GUESS THE FUNCTION!!
• We have everything except control signals
Tuesday, February 5, 13

107. GAME: GUESS THE FUNCTION!!
• We have everything except control signals
Tuesday, February 5, 13

108. GAME: GUESS THE FUNCTION!!
• We have everything except control signals
Tuesday, February 5, 13

109. GAME: GUESS THE FUNCTION!!
• We have everything except control signals
Tuesday, February 5, 13

110. GAME: GUESS THE FUNCTION!!
• We have everything except control signals
Tuesday, February 5, 13

111. GAME: GUESS THE FUNCTION!!
• We have everything except control signals
Tuesday, February 5, 13

112. GAME: GUESS THE FUNCTION!!
• We have everything except control signals
Tuesday, February 5, 13

113. GAME: GUESS THE FUNCTION!!
• We have everything except control signals
Tuesday, February 5, 13

114. The R-Format (e.g. add) Datapath
Tuesday, February 5, 13

115. The R-Format (e.g. add) Datapath
Tuesday, February 5, 13

116. The R-Format (e.g. add) Datapath
Tuesday, February 5, 13

117. The R-Format (e.g. add) Datapath
Tuesday, February 5, 13

118. The R-Format (e.g. add) Datapath
Tuesday, February 5, 13

119. The R-Format (e.g. add) Datapath
Tuesday, February 5, 13

120. The R-Format (e.g. add) Datapath
Tuesday, February 5, 13

121. The R-Format (e.g. add) Datapath
Tuesday, February 5, 13

122. The R-Format (e.g. add) Datapath
Tuesday, February 5, 13

123. The R-Format (e.g. add) Datapath
Tuesday, February 5, 13

124. The R-Format (e.g. add) Datapath
Tuesday, February 5, 13

125. The R-Format (e.g. add) Datapath
Tuesday, February 5, 13

126. The Load Datapath
Tuesday, February 5, 13

127. The Load Datapath
Tuesday, February 5, 13

128. The Load Datapath
Tuesday, February 5, 13

129. The Load Datapath
Tuesday, February 5, 13

130. The Load Datapath
Tuesday, February 5, 13

131. The Load Datapath
Tuesday, February 5, 13

132. The Load Datapath
Tuesday, February 5, 13

133. The Load Datapath
Tuesday, February 5, 13

134. The Load Datapath
Tuesday, February 5, 13

135. The Load Datapath
Tuesday, February 5, 13

136. The Load Datapath
Tuesday, February 5, 13

137. The Store Datapath
Tuesday, February 5, 13

138. The Store Datapath
Tuesday, February 5, 13

139. The Store Datapath
Tuesday, February 5, 13

140. The Store Datapath
Tuesday, February 5, 13

141. The Store Datapath
Tuesday, February 5, 13

142. The Store Datapath
Tuesday, February 5, 13

143. The Store Datapath
Tuesday, February 5, 13

144. The Store Datapath
Tuesday, February 5, 13

145. The Store Datapath
Tuesday, February 5, 13

146. The Branch (beq) Datapath
Tuesday, February 5, 13

147. The Branch (beq) Datapath
Tuesday, February 5, 13

148. The Branch (beq) Datapath
Tuesday, February 5, 13

149. The Branch (beq) Datapath
Tuesday, February 5, 13

150. The Branch (beq) Datapath
Tuesday, February 5, 13

151. The Branch (beq) Datapath
Tuesday, February 5, 13

152. The Branch (beq) Datapath
Tuesday, February 5, 13

153. The Branch (beq) Datapath
Tuesday, February 5, 13

154. The Branch (beq) Datapath
Tuesday, February 5, 13

155. The Branch (beq) Datapath
Tuesday, February 5, 13

156. The Branch (beq) Datapath
Tuesday, February 5, 13

157. The Branch (beq) Datapath
Tuesday, February 5, 13

158. The Branch (beq) Datapath
Tuesday, February 5, 13

159. The Branch (beq) Datapath
Tuesday, February 5, 13

160. GAME: GUESS THE FUNCTION!! (Review)
• We have everything except control signals
Tuesday, February 5, 13

161. GAME: GUESS THE FUNCTION!! (Review)
• We have everything except control signals
Tuesday, February 5, 13

162. GAME: GUESS THE FUNCTION!! (Review)
• We have everything except control signals
Tuesday, February 5, 13

163. GAME: GUESS THE FUNCTION!! (Review)
• We have everything except control signals
Tuesday, February 5, 13

164. GAME: GUESS THE FUNCTION!! (Review)
• We have everything except control signals
Tuesday, February 5, 13

165. GAME: GUESS THE FUNCTION!! (Review)
• We have everything except control signals
Tuesday, February 5, 13

166. GAME: GUESS THE FUNCTION!! (Review)
• We have everything except control signals
Tuesday, February 5, 13

167. GAME: GUESS THE FUNCTION!! (Review)
• We have everything except control signals
Tuesday, February 5, 13

168. Key Points
Tuesday, February 5, 13

169. Key Points
• CPU is just a collection of state and combinational logic
Tuesday, February 5, 13

170. Key Points
• CPU is just a collection of state and combinational logic
• We just designed a very rich processor, at least in terms of functionality
Tuesday, February 5, 13

171. Key Points
• CPU is just a collection of state and combinational logic
• We just designed a very rich processor, at least in terms of functionality
• ET = IC * CPI * Cycle Time
• where does the single-cycle machine fit in?
Tuesday, February 5, 13

172. The Control Unit
Tuesday, February 5, 13

173. Putting it All Together: A Single Cycle Datapath
• We have everything except control signals
Tuesday, February 5, 13

174. Putting it All Together: A Single Cycle Datapath
Tuesday, February 5, 13

175. Putting it All Together: A Single Cycle Datapath
Tuesday, February 5, 13

176. Putting it All Together: A Single Cycle Datapath
Tuesday, February 5, 13

177. ALU Control Bits
• 5-Function ALU
• Note: book also has NOR, not used - and a forth bit, not used
ALU control input Function Operations
000 And and
001 Or or
010 Add add, lw, sw
110 Subtract sub, beq
111 Slt slt
Tuesday, February 5, 13

178. Full ALU
what signals accomplish:
Binvert CIn Oper
add?
sub?
and?
or?
beq?
slt?
ALU
a
ALU operation
b
CarryOut
Zero
Result
Overflow
FIGURE C.5.14 The symbol commonly used to represent an ALU,
C.5.12. This symbol is also used to represent an adder, so it is normally labeled eit
C.5 Constructing a Basic A
Tuesday, February 5, 13

179. Full ALU
what signals accomplish:
Binvert CIn Oper
add?
sub?
and?
or?
beq?
slt?
0 0 10
ALU
a
ALU operation
b
CarryOut
Zero
Result
Overflow
FIGURE C.5.14 The symbol commonly used to represent an ALU,
C.5.12. This symbol is also used to represent an adder, so it is normally labeled eit
C.5 Constructing a Basic A
Tuesday, February 5, 13

180. Full ALU
what signals accomplish:
Binvert CIn Oper
add?
sub?
and?
or?
beq?
slt?
0 0 10
1 1 10
ALU
a
ALU operation
b
CarryOut
Zero
Result
Overflow
FIGURE C.5.14 The symbol commonly used to represent an ALU,
C.5.12. This symbol is also used to represent an adder, so it is normally labeled eit
C.5 Constructing a Basic A
Tuesday, February 5, 13

181. Full ALU
what signals accomplish:
Binvert CIn Oper
add?
sub?
and?
or?
beq?
slt?
0 0 10
1 1 10
0 0 00
ALU
a
ALU operation
b
CarryOut
Zero
Result
Overflow
FIGURE C.5.14 The symbol commonly used to represent an ALU,
C.5.12. This symbol is also used to represent an adder, so it is normally labeled eit
C.5 Constructing a Basic A
Tuesday, February 5, 13

182. Full ALU
what signals accomplish:
Binvert CIn Oper
add?
sub?
and?
or?
beq?
slt?
0 0 10
1 1 10
0 0 00
0 0 01
ALU
a
ALU operation
b
CarryOut
Zero
Result
Overflow
FIGURE C.5.14 The symbol commonly used to represent an ALU,
C.5.12. This symbol is also used to represent an adder, so it is normally labeled eit
C.5 Constructing a Basic A
Tuesday, February 5, 13

183. Full ALU
what signals accomplish:
Binvert CIn Oper
add?
sub?
and?
or?
beq?
slt?
0 0 10
1 1 10
0 0 00
0 0 01
1 1 10
ALU
a
ALU operation
b
CarryOut
Zero
Result
Overflow
FIGURE C.5.14 The symbol commonly used to represent an ALU,
C.5.12. This symbol is also used to represent an adder, so it is normally labeled eit
C.5 Constructing a Basic A
Tuesday, February 5, 13

184. Full ALU
what signals accomplish:
Binvert CIn Oper
add?
sub?
and?
or?
beq?
slt?
0 0 10
1 1 10
0 0 00
0 0 01
1 1 10
1 1 11
ALU
a
ALU operation
b
CarryOut
Zero
Result
Overflow
FIGURE C.5.14 The symbol commonly used to represent an ALU,
C.5.12. This symbol is also used to represent an adder, so it is normally labeled eit
C.5 Constructing a Basic A
Tuesday, February 5, 13

185. ALU Control Bits
• 5-Function ALU
• Based on opcode (bits 31-26) and function code (bits 5-0) from instruction
• ALU doesn’t need to know all opcodes--we will summarize opcode with
ALUOp (2 bits):
00 - lw,sw
01 - beq
10 - R-format
ALU control input Function Operations
000 And and
001 Or or
010 Add add, lw, sw
110 Subtract sub, beq
111 Slt slt
Main
Control
op
6
ALU
Control
func
2
6
ALUop
ALUctr
3
Tuesday, February 5, 13

186. Generating ALU Control
Instruction
opcode
ALUOp Instruction
operation
Function
code
Desired
ALU
action
ALU
control
input
lw 00 load word xxxxxx add 010
sw 00 store word xxxxxx add 010
beq 01 branch eq xxxxxx subtract 110
R-type 10 add 100000 add 010
R-type 10 subtract 100010 subtract 110
R-type 10 AND 100100 and 000
R-type 10 OR 100101 or 001
R-type 10 slt 101010 slt 111
ALU
Control
Logic
Tuesday, February 5, 13

187. Controlling the CPU
Instruction RegDst ALUSrc
Memto-
Reg
Reg
Write
Mem
Read
Mem
Write Branch ALUOp1 ALUp0
R-format 1 0
lw 0 0
sw 0 0
beq 0 1
Tuesday, February 5, 13

188. Controlling the CPU
Instruction RegDst ALUSrc
Memto-
Reg
Reg
Write
Mem
Read
Mem
Write Branch ALUOp1 ALUp0
R-format 1 0
lw 0 0
sw 0 0
beq 0 1
1
Tuesday, February 5, 13

189. Controlling the CPU
Instruction RegDst ALUSrc
Memto-
Reg
Reg
Write
Mem
Read
Mem
Write Branch ALUOp1 ALUp0
R-format 1 0
lw 0 0
sw 0 0
beq 0 1
1 0
Tuesday, February 5, 13

190. Controlling the CPU
Instruction RegDst ALUSrc
Memto-
Reg
Reg
Write
Mem
Read
Mem
Write Branch ALUOp1 ALUp0
R-format 1 0
lw 0 0
sw 0 0
beq 0 1
1 0 0
Tuesday, February 5, 13

191. Controlling the CPU
Instruction RegDst ALUSrc
Memto-
Reg
Reg
Write
Mem
Read
Mem
Write Branch ALUOp1 ALUp0
R-format 1 0
lw 0 0
sw 0 0
beq 0 1
1 0 0 1
Tuesday, February 5, 13

192. Controlling the CPU
Instruction RegDst ALUSrc
Memto-
Reg
Reg
Write
Mem
Read
Mem
Write Branch ALUOp1 ALUp0
R-format 1 0
lw 0 0
sw 0 0
beq 0 1
1 0 0 1 0
Tuesday, February 5, 13

193. Controlling the CPU
Instruction RegDst ALUSrc
Memto-
Reg
Reg
Write
Mem
Read
Mem
Write Branch ALUOp1 ALUp0
R-format 1 0
lw 0 0
sw 0 0
beq 0 1
1 0 0 1 0 0
Tuesday, February 5, 13

194. Controlling the CPU
Instruction RegDst ALUSrc
Memto-
Reg
Reg
Write
Mem
Read
Mem
Write Branch ALUOp1 ALUp0
R-format 1 0
lw 0 0
sw 0 0
beq 0 1
1 0 0 1 0 0 0
Tuesday, February 5, 13

195. Controlling the CPU
Instruction RegDst ALUSrc
Memto-
Reg
Reg
Write
Mem
Read
Mem
Write Branch ALUOp1 ALUp0
R-format 1 0
lw 0 0
sw 0 0
beq 0 1
1 0 0 1 0 0 0
0
Tuesday, February 5, 13

196. Controlling the CPU
Instruction RegDst ALUSrc
Memto-
Reg
Reg
Write
Mem
Read
Mem
Write Branch ALUOp1 ALUp0
R-format 1 0
lw 0 0
sw 0 0
beq 0 1
1 0 0 1 0 0 0
0 1
Tuesday, February 5, 13

197. Controlling the CPU
Instruction RegDst ALUSrc
Memto-
Reg
Reg
Write
Mem
Read
Mem
Write Branch ALUOp1 ALUp0
R-format 1 0
lw 0 0
sw 0 0
beq 0 1
1 0 0 1 0 0 0
0 1 1
Tuesday, February 5, 13

198. Controlling the CPU
Instruction RegDst ALUSrc
Memto-
Reg
Reg
Write
Mem
Read
Mem
Write Branch ALUOp1 ALUp0
R-format 1 0
lw 0 0
sw 0 0
beq 0 1
1 0 0 1 0 0 0
0 1 1 1
Tuesday, February 5, 13

199. Controlling the CPU
Instruction RegDst ALUSrc
Memto-
Reg
Reg
Write
Mem
Read
Mem
Write Branch ALUOp1 ALUp0
R-format 1 0
lw 0 0
sw 0 0
beq 0 1
1 0 0 1 0 0 0
0 1 1 1 1
Tuesday, February 5, 13

200. Controlling the CPU
Instruction RegDst ALUSrc
Memto-
Reg
Reg
Write
Mem
Read
Mem
Write Branch ALUOp1 ALUp0
R-format 1 0
lw 0 0
sw 0 0
beq 0 1
1 0 0 1 0 0 0
0 1 1 1 1 0
Tuesday, February 5, 13

201. Controlling the CPU
Instruction RegDst ALUSrc
Memto-
Reg
Reg
Write
Mem
Read
Mem
Write Branch ALUOp1 ALUp0
R-format 1 0
lw 0 0
sw 0 0
beq 0 1
1 0 0 1 0 0 0
0 1 1 1 1 0 0
Tuesday, February 5, 13

202. Controlling the CPU
Instruction RegDst ALUSrc
Memto-
Reg
Reg
Write
Mem
Read
Mem
Write Branch ALUOp1 ALUp0
R-format 1 0
lw 0 0
sw 0 0
beq 0 1
1 0 0 1 0 0 0
0 1 1 1 1 0 0
X
Tuesday, February 5, 13

203. Controlling the CPU
Instruction RegDst ALUSrc
Memto-
Reg
Reg
Write
Mem
Read
Mem
Write Branch ALUOp1 ALUp0
R-format 1 0
lw 0 0
sw 0 0
beq 0 1
1 0 0 1 0 0 0
0 1 1 1 1 0 0
X 1
Tuesday, February 5, 13

204. Controlling the CPU
Instruction RegDst ALUSrc
Memto-
Reg
Reg
Write
Mem
Read
Mem
Write Branch ALUOp1 ALUp0
R-format 1 0
lw 0 0
sw 0 0
beq 0 1
1 0 0 1 0 0 0
0 1 1 1 1 0 0
X 1 X
Tuesday, February 5, 13

205. Controlling the CPU
Instruction RegDst ALUSrc
Memto-
Reg
Reg
Write
Mem
Read
Mem
Write Branch ALUOp1 ALUp0
R-format 1 0
lw 0 0
sw 0 0
beq 0 1
1 0 0 1 0 0 0
0 1 1 1 1 0 0
X 1 X 0
Tuesday, February 5, 13

206. Controlling the CPU
Instruction RegDst ALUSrc
Memto-
Reg
Reg
Write
Mem
Read
Mem
Write Branch ALUOp1 ALUp0
R-format 1 0
lw 0 0
sw 0 0
beq 0 1
1 0 0 1 0 0 0
0 1 1 1 1 0 0
X 1 X 0 0
Tuesday, February 5, 13

207. Controlling the CPU
Instruction RegDst ALUSrc
Memto-
Reg
Reg
Write
Mem
Read
Mem
Write Branch ALUOp1 ALUp0
R-format 1 0
lw 0 0
sw 0 0
beq 0 1
1 0 0 1 0 0 0
0 1 1 1 1 0 0
X 1 X 0 0 1
Tuesday, February 5, 13

208. Controlling the CPU
Instruction RegDst ALUSrc
Memto-
Reg
Reg
Write
Mem
Read
Mem
Write Branch ALUOp1 ALUp0
R-format 1 0
lw 0 0
sw 0 0
beq 0 1
1 0 0 1 0 0 0
0 1 1 1 1 0 0
X 1 X 0 0 1 0
Tuesday, February 5, 13

209. Controlling the CPU
Instruction RegDst ALUSrc
Memto-
Reg
Reg
Write
Mem
Read
Mem
Write Branch ALUOp1 ALUp0
R-format 1 0
lw 0 0
sw 0 0
beq 0 1
1 0 0 1 0 0 0
0 1 1 1 1 0 0
X 1 X 0 0 1 0
X
Tuesday, February 5, 13

210. Controlling the CPU
Instruction RegDst ALUSrc
Memto-
Reg
Reg
Write
Mem
Read
Mem
Write Branch ALUOp1 ALUp0
R-format 1 0
lw 0 0
sw 0 0
beq 0 1
1 0 0 1 0 0 0
0 1 1 1 1 0 0
X 1 X 0 0 1 0
X 0
Tuesday, February 5, 13

211. Controlling the CPU
Instruction RegDst ALUSrc
Memto-
Reg
Reg
Write
Mem
Read
Mem
Write Branch ALUOp1 ALUp0
R-format 1 0
lw 0 0
sw 0 0
beq 0 1
1 0 0 1 0 0 0
0 1 1 1 1 0 0
X 1 X 0 0 1 0
X 0 X
Tuesday, February 5, 13

212. Controlling the CPU
Instruction RegDst ALUSrc
Memto-
Reg
Reg
Write
Mem
Read
Mem
Write Branch ALUOp1 ALUp0
R-format 1 0
lw 0 0
sw 0 0
beq 0 1
1 0 0 1 0 0 0
0 1 1 1 1 0 0
X 1 X 0 0 1 0
X 0 X 0
Tuesday, February 5, 13

213. Controlling the CPU
Instruction RegDst ALUSrc
Memto-
Reg
Reg
Write
Mem
Read
Mem
Write Branch ALUOp1 ALUp0
R-format 1 0
lw 0 0
sw 0 0
beq 0 1
1 0 0 1 0 0 0
0 1 1 1 1 0 0
X 1 X 0 0 1 0
X 0 X 0 0
Tuesday, February 5, 13

214. Controlling the CPU
Instruction RegDst ALUSrc
Memto-
Reg
Reg
Write
Mem
Read
Mem
Write Branch ALUOp1 ALUp0
R-format 1 0
lw 0 0
sw 0 0
beq 0 1
1 0 0 1 0 0 0
0 1 1 1 1 0 0
X 1 X 0 0 1 0
X 0 X 0 0 0
Tuesday, February 5, 13

215. Controlling the CPU
Instruction RegDst ALUSrc
Memto-
Reg
Reg
Write
Mem
Read
Mem
Write Branch ALUOp1 ALUp0
R-format 1 0
lw 0 0
sw 0 0
beq 0 1
1 0 0 1 0 0 0
0 1 1 1 1 0 0
X 1 X 0 0 1 0
X 0 X 0 0 0 1
Tuesday, February 5, 13

216. Control Truth Table
R-format lw sw beq
Opcode 000000 100011 101011 000100
RegDst 1 0 x x
ALUSrc 0 1 1 0
MemtoReg 0 1 x x
RegWrite 1 1 0 0
Outputs MemRead 0 1 0 0
MemWrite 0 0 1 0
Branch 0 0 0 1
ALUOp1 1 0 0 0
ALUOp0 0 0 0 1
Tuesday, February 5, 13

217. Control
• Simple Combinational Logic (truth tables)
Operation2
Operation1
Operation0
Operation
ALUOp1
F3
F2
F1
F0
F (5– 0)
ALUOp0
ALUOp
ALU control block
R-format Iw sw beq
Op0
Op1
Op2
Op3
Op4
Op5
Inputs
Outputs
RegDst
ALUSrc
MemtoReg
RegWrite
MemRead
MemWrite
Branch
ALUOp1
ALUOpO
Tuesday, February 5, 13

218. Single Cycle CPU Summary
Tuesday, February 5, 13

219. Single Cycle CPU Summary
• Easy, particularly the control
Tuesday, February 5, 13

220. Single Cycle CPU Summary
• Easy, particularly the control
• Which instruction takes the longest? By how much? Why is that a problem?
• ET = IC * CPI * CT
Tuesday, February 5, 13

221. Single Cycle CPU Summary
• Easy, particularly the control
• Which instruction takes the longest? By how much? Why is that a problem?
• ET = IC * CPI * CT
• What else can we do?
Tuesday, February 5, 13

222. Single Cycle CPU Summary
• Easy, particularly the control
• Which instruction takes the longest? By how much? Why is that a problem?
• ET = IC * CPI * CT
• What else can we do?
• When does a multi-cycle implementation make sense?
• e.g., 70% of instructions take 75 ns, 30% take 200 ns?
• suppose 20% overhead for extra latches
Tuesday, February 5, 13

223. Single Cycle CPU Summary
• Easy, particularly the control
• Which instruction takes the longest? By how much? Why is that a problem?
• ET = IC * CPI * CT
• What else can we do?
• When does a multi-cycle implementation make sense?
• e.g., 70% of instructions take 75 ns, 30% take 200 ns?
• suppose 20% overhead for extra latches
• Real machines have much more variable instruction latencies than this.
Tuesday, February 5, 13