SlideShare una empresa de Scribd logo
1 de 53
Quantum Cost Calculation of
Reversible Circuit

      Sajib Mitra
      Department of Computer Science and
      Engineering
      University of Dhaka
      sajibmitra.csedu@yahoo.com
OVERVIEW
 Reversible Logic
 Quantum Computing
 Quantum Gates
 Realization of Quantum NOT
 Quantum wire and Special Cases
 Quantum Cost Calculation of RC
 Conclusion
 Assignment
 References
Reversible Logic
    Equal number of input and output vectors
    Preserves an unique mapping between input and output
     vectors of the particular circuit
    One or more operation can implement in a single unit
     called Reversible Gate
    (N x N) Reversible Gate has N number of inputs and N
     number of outputs where N= {1, 2, 3, …}
Reversible Logic       (cont…)

  Advantage
    Recovers bit-loss as well as production of heat
    Adaptable for Quantum Computing
    Multiple operations in a single cycle
    Uses low power CMOS technology
Reversible Logic    (cont…)

  Limitation
    Feedback is strictly restricted
    Maximum and minimum Fan-out is always one
Reversible Logic       (cont…)

Most Popular reversible gates are as follows:




            Fig. 3x3 Dimensional Reversible gates
Reversible Logic       (cont…)

Most Popular reversible gates are as follows:




            Fig. 4x4 Dimensional Reversible gates
Quantum Computing
   First proposed in the 1970s, quantum computing relies on
    quantum physics by taking advantage of certain quantum
    physics properties of atoms or nuclei that allow them to work
    together as quantum bits, or qubits, to be the computer's
    processor and memory.
   Qubits can perform certain calculations exponentially faster
    than conventional computers.
   Quantum computers encode information as a series of
    quantum-mechanical states such as spin directions of
    electrons or polarization orientations of a photon that might
    represent as 0 or 1 or might represent a superposition of the
    two values.
                        q =α 0 + β 1
Quantum Computing                  (cont…)

   Quantum Computation uses matrix multiplication rather than
    conventional Boolean operations and the information
    measurement is realized using qubits rather than bits The matrix
    operations over qubits are simply specifies by using quantum
    primitives as follows:
Quantum Computing   (cont…)




  Input   Output        Input/output   Symbol
 A    B   P   Q          Pattern
 0    0   0   0               00         a
 0    1   0   1               01         b
 1    0   1   1               10         c
 1    1   1   0               11         d
Quantum Computing   (cont…)
Quantum Computing   (cont…)


                              Input   Output
                              A   B   P   Q
                              0   0   0   0
                              0   1   0   1
                              1   0   1   1
                              1   1   1   0
Quantum Gates




    Fig: Quantum Gates are used for realizing Reversible Circuit
Quantum Gates      (cont…)

   What is SRN?




                     But
Quantum Gates      (cont…)

   What is SRN?




                      But


                    NOT

                             But How?
Realization of Quantum NOT
 Basic operator for single input line:
        1. NOT
        2. Coin Flip
        3. Quantum Coin Flip
Realization of Quantum NOT   (cont…)
Realization of Quantum NOT                    (cont…)
 Probability of 0 or 1 based on Coin Flip:



                             1
                       1/2          1/2


                  0                       1
            1/2       1/2          1/2        1/2


            0          1           0           1
           1/4         1/4         1/4         1/4
Realization of Quantum NOT                   (cont…)
 Probability of 0 or 1 based on Coin Flip:



                   1
             1/2          1/2         So the Probability of
                                           P(0)=1/2
        0                       1          P(1)=1/2
  1/2       1/2           1/2       1/2


  0           1          0           1
 1/4         1/4         1/4         1/4
Realization of Quantum NOT                                 (cont…)
 Probability of |0> or |1> based on Quantum Coin Flip:


                                     |
                                     1>
                        1                 1
                            2                     2

                   |                                  |
                   0>                                 1>
          1             − 1               1                 1
               2                 2            2                     2


          |             |                 |                 |
          0>            1>                0>                1>
           1            −1                1                 1
               2             2                2                 2
Realization of Quantum NOT                                    (cont…)
 Probability of |0> or |1> based on Quantum Coin Flip:


                            |
                            1>
               1                 1
                   2                     2        So the Probability of
           |                                  |
                                                       P(|0>)=1
          0>                                 1>        P(|1>)=0
  1            − 1               1                1
      2                 2            2                    2


   |           |                  |               |
  0>           1>                0>               1>
  1            −1                1                1
      2             2                2                2
Realization of Quantum NOT           (cont…)

   NOT operation can be divided into to SRN matrix
    production


            1
                        NO               0
                         T
   Quantum Cost (QC) of any reversible circuit is the
    total number of 2x2 quantum primitives which are
    used to form equivalent quantum circuit.
Quantum Wire and Special Cases       (cont…)




       Quantum XOR gate, cost is 1
Quantum Wire and Special Cases     (cont…)




    Two Quantum XOR gates, but cost is
                  0
Quantum Wire and Special Cases   (cont…)




           Quantum Wire
Quantum Wire and Special Cases           (cont…)

Quantum Cost of V and V+ are same , equal to one.




     SRN and its Hermitian Matrix on same
                     line.
      VV+= Identity and the total cost = 0
Quantum Wire and Special Cases       (cont…)




    SRN and its Hermitian Matrix on same
                    line.
     VV+= Identity and the total cost = 0
Quantum Wire and Special Cases          (cont…)




   The attachment of SRN (Hermitian Matrix of
     SRN) and EX-OR gate on the same line
   generates symmetric gate pattern has a cost
                      of 1.
                Here T= V or V+
Quantum Wire and Special Cases                     (cont…)




    The cost of all 4x4 Unitary Matrices (b, c, d) and the
        symmetric gate pattern (e, f, g, h) are unit.
Quantum Cost of F2G
Quantum Cost of Toffoli Gate




                           But How?
Quantum Cost of Toffoli Gate


                         INPUT       OUTPUT
                         a       b     r
                         0       0     c
                         0       1     c
                         1       0     c
                         1       1     c’
Quantum Cost of Toffoli Gate

    INPUT       OUTPUT
    a       b     r
    0       0     c
    0       1     c
    1       0     c
    1       1     c’
Quantum Cost of Toffoli Gate
        INPUT       OUTPUT
    a           b      r
    0           0      c
    0           1      c
    1           0      c
    1           1      c’

    INPUT           OUTPUT
   a        b         r
    0           0     c
    0           1     c
    1           0     c
    1           1     c’
Now
Quantum Cost of Toffoli Gate

                             Input       Outpu
                                           t
                         A           B    R
                         0           0    C
                         0           1    C
                         1   Have anything wr
                                0   C
                         1           1    C’
Quantum Cost of Toffoli Gate

                               Input       Outpu
                                             t
                           A           B    R
                           0           0    C
                           0           1    C
                           1           0    C
                           1           1    C’




                      Ok
Quantum Cost of Toffoli Gate       (cont…)

Alternate representation of Quantum circuit of TG…
Quantum Cost of Fredkin Gate




                       But How?
Quantum Cost of Fredkin Gate   (cont…)
Quantum Cost of Fredkin Gate   (cont…)
Quantum Cost of Fredkin Gate   (cont…)
Quantum Cost of Fredkin Gate   (cont…)
Quantum Cost of Fredkin Gate   (cont…)
Quantum Cost of Fredkin Gate   (cont…)
Quantum Cost of Peres Gate
Quantum Cost of NFT Gate
Quantum Cost of NFT Gate
Quantum Cost of MIG Gate
Assignment




             Find out cost
About Author
               Sajib Kumar Mitra is an MS student of Dept.
               of Computer Science and Engineering,
               University of Dhaka, Dhaka, Bangladesh. His
               research interests include Electronics, Digital
               Circuit Design, Logic Design, and Reversible
               Logic Synthesis.
THANKS TO ALL

Más contenido relacionado

La actualidad más candente

Chapter 5 introduction to VHDL
Chapter 5 introduction to VHDLChapter 5 introduction to VHDL
Chapter 5 introduction to VHDLSSE_AndyLi
 
Verilog VHDL code Parallel adder
Verilog VHDL code Parallel adder Verilog VHDL code Parallel adder
Verilog VHDL code Parallel adder Bharti Airtel Ltd.
 
Phase Shift Keying & π/4 -Quadrature Phase Shift Keying
Phase Shift Keying & π/4 -Quadrature Phase Shift KeyingPhase Shift Keying & π/4 -Quadrature Phase Shift Keying
Phase Shift Keying & π/4 -Quadrature Phase Shift KeyingNaveen Jakhar, I.T.S
 
Data flow model -Lecture-4
Data flow model -Lecture-4Data flow model -Lecture-4
Data flow model -Lecture-4Dr.YNM
 
Latch & Flip-Flop.pptx
Latch & Flip-Flop.pptxLatch & Flip-Flop.pptx
Latch & Flip-Flop.pptxGargiKhanna1
 
carry look ahead adder
carry look ahead addercarry look ahead adder
carry look ahead adderASHISH MANI
 
Sequence detector Verilog Code
Sequence detector Verilog CodeSequence detector Verilog Code
Sequence detector Verilog CodeBharti Airtel Ltd.
 
halfadder & halfsubtractor using 4:1 MUX
halfadder & halfsubtractor using 4:1 MUXhalfadder & halfsubtractor using 4:1 MUX
halfadder & halfsubtractor using 4:1 MUXU Reshmi
 
Verification Engineer - Opportunities and Career Path
Verification Engineer - Opportunities and Career PathVerification Engineer - Opportunities and Career Path
Verification Engineer - Opportunities and Career PathRamdas Mozhikunnath
 
Asynchronous Sequential Circuit-Unit 4 ppt
Asynchronous Sequential Circuit-Unit 4 pptAsynchronous Sequential Circuit-Unit 4 ppt
Asynchronous Sequential Circuit-Unit 4 pptSIVALAKSHMIPANNEERSE
 
sequential circuits
sequential circuitssequential circuits
sequential circuitsUnsa Shakir
 
Overview of digital design with Verilog HDL
Overview of digital design with Verilog HDLOverview of digital design with Verilog HDL
Overview of digital design with Verilog HDLanand hd
 

La actualidad más candente (20)

Verilog lab manual (ECAD and VLSI Lab)
Verilog lab manual (ECAD and VLSI Lab)Verilog lab manual (ECAD and VLSI Lab)
Verilog lab manual (ECAD and VLSI Lab)
 
TTL(Transistor Transistor Logic)
TTL(Transistor Transistor Logic)TTL(Transistor Transistor Logic)
TTL(Transistor Transistor Logic)
 
Ripple Carry Adder
Ripple Carry AdderRipple Carry Adder
Ripple Carry Adder
 
Chapter 5 introduction to VHDL
Chapter 5 introduction to VHDLChapter 5 introduction to VHDL
Chapter 5 introduction to VHDL
 
Verilog VHDL code Parallel adder
Verilog VHDL code Parallel adder Verilog VHDL code Parallel adder
Verilog VHDL code Parallel adder
 
Phase Shift Keying & π/4 -Quadrature Phase Shift Keying
Phase Shift Keying & π/4 -Quadrature Phase Shift KeyingPhase Shift Keying & π/4 -Quadrature Phase Shift Keying
Phase Shift Keying & π/4 -Quadrature Phase Shift Keying
 
Data flow model -Lecture-4
Data flow model -Lecture-4Data flow model -Lecture-4
Data flow model -Lecture-4
 
Latch & Flip-Flop.pptx
Latch & Flip-Flop.pptxLatch & Flip-Flop.pptx
Latch & Flip-Flop.pptx
 
carry look ahead adder
carry look ahead addercarry look ahead adder
carry look ahead adder
 
Sequence detector Verilog Code
Sequence detector Verilog CodeSequence detector Verilog Code
Sequence detector Verilog Code
 
Clock distribution
Clock distributionClock distribution
Clock distribution
 
halfadder & halfsubtractor using 4:1 MUX
halfadder & halfsubtractor using 4:1 MUXhalfadder & halfsubtractor using 4:1 MUX
halfadder & halfsubtractor using 4:1 MUX
 
Verification Engineer - Opportunities and Career Path
Verification Engineer - Opportunities and Career PathVerification Engineer - Opportunities and Career Path
Verification Engineer - Opportunities and Career Path
 
Asynchronous Sequential Circuit-Unit 4 ppt
Asynchronous Sequential Circuit-Unit 4 pptAsynchronous Sequential Circuit-Unit 4 ppt
Asynchronous Sequential Circuit-Unit 4 ppt
 
sequential circuits
sequential circuitssequential circuits
sequential circuits
 
Overview of digital design with Verilog HDL
Overview of digital design with Verilog HDLOverview of digital design with Verilog HDL
Overview of digital design with Verilog HDL
 
Introduction to FPGAs
Introduction to FPGAsIntroduction to FPGAs
Introduction to FPGAs
 
Pulse modulation
Pulse modulationPulse modulation
Pulse modulation
 
Digital Communication Unit 1
Digital Communication Unit 1Digital Communication Unit 1
Digital Communication Unit 1
 
Data types in verilog
Data types in verilogData types in verilog
Data types in verilog
 

Destacado

Power Optimized ALU Design with Control-Signal Gating Technique for Efficient...
Power Optimized ALU Design with Control-Signal Gating Technique for Efficient...Power Optimized ALU Design with Control-Signal Gating Technique for Efficient...
Power Optimized ALU Design with Control-Signal Gating Technique for Efficient...Anil Yadav
 
Designing of 8 BIT Arithmetic and Logical Unit and implementing on Xilinx Ver...
Designing of 8 BIT Arithmetic and Logical Unit and implementing on Xilinx Ver...Designing of 8 BIT Arithmetic and Logical Unit and implementing on Xilinx Ver...
Designing of 8 BIT Arithmetic and Logical Unit and implementing on Xilinx Ver...Rahul Borthakur
 
Design And Implementation Of Arithmetic Logic Unit Using Modified Quasi Stati...
Design And Implementation Of Arithmetic Logic Unit Using Modified Quasi Stati...Design And Implementation Of Arithmetic Logic Unit Using Modified Quasi Stati...
Design And Implementation Of Arithmetic Logic Unit Using Modified Quasi Stati...IOSRJVSP
 
Design and implementation of low power
Design and implementation of low powerDesign and implementation of low power
Design and implementation of low powerSurendra Bommavarapu
 

Destacado (6)

Power Optimized ALU Design with Control-Signal Gating Technique for Efficient...
Power Optimized ALU Design with Control-Signal Gating Technique for Efficient...Power Optimized ALU Design with Control-Signal Gating Technique for Efficient...
Power Optimized ALU Design with Control-Signal Gating Technique for Efficient...
 
Reversible Logic Gate
Reversible Logic GateReversible Logic Gate
Reversible Logic Gate
 
Designing of 8 BIT Arithmetic and Logical Unit and implementing on Xilinx Ver...
Designing of 8 BIT Arithmetic and Logical Unit and implementing on Xilinx Ver...Designing of 8 BIT Arithmetic and Logical Unit and implementing on Xilinx Ver...
Designing of 8 BIT Arithmetic and Logical Unit and implementing on Xilinx Ver...
 
8 bit alu design
8 bit alu design8 bit alu design
8 bit alu design
 
Design And Implementation Of Arithmetic Logic Unit Using Modified Quasi Stati...
Design And Implementation Of Arithmetic Logic Unit Using Modified Quasi Stati...Design And Implementation Of Arithmetic Logic Unit Using Modified Quasi Stati...
Design And Implementation Of Arithmetic Logic Unit Using Modified Quasi Stati...
 
Design and implementation of low power
Design and implementation of low powerDesign and implementation of low power
Design and implementation of low power
 

Similar a Quantum Cost Calculation of Reversible Circuits

Monte Caro Simualtions, Sampling and Markov Chain Monte Carlo
Monte Caro Simualtions, Sampling and Markov Chain Monte CarloMonte Caro Simualtions, Sampling and Markov Chain Monte Carlo
Monte Caro Simualtions, Sampling and Markov Chain Monte CarloXin-She Yang
 
quantumComputers.ppt
quantumComputers.pptquantumComputers.ppt
quantumComputers.pptAbhayGill3
 
quantumComputers.ppt
quantumComputers.pptquantumComputers.ppt
quantumComputers.pptRaja Shekar
 
quantumComputers.ppt
quantumComputers.pptquantumComputers.ppt
quantumComputers.pptAjayRaj912848
 
quantumComputers.ppt
quantumComputers.pptquantumComputers.ppt
quantumComputers.pptraju980973
 
quantumComputers (1).ppt
quantumComputers (1).pptquantumComputers (1).ppt
quantumComputers (1).pptharithasahasra
 
quantumComputers.ppt
quantumComputers.pptquantumComputers.ppt
quantumComputers.pptTrushaKyada
 
quantumComputers.pptICICI-An HR perspective
quantumComputers.pptICICI-An HR perspectivequantumComputers.pptICICI-An HR perspective
quantumComputers.pptICICI-An HR perspectiveBenjinkumarNimmala
 
quantumComputers.ppt
quantumComputers.pptquantumComputers.ppt
quantumComputers.pptAdnan kHAN
 
hddhdhdhdhdhdhdhdhdhddhddhdhdhdhddhdhdddhdhdh
hddhdhdhdhdhdhdhdhdhddhddhdhdhdhddhdhdddhdhdhhddhdhdhdhdhdhdhdhdhddhddhdhdhdhddhdhdddhdhdh
hddhdhdhdhdhdhdhdhdhddhddhdhdhdhddhdhdddhdhdhzoobiarana76
 
Quantum Computing 101, Part 1 - Hello Quantum World
Quantum Computing 101, Part 1 - Hello Quantum WorldQuantum Computing 101, Part 1 - Hello Quantum World
Quantum Computing 101, Part 1 - Hello Quantum WorldAaronTurner9
 
Fault tolerant and online testability
Fault tolerant and online testabilityFault tolerant and online testability
Fault tolerant and online testabilitySajib Mitra
 
Hardware combinational
Hardware combinationalHardware combinational
Hardware combinationalDefri Tan
 
Quantum Computing Notes Ver 1.2
Quantum Computing Notes Ver 1.2Quantum Computing Notes Ver 1.2
Quantum Computing Notes Ver 1.2Vijayananda Mohire
 
Quantum computing - A Compilation of Concepts
Quantum computing - A Compilation of ConceptsQuantum computing - A Compilation of Concepts
Quantum computing - A Compilation of ConceptsGokul Alex
 
Minimum Cost Fault Tolerant Adder Circuits in Reversible Logic Synthesis
Minimum Cost Fault Tolerant Adder Circuits in Reversible Logic SynthesisMinimum Cost Fault Tolerant Adder Circuits in Reversible Logic Synthesis
Minimum Cost Fault Tolerant Adder Circuits in Reversible Logic SynthesisSajib Mitra
 
Viterbi Decoder Algorithm.pptx
Viterbi Decoder Algorithm.pptxViterbi Decoder Algorithm.pptx
Viterbi Decoder Algorithm.pptxChandralekhaR2
 

Similar a Quantum Cost Calculation of Reversible Circuits (20)

Monte Caro Simualtions, Sampling and Markov Chain Monte Carlo
Monte Caro Simualtions, Sampling and Markov Chain Monte CarloMonte Caro Simualtions, Sampling and Markov Chain Monte Carlo
Monte Caro Simualtions, Sampling and Markov Chain Monte Carlo
 
Quantum Computing
Quantum ComputingQuantum Computing
Quantum Computing
 
quantumComputers.ppt
quantumComputers.pptquantumComputers.ppt
quantumComputers.ppt
 
quantumComputers.ppt
quantumComputers.pptquantumComputers.ppt
quantumComputers.ppt
 
quantumComputers.ppt
quantumComputers.pptquantumComputers.ppt
quantumComputers.ppt
 
quantumComputers.ppt
quantumComputers.pptquantumComputers.ppt
quantumComputers.ppt
 
quantumComputers.ppt
quantumComputers.pptquantumComputers.ppt
quantumComputers.ppt
 
quantumComputers.ppt
quantumComputers.pptquantumComputers.ppt
quantumComputers.ppt
 
quantumComputers (1).ppt
quantumComputers (1).pptquantumComputers (1).ppt
quantumComputers (1).ppt
 
quantumComputers.ppt
quantumComputers.pptquantumComputers.ppt
quantumComputers.ppt
 
quantumComputers.pptICICI-An HR perspective
quantumComputers.pptICICI-An HR perspectivequantumComputers.pptICICI-An HR perspective
quantumComputers.pptICICI-An HR perspective
 
quantumComputers.ppt
quantumComputers.pptquantumComputers.ppt
quantumComputers.ppt
 
hddhdhdhdhdhdhdhdhdhddhddhdhdhdhddhdhdddhdhdh
hddhdhdhdhdhdhdhdhdhddhddhdhdhdhddhdhdddhdhdhhddhdhdhdhdhdhdhdhdhddhddhdhdhdhddhdhdddhdhdh
hddhdhdhdhdhdhdhdhdhddhddhdhdhdhddhdhdddhdhdh
 
Quantum Computing 101, Part 1 - Hello Quantum World
Quantum Computing 101, Part 1 - Hello Quantum WorldQuantum Computing 101, Part 1 - Hello Quantum World
Quantum Computing 101, Part 1 - Hello Quantum World
 
Fault tolerant and online testability
Fault tolerant and online testabilityFault tolerant and online testability
Fault tolerant and online testability
 
Hardware combinational
Hardware combinationalHardware combinational
Hardware combinational
 
Quantum Computing Notes Ver 1.2
Quantum Computing Notes Ver 1.2Quantum Computing Notes Ver 1.2
Quantum Computing Notes Ver 1.2
 
Quantum computing - A Compilation of Concepts
Quantum computing - A Compilation of ConceptsQuantum computing - A Compilation of Concepts
Quantum computing - A Compilation of Concepts
 
Minimum Cost Fault Tolerant Adder Circuits in Reversible Logic Synthesis
Minimum Cost Fault Tolerant Adder Circuits in Reversible Logic SynthesisMinimum Cost Fault Tolerant Adder Circuits in Reversible Logic Synthesis
Minimum Cost Fault Tolerant Adder Circuits in Reversible Logic Synthesis
 
Viterbi Decoder Algorithm.pptx
Viterbi Decoder Algorithm.pptxViterbi Decoder Algorithm.pptx
Viterbi Decoder Algorithm.pptx
 

Último

Finology Group – Insurtech Innovation Award 2024
Finology Group – Insurtech Innovation Award 2024Finology Group – Insurtech Innovation Award 2024
Finology Group – Insurtech Innovation Award 2024The Digital Insurer
 
A Domino Admins Adventures (Engage 2024)
A Domino Admins Adventures (Engage 2024)A Domino Admins Adventures (Engage 2024)
A Domino Admins Adventures (Engage 2024)Gabriella Davis
 
Scaling API-first – The story of a global engineering organization
Scaling API-first – The story of a global engineering organizationScaling API-first – The story of a global engineering organization
Scaling API-first – The story of a global engineering organizationRadu Cotescu
 
CNv6 Instructor Chapter 6 Quality of Service
CNv6 Instructor Chapter 6 Quality of ServiceCNv6 Instructor Chapter 6 Quality of Service
CNv6 Instructor Chapter 6 Quality of Servicegiselly40
 
04-2024-HHUG-Sales-and-Marketing-Alignment.pptx
04-2024-HHUG-Sales-and-Marketing-Alignment.pptx04-2024-HHUG-Sales-and-Marketing-Alignment.pptx
04-2024-HHUG-Sales-and-Marketing-Alignment.pptxHampshireHUG
 
The 7 Things I Know About Cyber Security After 25 Years | April 2024
The 7 Things I Know About Cyber Security After 25 Years | April 2024The 7 Things I Know About Cyber Security After 25 Years | April 2024
The 7 Things I Know About Cyber Security After 25 Years | April 2024Rafal Los
 
A Call to Action for Generative AI in 2024
A Call to Action for Generative AI in 2024A Call to Action for Generative AI in 2024
A Call to Action for Generative AI in 2024Results
 
Raspberry Pi 5: Challenges and Solutions in Bringing up an OpenGL/Vulkan Driv...
Raspberry Pi 5: Challenges and Solutions in Bringing up an OpenGL/Vulkan Driv...Raspberry Pi 5: Challenges and Solutions in Bringing up an OpenGL/Vulkan Driv...
Raspberry Pi 5: Challenges and Solutions in Bringing up an OpenGL/Vulkan Driv...Igalia
 
08448380779 Call Girls In Greater Kailash - I Women Seeking Men
08448380779 Call Girls In Greater Kailash - I Women Seeking Men08448380779 Call Girls In Greater Kailash - I Women Seeking Men
08448380779 Call Girls In Greater Kailash - I Women Seeking MenDelhi Call girls
 
TrustArc Webinar - Stay Ahead of US State Data Privacy Law Developments
TrustArc Webinar - Stay Ahead of US State Data Privacy Law DevelopmentsTrustArc Webinar - Stay Ahead of US State Data Privacy Law Developments
TrustArc Webinar - Stay Ahead of US State Data Privacy Law DevelopmentsTrustArc
 
Developing An App To Navigate The Roads of Brazil
Developing An App To Navigate The Roads of BrazilDeveloping An App To Navigate The Roads of Brazil
Developing An App To Navigate The Roads of BrazilV3cube
 
Mastering MySQL Database Architecture: Deep Dive into MySQL Shell and MySQL R...
Mastering MySQL Database Architecture: Deep Dive into MySQL Shell and MySQL R...Mastering MySQL Database Architecture: Deep Dive into MySQL Shell and MySQL R...
Mastering MySQL Database Architecture: Deep Dive into MySQL Shell and MySQL R...Miguel Araújo
 
Driving Behavioral Change for Information Management through Data-Driven Gree...
Driving Behavioral Change for Information Management through Data-Driven Gree...Driving Behavioral Change for Information Management through Data-Driven Gree...
Driving Behavioral Change for Information Management through Data-Driven Gree...Enterprise Knowledge
 
08448380779 Call Girls In Friends Colony Women Seeking Men
08448380779 Call Girls In Friends Colony Women Seeking Men08448380779 Call Girls In Friends Colony Women Seeking Men
08448380779 Call Girls In Friends Colony Women Seeking MenDelhi Call girls
 
Salesforce Community Group Quito, Salesforce 101
Salesforce Community Group Quito, Salesforce 101Salesforce Community Group Quito, Salesforce 101
Salesforce Community Group Quito, Salesforce 101Paola De la Torre
 
08448380779 Call Girls In Civil Lines Women Seeking Men
08448380779 Call Girls In Civil Lines Women Seeking Men08448380779 Call Girls In Civil Lines Women Seeking Men
08448380779 Call Girls In Civil Lines Women Seeking MenDelhi Call girls
 
The Codex of Business Writing Software for Real-World Solutions 2.pptx
The Codex of Business Writing Software for Real-World Solutions 2.pptxThe Codex of Business Writing Software for Real-World Solutions 2.pptx
The Codex of Business Writing Software for Real-World Solutions 2.pptxMalak Abu Hammad
 
From Event to Action: Accelerate Your Decision Making with Real-Time Automation
From Event to Action: Accelerate Your Decision Making with Real-Time AutomationFrom Event to Action: Accelerate Your Decision Making with Real-Time Automation
From Event to Action: Accelerate Your Decision Making with Real-Time AutomationSafe Software
 
🐬 The future of MySQL is Postgres 🐘
🐬  The future of MySQL is Postgres   🐘🐬  The future of MySQL is Postgres   🐘
🐬 The future of MySQL is Postgres 🐘RTylerCroy
 
08448380779 Call Girls In Diplomatic Enclave Women Seeking Men
08448380779 Call Girls In Diplomatic Enclave Women Seeking Men08448380779 Call Girls In Diplomatic Enclave Women Seeking Men
08448380779 Call Girls In Diplomatic Enclave Women Seeking MenDelhi Call girls
 

Último (20)

Finology Group – Insurtech Innovation Award 2024
Finology Group – Insurtech Innovation Award 2024Finology Group – Insurtech Innovation Award 2024
Finology Group – Insurtech Innovation Award 2024
 
A Domino Admins Adventures (Engage 2024)
A Domino Admins Adventures (Engage 2024)A Domino Admins Adventures (Engage 2024)
A Domino Admins Adventures (Engage 2024)
 
Scaling API-first – The story of a global engineering organization
Scaling API-first – The story of a global engineering organizationScaling API-first – The story of a global engineering organization
Scaling API-first – The story of a global engineering organization
 
CNv6 Instructor Chapter 6 Quality of Service
CNv6 Instructor Chapter 6 Quality of ServiceCNv6 Instructor Chapter 6 Quality of Service
CNv6 Instructor Chapter 6 Quality of Service
 
04-2024-HHUG-Sales-and-Marketing-Alignment.pptx
04-2024-HHUG-Sales-and-Marketing-Alignment.pptx04-2024-HHUG-Sales-and-Marketing-Alignment.pptx
04-2024-HHUG-Sales-and-Marketing-Alignment.pptx
 
The 7 Things I Know About Cyber Security After 25 Years | April 2024
The 7 Things I Know About Cyber Security After 25 Years | April 2024The 7 Things I Know About Cyber Security After 25 Years | April 2024
The 7 Things I Know About Cyber Security After 25 Years | April 2024
 
A Call to Action for Generative AI in 2024
A Call to Action for Generative AI in 2024A Call to Action for Generative AI in 2024
A Call to Action for Generative AI in 2024
 
Raspberry Pi 5: Challenges and Solutions in Bringing up an OpenGL/Vulkan Driv...
Raspberry Pi 5: Challenges and Solutions in Bringing up an OpenGL/Vulkan Driv...Raspberry Pi 5: Challenges and Solutions in Bringing up an OpenGL/Vulkan Driv...
Raspberry Pi 5: Challenges and Solutions in Bringing up an OpenGL/Vulkan Driv...
 
08448380779 Call Girls In Greater Kailash - I Women Seeking Men
08448380779 Call Girls In Greater Kailash - I Women Seeking Men08448380779 Call Girls In Greater Kailash - I Women Seeking Men
08448380779 Call Girls In Greater Kailash - I Women Seeking Men
 
TrustArc Webinar - Stay Ahead of US State Data Privacy Law Developments
TrustArc Webinar - Stay Ahead of US State Data Privacy Law DevelopmentsTrustArc Webinar - Stay Ahead of US State Data Privacy Law Developments
TrustArc Webinar - Stay Ahead of US State Data Privacy Law Developments
 
Developing An App To Navigate The Roads of Brazil
Developing An App To Navigate The Roads of BrazilDeveloping An App To Navigate The Roads of Brazil
Developing An App To Navigate The Roads of Brazil
 
Mastering MySQL Database Architecture: Deep Dive into MySQL Shell and MySQL R...
Mastering MySQL Database Architecture: Deep Dive into MySQL Shell and MySQL R...Mastering MySQL Database Architecture: Deep Dive into MySQL Shell and MySQL R...
Mastering MySQL Database Architecture: Deep Dive into MySQL Shell and MySQL R...
 
Driving Behavioral Change for Information Management through Data-Driven Gree...
Driving Behavioral Change for Information Management through Data-Driven Gree...Driving Behavioral Change for Information Management through Data-Driven Gree...
Driving Behavioral Change for Information Management through Data-Driven Gree...
 
08448380779 Call Girls In Friends Colony Women Seeking Men
08448380779 Call Girls In Friends Colony Women Seeking Men08448380779 Call Girls In Friends Colony Women Seeking Men
08448380779 Call Girls In Friends Colony Women Seeking Men
 
Salesforce Community Group Quito, Salesforce 101
Salesforce Community Group Quito, Salesforce 101Salesforce Community Group Quito, Salesforce 101
Salesforce Community Group Quito, Salesforce 101
 
08448380779 Call Girls In Civil Lines Women Seeking Men
08448380779 Call Girls In Civil Lines Women Seeking Men08448380779 Call Girls In Civil Lines Women Seeking Men
08448380779 Call Girls In Civil Lines Women Seeking Men
 
The Codex of Business Writing Software for Real-World Solutions 2.pptx
The Codex of Business Writing Software for Real-World Solutions 2.pptxThe Codex of Business Writing Software for Real-World Solutions 2.pptx
The Codex of Business Writing Software for Real-World Solutions 2.pptx
 
From Event to Action: Accelerate Your Decision Making with Real-Time Automation
From Event to Action: Accelerate Your Decision Making with Real-Time AutomationFrom Event to Action: Accelerate Your Decision Making with Real-Time Automation
From Event to Action: Accelerate Your Decision Making with Real-Time Automation
 
🐬 The future of MySQL is Postgres 🐘
🐬  The future of MySQL is Postgres   🐘🐬  The future of MySQL is Postgres   🐘
🐬 The future of MySQL is Postgres 🐘
 
08448380779 Call Girls In Diplomatic Enclave Women Seeking Men
08448380779 Call Girls In Diplomatic Enclave Women Seeking Men08448380779 Call Girls In Diplomatic Enclave Women Seeking Men
08448380779 Call Girls In Diplomatic Enclave Women Seeking Men
 

Quantum Cost Calculation of Reversible Circuits

  • 1. Quantum Cost Calculation of Reversible Circuit Sajib Mitra Department of Computer Science and Engineering University of Dhaka sajibmitra.csedu@yahoo.com
  • 2. OVERVIEW  Reversible Logic  Quantum Computing  Quantum Gates  Realization of Quantum NOT  Quantum wire and Special Cases  Quantum Cost Calculation of RC  Conclusion  Assignment  References
  • 3. Reversible Logic  Equal number of input and output vectors  Preserves an unique mapping between input and output vectors of the particular circuit  One or more operation can implement in a single unit called Reversible Gate  (N x N) Reversible Gate has N number of inputs and N number of outputs where N= {1, 2, 3, …}
  • 4. Reversible Logic (cont…)  Advantage  Recovers bit-loss as well as production of heat  Adaptable for Quantum Computing  Multiple operations in a single cycle  Uses low power CMOS technology
  • 5. Reversible Logic (cont…)  Limitation  Feedback is strictly restricted  Maximum and minimum Fan-out is always one
  • 6. Reversible Logic (cont…) Most Popular reversible gates are as follows: Fig. 3x3 Dimensional Reversible gates
  • 7. Reversible Logic (cont…) Most Popular reversible gates are as follows: Fig. 4x4 Dimensional Reversible gates
  • 8. Quantum Computing  First proposed in the 1970s, quantum computing relies on quantum physics by taking advantage of certain quantum physics properties of atoms or nuclei that allow them to work together as quantum bits, or qubits, to be the computer's processor and memory.  Qubits can perform certain calculations exponentially faster than conventional computers.  Quantum computers encode information as a series of quantum-mechanical states such as spin directions of electrons or polarization orientations of a photon that might represent as 0 or 1 or might represent a superposition of the two values. q =α 0 + β 1
  • 9. Quantum Computing (cont…)  Quantum Computation uses matrix multiplication rather than conventional Boolean operations and the information measurement is realized using qubits rather than bits The matrix operations over qubits are simply specifies by using quantum primitives as follows:
  • 10. Quantum Computing (cont…) Input Output Input/output Symbol A B P Q Pattern 0 0 0 0 00 a 0 1 0 1 01 b 1 0 1 1 10 c 1 1 1 0 11 d
  • 11. Quantum Computing (cont…)
  • 12. Quantum Computing (cont…) Input Output A B P Q 0 0 0 0 0 1 0 1 1 0 1 1 1 1 1 0
  • 13. Quantum Gates Fig: Quantum Gates are used for realizing Reversible Circuit
  • 14. Quantum Gates (cont…)  What is SRN? But
  • 15. Quantum Gates (cont…)  What is SRN? But NOT But How?
  • 16. Realization of Quantum NOT Basic operator for single input line: 1. NOT 2. Coin Flip 3. Quantum Coin Flip
  • 17. Realization of Quantum NOT (cont…)
  • 18. Realization of Quantum NOT (cont…) Probability of 0 or 1 based on Coin Flip: 1 1/2 1/2 0 1 1/2 1/2 1/2 1/2 0 1 0 1 1/4 1/4 1/4 1/4
  • 19. Realization of Quantum NOT (cont…) Probability of 0 or 1 based on Coin Flip: 1 1/2 1/2 So the Probability of P(0)=1/2 0 1 P(1)=1/2 1/2 1/2 1/2 1/2 0 1 0 1 1/4 1/4 1/4 1/4
  • 20. Realization of Quantum NOT (cont…) Probability of |0> or |1> based on Quantum Coin Flip: | 1> 1 1 2 2 | | 0> 1> 1 − 1 1 1 2 2 2 2 | | | | 0> 1> 0> 1> 1 −1 1 1 2 2 2 2
  • 21. Realization of Quantum NOT (cont…) Probability of |0> or |1> based on Quantum Coin Flip: | 1> 1 1 2 2 So the Probability of | | P(|0>)=1 0> 1> P(|1>)=0 1 − 1 1 1 2 2 2 2 | | | | 0> 1> 0> 1> 1 −1 1 1 2 2 2 2
  • 22. Realization of Quantum NOT (cont…)  NOT operation can be divided into to SRN matrix production 1 NO 0 T
  • 23. Quantum Cost (QC) of any reversible circuit is the total number of 2x2 quantum primitives which are used to form equivalent quantum circuit.
  • 24. Quantum Wire and Special Cases (cont…) Quantum XOR gate, cost is 1
  • 25. Quantum Wire and Special Cases (cont…) Two Quantum XOR gates, but cost is 0
  • 26. Quantum Wire and Special Cases (cont…) Quantum Wire
  • 27. Quantum Wire and Special Cases (cont…) Quantum Cost of V and V+ are same , equal to one. SRN and its Hermitian Matrix on same line. VV+= Identity and the total cost = 0
  • 28. Quantum Wire and Special Cases (cont…) SRN and its Hermitian Matrix on same line. VV+= Identity and the total cost = 0
  • 29. Quantum Wire and Special Cases (cont…) The attachment of SRN (Hermitian Matrix of SRN) and EX-OR gate on the same line generates symmetric gate pattern has a cost of 1. Here T= V or V+
  • 30. Quantum Wire and Special Cases (cont…) The cost of all 4x4 Unitary Matrices (b, c, d) and the symmetric gate pattern (e, f, g, h) are unit.
  • 32. Quantum Cost of Toffoli Gate But How?
  • 33. Quantum Cost of Toffoli Gate INPUT OUTPUT a b r 0 0 c 0 1 c 1 0 c 1 1 c’
  • 34. Quantum Cost of Toffoli Gate INPUT OUTPUT a b r 0 0 c 0 1 c 1 0 c 1 1 c’
  • 35. Quantum Cost of Toffoli Gate INPUT OUTPUT a b r 0 0 c 0 1 c 1 0 c 1 1 c’ INPUT OUTPUT a b r 0 0 c 0 1 c 1 0 c 1 1 c’
  • 36. Now
  • 37. Quantum Cost of Toffoli Gate Input Outpu t A B R 0 0 C 0 1 C 1 Have anything wr 0 C 1 1 C’
  • 38. Quantum Cost of Toffoli Gate Input Outpu t A B R 0 0 C 0 1 C 1 0 C 1 1 C’ Ok
  • 39. Quantum Cost of Toffoli Gate (cont…) Alternate representation of Quantum circuit of TG…
  • 40. Quantum Cost of Fredkin Gate But How?
  • 41. Quantum Cost of Fredkin Gate (cont…)
  • 42. Quantum Cost of Fredkin Gate (cont…)
  • 43. Quantum Cost of Fredkin Gate (cont…)
  • 44. Quantum Cost of Fredkin Gate (cont…)
  • 45. Quantum Cost of Fredkin Gate (cont…)
  • 46. Quantum Cost of Fredkin Gate (cont…)
  • 47. Quantum Cost of Peres Gate
  • 48. Quantum Cost of NFT Gate
  • 49. Quantum Cost of NFT Gate
  • 50. Quantum Cost of MIG Gate
  • 51. Assignment Find out cost
  • 52. About Author Sajib Kumar Mitra is an MS student of Dept. of Computer Science and Engineering, University of Dhaka, Dhaka, Bangladesh. His research interests include Electronics, Digital Circuit Design, Logic Design, and Reversible Logic Synthesis.