This Presentation discusses the various terminology involved in ASIC design. Each step is described with the help of a flowchart.

1. ASIC DESIGN FLOW
(DIGITAL FLOW)
SUDHANSHU JANWADKAR
S. V. NATIONAL INSTITUTE OF TECHNOLOGY,
SURAT

2. Introduction
ASIC: Application Specific Integrated Circuits
- Electronic circuitry realised on a silicon wafer
- Performs a dedicated application
- Inherently, not programmable
- Customized for a particular application
What is required to fabricate ASICs?
- Among other requirements, Masks are a pre-
requisite

3. • A mask is a specification of geometric shapes that
need to be created on a certain layer.
• Masks are used to produce a pattern on a substrate,
(normally a thin slice of silicon known as a wafer).
• Several masks are used in turn, each one
reproducing a layer of the completed design
• Masks are used to create a specific patterns of each
material in a sequential manner and create a
complex pattern of several layers
Introduction

4. Introduction

5. Introduction
• Integrated circuit layout is the representation of an
integrated circuit in terms of planar geometric
shapes.
• The shapes correspond to the patterns of metal,
oxide, or semiconductor layers, that make up the
components of the integrated circuit.
• Drawing a custom layout is feasible
when the number of transistors in
circuit are less in number.

6. Motivation
• Modern day chips contain millions of transistors.
• Would it be feasible to design such a complex
system with help of truth table and K-maps?
• Would it be feasible to draw custom layout?
Obviously Impossible!!

7. Contd..
• Today’s semiconductors and electronic systems are
complex that designing them would be impossible
without electronic design automation (EDA) tools.
• Using these EDA tools, the layout engineer places and
connects all of the components that make up the chip.
• EDA tools run scripts in background which employ
complex algorithms to effect the processes.
• The typical steps are discussed.

8. Digital Design Flow
Verilog/
VHDL
Library
Std., Cell.
Library
Tech file
For layout
values
Look up
Table for
timing
Tech file
For RC
Parasite
extraction
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification

9. Design Analysis
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
This is a very crucial step in
digital design where the design
functionality is stated.
Like if we are making a processor,
what type of functionality is
expected??

10. Design Specification
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
This step involved stating in
definite terms the performance of
the chip.
Like if we are making a processor,
data size, processor speed, special
functions, power etc. is clearly
stated at this point.
So, it deals with architectural part
of the design at highest level
possible.
Based on these foundation , the
whole design is built.

11. Design Implementation using
HDL
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Hardware Description Language
is used to run the simulations.
It is very expensive to build the
entire chip and then verify the
performance of the architecture.
Imagine if after designing
a chip for a whole year, the chip
fabricated, does not come even
closer to the specifications.

12. Design Implementation using HDL
(contd..)
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Hardware description languages
provides a way to implement a
design without going into much
architecture, simulate and verify
design output and functionality.
For example, rather than building
a mux design in hardware, we
can write verilog code and verify
the output at higher level of
abstraction.
Examples of HDL: VHDL,
Verilog HDL

13. Synthesis
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Most of the digital designs are
build up of some basic
elements or components like
logic gates, registers, counters,
adders, substractors, shifters,
comparators, RAM, ROM etc.
Standard Cell Library is the
collection of such building
blocks which comprises most
of the digital designs.
These cell libraries are specific
to technology node (foundry).

14. Synthesis (contd..)
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
When the synthesis tool (e.g.
genus) encounters a specific
construct in HDL, it replaces it
with the corresponding
Standard Cell from the library
to build the entire design.
There may be different options
of standard cells available to
customize chip area, delay etc.
Like if we use a for loop , it
gets converted to counter and a
combinational circuit.

15. Synthesis (contd..)
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
At the end of this stage, we have
the logic circuit i.e. in terms of
gates and memories
The output of synthesis is a gate
level netlist.
Netlist is an ASCII file which
enlists and indicates the devices
and the interconnections between
them.

16. Simulation
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
After the netlist is generated as part
of synthesis, this netlist is
simulated to verify the functionality
of this gate level implementation of
design.
Till this step, only simulation meant
only functional verification.
Here onwards, simulation is done
also to verify if the design meets
specification (mostly in terms of
delay parameters).

17. Timing Analysis
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
RTL and Gate Level simulation
doesn’t take into account the
physical time delay in signal
propagation from one device to
another and through
the device.
This time delay is dependent on
the fabrication process adopted.
Each component in standard cell
library is associated with some
specific delay.

18. Timing Analysis (contd..)
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Delay Lookup Tables list the delays
associated with the components.
Delays are in the form of rise time,
fall time etc.
In timing analysis, using Delay
Lookup Tables, all the inputs and
outputs of components are verified
with timing introduced.
Design proceeds to further steps of
physical design only if timing is
met. If timing is not met, then
various techniques such as resizing
of standard cells, insertion of
buffers etc. may be carried out.

19. Place and Route
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Semiconductor layout has to follow
certain design rules to lay devices
at semiconductor level.
These design rules are fabrication
process dependent.
The layout uses layers as p/n
diffusion, nwell, pwell, metals, via
etc.
Rules involving minimum spacing
between two layers, width of each
layer, minimum area of contact
between two layers etc. are known
as Design Rules.

20. Place and Route (contd..)
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Placement and Routing involves
laying of the devices, placing
them and making interconnection
between them, following the
Design Rules.
The result is the design
implemented in the form of
semiconductor layers.

21. Extraction
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Once the layout is made, there
always is parasitic capacitances
and resistances associated with
the design.
This is because of the compact
layouts to make the chips smaller.
More you make compact layout
more will it introduce these
parasitic components.
These interferes in the
functioning and performance of
the circuit in terms of timing,
speed and power consumption.

22. Extraction (contd..)
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Due to these factors it becomes
very much important to extract
these devices from layout and
check the design for
performance and functionality.
Extraction would extract from
the layout, the devices formed
because of junctions of different
semiconductor and metal layers
and the interconnections.

23. Verification
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Verification would either be just
before tape out stage of the chip or
the stage where design is again taken
back through the same flow for
optimization or modification.
It verifies the extracted view of the
chip for performance and
functionality.
Various Design Rule Check (DRC),
Layout vs Schematic(LVS), Antenna
rule check etc. are performed.

24. What Next?
• When all verification is complete, layout post
processing is applied where the data is also
translated into an industry-standard format (typically
called GDSII).
• This is sent to a semiconductor foundry. The
milestone completion of the layout process of
sending this data to the foundry is called "tapeout".
• The foundry converts the data into mask data and
uses it to generate the photo-masks used in a
photolithographic process of semiconductor device
fabrication.