Subido poralbertoperojoparas
PPT, PDF305 vistas

Transpar Tema1a

Este documento introduce Verilog como un lenguaje de descripción de hardware. Explica los diferentes niveles de abstracción en la síntesis digital, incluyendo simulación lógica, transferencia de registros y nivel de circuito. También describe tipos de datos, sentencias de asignación, operadores y estructuras de módulos en Verilog.

Incrustar presentación

Descargar para leer sin conexión
INTRODUCCIÓN A VERILOG Objetivos comprender el uso de un HDL en el diseño de sistemas digitales estudiar Verilog como Lenguaje de Descripción de Hardware (HDL)
Bibliografía J. Bhasker: “Verilog HDL synthesis: A practical primer”, Star Galaxy Publishing, 1998. E. Villar y P. Sánchez: “Síntesis”, Capitulo 4 de L. Terés, Y. Torroja, S. Olcóz y E. Villar: “VHDL: Lenguaje estándar de diseño electrónico”, McGraw-Hill, 1998. INTRODUCCIÓN A VERILOG
SÍNTESIS AL NIVEL DE TRANSFERENCIA ENTRE REGISTROS Simulación Lógica Arquitectura RT Circuito Lógico Posicionamiento Interconexión Síntesis RT-Lógica Implementación Retroanotación Simulación RT Optimización aritmética Identificación de elementos de memoria Codificación de tipos Extracción de las funciones lógicas Minimización Lógica
NIVELES DE ABSTRACCIÓN Modelo de Computación: Tiempo discreto Señal  transición activa de la señal de reloj Señal t Simulación RT
NIVELES DE ABSTRACCIÓN Modelo de Computación: eventos discretos Simulación dirigida por eventos Simulación Lógica Señal t Señal t transición activa de la señal de reloj Simulación RT
NIVELES DE ABSTRACCIÓN ventana de comparación corrección del diseño valores compatibles Simulación Lógica Señal t Señal t transición activa de la señal de reloj Simulación RT Señal t Simulación Lógica retroanotada transición activa de la señal de reloj tiempo de ‘ set-up’ periodo de reloj - tiempo de ‘set-up’ camino crítico ‘ X’ ‘ 1’ ‘ 1’
SISTEMA DIGITAL A NIVEL RT Entradas de Control Entradas de Datos Salidas de Control Señales de Control Señales de Estatus Salidas de Datos Unidad de Control Unidad de Datos
SISTEMA DIGITAL A NIVEL RT Lógica Combinacional de Control Registro de Estado reloj reset set Estado de Control próximo Estado de Control actual Salidas de Control Entradas de Control Señales de Control Señales de Estatus Lógica Combinacional y Unidades Operacionales Registros de Datos reloj reset set Datos próximos Valores actuales en registros Salidas de Datos Entradas de Datos
VALORES LÓGICOS Interpretación en modelado y síntesis ‘ don’t care’ desconocido x tri-estado (‘don’t care’ en sentencias ‘case’) tri-estado z (?) ‘ 1’ lógico ‘ 1’ lógico 1 ‘ 0’ lógico ‘ 0’ lógico 0 síntesis simulación
MÓDULO Entidad de diseño module Ejemplo (BpW, Error, Wait, Valid, Clear); input Error, Wait, Valid, Clear; output BpW; . . . endmodule Error BpW Wait Valid Clear Ejemplo
TIPOS DE DATOS Nodos de red (‘net data types’) wire Ax; // línea de un ‘bit’ wire [4:0] Dak; // agrupación de 5 líneas wire línea tri idéntico a ‘wire’ (sólo informa de múltiples drivers) supply0 y supply1 ‘ 0’ ‘ 1’
TIPOS DE DATOS Nodos de red (‘net data types’) wire Error BpW Wait Valid Clear module Ejemplo (BpW, Error, Wait, Valid, Clear); input Error, Wait, Valid, Clear; output BpW; wire BpW; assign BpW = Error&Wait; endmodule Ejemplo
TIPOS DE DATOS Nodos de red (‘net data types’) múltiples ‘drivers’ Error BpW Wait Valid Clear module Ejemplo (BpW, Error, Wait, Valid, Clear); input Error, Wait, Valid, Clear; output BpW; wire BpW; assign BpW = Error&Wait; assign BpW = Valid | Clear; endmodule Error&Wait 0101 Valid | Clear 0011 BpW 0xx1
TIPOS DE DATOS Nodos de red (‘net data types’) wor Error BpW Wait Valid Clear module Ejemplo (BpW, Error, Wait, Valid, Clear); input Error, Wait, Valid, Clear; output BpW; wor BpW; assign BpW = Error&Wait; assign BpW = Valid | Clear; endmodule Error&Wait 0101 Valid | Clear 0011 BpW 0111
TIPOS DE DATOS Nodos de red (‘net data types’) wor Error BpW Wait Valid Clear module Ejemplo (BpW, Error, Wait, Valid, Clear); input Error, Wait, Valid, Clear; output BpW; wor BpW; assign BpW = Error&Wait; assign BpW = Valid | Clear; endmodule
TIPOS DE DATOS Nodos de red (‘net data types’) wand Error BpW Wait Valid Clear module Ejemplo (BpW, Error, Wait, Valid, Clear); input Error, Wait, Valid, Clear; output BpW; wand BpW; assign BpW = Error&Wait; assign BpW = Valid | Clear; endmodule Error&Wait 0101 Valid | Clear 0011 BpW 0001
TIPOS DE DATOS Nodos de red (‘net data types’) wand Error BpW Wait Valid Clear module Ejemplo (BpW, Error, Wait, Valid, Clear); input Error, Wait, Valid, Clear; output BpW; wand BpW; assign BpW = Error&Wait; assign BpW = Valid | Clear; endmodule
TIPOS DE DATOS Registros reg Ax; // registro de un ‘bit’ reg [4:0] Dak; // registro de 5 ‘bits’ reg integer registros de hasta 32 ‘bits’ en complemento-2 la herramienta de síntesis debe sintetizar el tamaño mínimo wire [1:5] Brq, Rbu; integer Arb; . . . Arb = Brq + Rbu; . . . 6 + Brq Rbu Arb 5 5
TIPOS DE DATOS Constantes 30 -2 decimal simple 32 ‘bits’ en complemento-2 formato con base 2’b10 6’d-4 ’d-10 [size]’base value base=h,H,o,O,b,B,d,D
TIPOS DE DATOS Parámetros constantes nominales parameter RED = -1, GREEN = 2; // constantes decimales (32 bits en complemento-2) parameter READY = 2’b01, BUSY = 2’b11, EXIT = 2’b10; // constantes de 2 ‘bits’
DESCRIPCION ESTRUCTURAL
DESCRIPCION PARAMETRIZABLE (0)
DESCRIPCION PARAMETRIZABLE (1)
SENTENCIAS DE ASIGNACIÓN Asignación continua assign Error Stop Start Wait Valid Clear module Ejemplo (Stop, Start, Error, Wait, Valid, Clear); input Error, Wait, Valid, Clear; output Stop, Start; wire Stop, Start; assign Stop = Error&Wait; assign Start = Valid | Clear; endmodule sentencias concurrentes Ejemplo
SENTENCIAS DE ASIGNACIÓN Asignación continua retraso Error Stop Start Wait Valid Clear module Ejemplo (Stop, Start, Error, Wait, Valid, Clear); input Error, Wait, Valid, Clear; output Stop, Start; wire Stop, Start; assign #5 Stop = Error&Wait; assign #6 Start = Valid | Clear; endmodule retrasos ignorados en síntesis
SENTENCIAS DE ASIGNACIÓN Asignación procesal module Ejemplo (Preset, Count); input [0:2] Preset; output [3:0] Count; reg [3:0] Count; always @ (Preset) begin . . . end endmodule sentencias secuenciales
SENTENCIAS DE ASIGNACIÓN Asignación procesal asignación bloqueante module Ejemplo (Preset, Count); input [0:2] Preset; output [3:0] Count; reg [3:0] Count; always @ (Preset) Count = Preset + 1; endmodule Preset[2] Preset[1] Preset[0] Count[0] Count[1] Count[3] Count[2]
SENTENCIAS DE ASIGNACIÓN Asignación procesal asignación no-bloqueante module Ejemplo (Preset, Count); input [0:2] Preset; output [3:0] Count; reg [3:0] Count; always @ (Preset) Count <= Preset + 1; endmodule Preset[2] Preset[1] Preset[0] Count[0] Count[1] Count[3] Count[2]
SENTENCIAS DE ASIGNACIÓN Asignación procesal las asignaciones dobles a un mismo objeto son un error Count <= Preset + 1; . . . Count = Mask; los retrasos se ignoran #5 Count <= Preset + 1; . . . Count = #5 Mask; retrasos ignorados en síntesis
OPERADORES Operadores lógicos expresiones de conmutación module FullAdder (A, B, Carryin, Sum, Carryout); input A, B, Carryin; output Sum, Carryout; assign Sum = (A ^ B) ^ Carryin; assign Carryout = (A & B) | (B & Carryin) | (A & Carryin); endmodule xor ^ or | and & complemento ~ A B Carryin Carryout Sum
OPERADORES Operadores aritméticos multiplicación * división / módulo % substracción - suma + signo +, -
OPERADORES Operadores aritméticos net, reg: operaciones sin signo module UnsignedAdder (Arb, Bet, Lot); input [2:0] Arb, Bet; output [2:0] Lot; assign Lot = Arb + Bet; endmodule + Arb Bet Lot 3 3 3
OPERADORES Operadores aritméticos integer: operaciones con signo module SignedAdder (Arb, Bet, Lot); input [1:0] Arb, Bet; output [2:0] Lot; reg [2:0] Lot; always @ (Arb or Bet) begin : addition integer Arbint, Betint; Arbint = - Arb; Betint = Bet; Lot = Arbint + Betint; end endmodule Bet ‘ 1’ Arb + Lot + 2 3 3 2 3
OPERADORES Operadores aritméticos ‘ carry’ y ‘borrow’ module carryborrow (Arb, Bet, Lot); input [3:0] CdoBus; output [3:0] Sum; output [4:0] OneUp; output [3:0] ShortOneUp; output Bore; assign OneUp = CdoBus + 1; assign ShortOneUp = CdoBus + 1; assign (Bore, Sum) = CdoBus – 2; endmodule // OneUp[4] lleva el ‘carry’ // se pierde el ‘carry’ // Bore lleva el ‘borrow’
OPERADORES Operadores relacionales mayor o igual >= menor o igual <= menor < mayor >
OPERADORES Operadores relacionales net, reg: comparaciones sin signo module GreatherThan (A, B, Z); input [3:0] A, B; output Z; assign Z = A[1:0] > B[3:2]; endmodule B A > Z
OPERADORES Operadores relacionales integer: comparaciones con signo module SignedGreatherThan (ArgA, ArgB, ResultZ); input [2:0] ArgA, ArgB; output ResultZ; reg ResultZ; integer ArgAInt, ArgBInt; always @ (ArgA or ArgB) begin ArgAInt = - ArgA; ArgBInt = - ArgB; ResultZ = ArgAInt > ArgBInt; end endmodule ‘ 1’ ArgB ‘ 1’ ArgA + > + ResultZ
OPERADORES Operadores relacionales igualdad y desigualdad module NotEquals (A, B, Z); input [0:3] A, B; output Z; reg Z; always @ (A or B) begin : comparison integer IntA, IntB; IntA = A; IntB = B; Z = IntA !=IntB; end endmodule distinto != igual = A[0] B[0] Z A[1] B[1] A[2] B[2] A[3] B[3]
OPERADORES Operadores de desplazamiento desplazamiento lógico constante module ConstantShift (DataMux, Address); input [0:3] DataMux; output [0:5] Address; assign Address = (~ DataMux) << 2; endmodule desplazamiento derecha >> desplazamiento izquierda << DataMux[0] Address[0] DataMux[1] Address[1] DataMux[2] Address[2] DataMux[3] Address[3] Address[4] Address[5]
OPERADORES Operadores de desplazamiento desplazamiento lógico variable module VariableShift (MemDataReg, Amount, InstrReg); input [0:2] MemDataReg; input [0:1] Amount; output [0:2] InstrReg; assign InstrReg = MemDataReg >> Amount; endmodule MemDataReg[0] MemDataReg[1] MemDataReg[2] InstrReg[0] InstrReg[1] InstrReg[2] Amount[0] Amount[1]
OPERADORES Operaciones con vectores operaciones lógicas module LogicalVectorOperations (A, B, C, Z); input [0:3] A, B, C; output [0:3] Z; assign Z = (A & B) | C; endmodule C[0] B[0] A[0] Z[0] C[1] B[1] A[1] Z[1] C[2] B[2] A[2] Z[2] C[3] B[3] A[3] Z[3]
OPERADORES Operaciones con vectores selección de partes module Selection (A, B, RegFile, ZCat); input [3:0] A, B, RegFile; output [3:0] ZCat; assign ZCat[3] = A[2]; assign ZCat[2:1] = B[3:2]; assign ZCat[0] = RegFile[3]; endmodule A[2] B[3] B[2] RegFile[3] ZCat[3] ZCat[2] ZCat[1] ZCat[0]
OPERADORES Operaciones con vectores concatenación module Concatenation (A, B, RegFile, ZCat); input [3:0] A, B, RegFile; output [3:0] ZCat; assign ZCat[3:0] = {A[2], B[3:2], RegFile[3]}; endmodule A[2] B[3] B[2] RegFile[3] ZCat[3] ZCat[2] ZCat[1] ZCat[0]
OPERADORES Operaciones con vectores selección de ‘bit’ variable en fuente module SourceVariableSelection (Data, Index, Dout); input [0:3] Data; input [1:2] Index; output Dout; assign Dout = Data[Index]; endmodule Data[0] Data[1] Data[2] Data[3] 00 01 10 11 Dout Index[0] Index[1]
OPERADORES Operaciones con vectores selección de ‘bit’ variable en destino (no soportado por ISE) module TargetVariable Selection (Mem, Store, Addr); input Store; input [1:3] Addr; output [7:0] Mem; assign Mem[Addr] = Store; endmodule Mem[0] Mem[1] Mem[2] Mem[3] Mem[4] Mem[5] Mem[6] Mem[7] 000 001 010 011 100 101 110 111 Store Addr[0] Addr[1] Addr[2]
OPERADORES Expresión condicional <condición> ? <expresión 1> : <expresión 2> module ConditionalExpression (StartXM, ShiftVal, Reset, StopXM); input StartXM, ShiftVal, Reset; output StopXM; assign StopXM = (! Reset) ? StartXM ^ ShiftVal : StartXM | ShiftVal ; endmodule 1 0 StartXM ShiftVal Reset StopXM
COMPORTAMIENTO COMBINACIONAL descripción de comportamiento código secuencial Sentencia ‘always’ module EvenParity (A, B, C, D, Z); input A, B, C, D; output Z; reg Z, Temp1, Temp2; always @ (A or B or C or D) begin Temp1 = A ^ B; Temp2 = C ^ D; Z = Temp1 ^ Temp2; end endmodule Z A B C D
lista de sensibilidad lógica combinacional Sentencia ‘always’ module EvenParity (A, B, C, D, Z); input A, B, C, D; output Z; reg Z; always @ (A or B) begin Z = A ^ B ^ C ^ D; end endmodule COMPORTAMIENTO COMBINACIONAL Z A B C D
Condición COMPORTAMIENTO COMBINACIONAL module Condition (StartXM, ShiftVal, Reset, StopXM); input StartXM, ShiftVal, Reset; output StopXM; reg StopXM; always @ (StartXM or ShiftVal or Reset) begin if (Reset) StopXM = StartXM | ShiftVal ; else StopXM = StartXM ^ ShiftVal ; end endmodule 1 0 StartXM ShiftVal Reset StopXM
Selección COMPORTAMIENTO COMBINACIONAL module ALU (Op, A, B, Z); input [1:2] Op; input [0:1] A, B; output [0:1] Z; reg [0:1] Z; parameter ADD = 'b00, SUB = 'b01, MUL = 'b10, AND = 'b11; always @ (Op or A or B) begin case (Op) ADD: Z = A + B; SUB: Z = A - B; MUL: Z = A * B; DIV: Z = A / B; endcase endmodule A Z B +/- * Op[1] Op[2] 00 01 10 11
Selección COMPORTAMIENTO COMBINACIONAL module CaseExample (DayOfWeek, SleepTime); input [1:3] DayOfWeek; output [1:4] SleepTime; reg [1:4] SleepTime; parameter MON = 0, TUE = 1, WED = 2, THU = 3, FRI = 4, SAT = 5, SUN = 6; always @ (DayOfWeek) begin case (DayOfWeek) MON, TUE, WED, THU: SleepTime = 6; FRI : SleepTime = 8; SAT : SleepTime = 9; SUN : SleepTime = 7; default SlepTime = 10; endcase end endmodule 000 001 010 011 100 101 110 111 DayOfWeek[1] DayOfWeek[2] DayOfWeek[3] SleepTime[1] SleepTime[2] SleepTime[3] SleepTime[4]
Selección con ‘z’ como ‘don´t care’ COMPORTAMIENTO COMBINACIONAL module CasezExample (ProgramCounter, DoCommand); input [0:3] ProgramCounter; output [0:1] DoCommand; reg [0:1] DoCommand; always @ (ProgramCounter) begin casez (ProgramCounter) 4’bzzz1: DoCommand = 0; 4’bzz10: DoCommand = 1; 4’bz100: DoCommand = 2; 4’b1000: DoCommand = 3; default DoCommand = 0; endcase end endmodule ProgramCounter[0] ProgramCounter[1] ProgramCounter[2] ProgramCounter[3] DoCommand[0] DoCommand[1]
Selección con ‘z’ y ‘x’ como ‘don´t care’ COMPORTAMIENTO COMBINACIONAL module CasexExample (ProgramCounter, DoCommand); input [0:3] ProgramCounter; output [0:1] DoCommand; reg [0:1] DoCommand; always @ (ProgramCounter) begin casex (ProgramCounter) 4’bxxx1: DoCommand = 0; 4’bzz10: DoCommand = 1; 4’bz100: DoCommand = 2; 4’b1000: DoCommand = 3; default DoCommand = 0; endcase end endmodule ProgramCounter[0] ProgramCounter[1] ProgramCounter[2] ProgramCounter[3] DoCommand[0] DoCommand[1]
Orden de selección COMPORTAMIENTO COMBINACIONAL codificador de prioridad module CasexExample (ProgramCounter, DoCommand); input [0:3] ProgramCounter; output [0:1] DoCommand; reg [0:1] DoCommand; always @ (ProgramCounter) begin casex (ProgramCounter) 4’bxxx1: DoCommand = 0; 4’bxx1x: DoCommand = 1; 4’bx1xx: DoCommand = 2; 4’b1xxx: DoCommand = 3; default DoCommand = 0; endcase end endmodule ProgramCounter[0] ProgramCounter[1] DoCommand[0] DoCommand[1] ProgramCounter[2] ProgramCounter[3]
Orden de selección COMPORTAMIENTO COMBINACIONAL codificador de prioridad module CasexExample (ProgramCounter, DoCommand); input [0:3] ProgramCounter; output [0:1] DoCommand; reg [0:1] DoCommand; always @ (ProgramCounter) begin if (ProgramCounter[3]) DoCommand = 0; else if (ProgramCounter[2]) DoCommand = 1; else if (ProgramCounter[1]) DoCommand = 2; else if (ProgramCounter[0]) DoCommand = 3; else DoCommand = 0; end endmodule ProgramCounter[0] ProgramCounter[1] DoCommand[0] DoCommand[1] ProgramCounter[2] ProgramCounter[3]
Lazos COMPORTAMIENTO COMBINACIONAL ‘ while’ ‘ forever’ ‘ repeat’ ‘ for’ no soportada en síntesis no soportada en síntesis no soportada en síntesis
Lazos COMPORTAMIENTO COMBINACIONAL ‘ for’ module DeMultiplexer (Address, Data, Line); input [1:0] Address; input Data; output [3:0] Line; reg [3:0] Line; integer J; always @ (Address) for (J = 3; J >= 0; J = J – 1) if (Address == J) Line[J] = Data; else Line[J] = 0; endmodule Address[1] Address[0] Line[3] Line[2] Line[1] Line[0] Data
Lazos COMPORTAMIENTO COMBINACIONAL ‘ for’ module DeMultiplexer (Address, Line); input [1:0] Address; output [3:0] Line; reg [3:0] Line; integer J; always @ (Address) if (Address == 3) Line[J] = Data; else Line[J] = 0; if (Address == 3) Line[J] = Data; else Line[J] = 0; if (Address == 3) Line[J] = Data; else Line[J] = 0; if (Address == 3) Line[J] = Data; else Line[J] = 0; endmodule Address[1] Address[0] Line[3] Line[2] Line[1] Line[0] Data
Condición LÓGICA COMBINACIONAL toda señal o variable o es asignada bajo cualquier condición de ejecución del proceso, o es utilizada después de ser asignada module NonCombinationalLogic (A, B, C, Z); input A, B, C; output Z; reg Z; always @ (A or B or C) begin : VAR_LABEL reg D; if (! A) Z = D; else begin D = B & C; Z = 1; end end endmodule module NonCombinationalLogic (A, B, C, Z); input A, B, C; output Z; reg Z; always @ (A or B or C) begin : VAR_LABEL reg D; D = B & C; if (! A) Z = D; end endmodule
COMPORTAMIENTO COMBINACIONAL module DeMultiplexer (Address, Data, Line); input [1:0] Address; input Data; output [3:0] Line; reg [3:0] Line; integer J; always @ (Address) for (J = 3; J >= 0; J = J – 1) if (Address == J) Line[J] = Data; endmodule Condición toda señal o variable o es asignada bajo cualquier condición de ejecución del proceso, o es utilizada después de ser asignada
Condición LÓGICA COMBINACIONAL toda señal o variable o es asignada bajo cualquier condición de ejecución del proceso, o es utilizada después de ser asignada module CombinationalLogic (A, B, C, Z); input A, B, C; output Z; reg Z; always @ (A or B or C) begin : VAR_LABEL reg D; if (! A) Z = 1; else begin D = B & C; Z = D; end end endmodule B C A Z
Condición LÓGICA COMBINACIONAL toda señal o variable o es asignada bajo cualquier condición de ejecución del proceso, o es utilizada después de ser asignada module CombinationalLogic (A, B, C); input A, B, C; output Z; reg Z; always @ (A or B or C) begin : VAR_LABEL reg D; D = B & C; if (! A) Z = D; else Z = 1; end endmodule B C A Z
Tareas LÓGICA COMBINACIONAL encapsulado de lógica combinacional module FunctionCall (XBC, DataIn); input [0:5] DataIn; output [0:2] XBC; reg [0:2] XBCTemp; task CountOnes; input [0:5] A; output [0:2] B; integer K; begin B = 0; for (K = 0; K <= 5; K = K+1) if (A[K]) B = B + 1; end ; endtask always @ (DataIn) CountOnes(DataIn, XBCTemp); assign XBC = XBCTemp; endmodule + + + DataIn[0] DataIn[1] DataIn[2] DataIn[3] DataIn[4] DataIn[5] XBC

Más contenido relacionado

PPTX
Resumen asignatura de Introducción a la Programación
porOriol Borras Gene
 
PPTX
Compuertas Logicas
porDavid
 
PDF
Tema 1. elementos básicos de pascal #ipg2murjc
porOriol Borras Gene
 
PPT
Ensayo Clase I
porHector Perez
 
PPT
Funcionesenlenguaje c
porGladys Coromoto Vergel Rivera
 
PPTX
Apunfun2
porpabesacv
 
PPT
Acciones funciones
porEliezer Cordova
 
PPTX
Funciones en Lenguaje C
porJaime David Romero Olivo
 
Resumen asignatura de Introducción a la Programación
porOriol Borras Gene
 
Compuertas Logicas
porDavid
 
Tema 1. elementos básicos de pascal #ipg2murjc
porOriol Borras Gene
 
Ensayo Clase I
porHector Perez
 
Funcionesenlenguaje c
porGladys Coromoto Vergel Rivera
 
Apunfun2
porpabesacv
 
Acciones funciones
porEliezer Cordova
 
Funciones en Lenguaje C
porJaime David Romero Olivo
 

La actualidad más candente

PPT
FUNCIONES LENGUAJE C
porGustavo Salazar Loor
 
PPTX
Funcionamiento de un pila2
porjefer
 
PPTX
Funciones en c++
porJose Eamirez
 
PPT
05 powerpoint daniel-ramirez
porDaniel Ramírez Salazar
 
PPTX
Funciones C++ modificado
porcompumet sac
 
PPTX
Definición de compuertas logicas
porlupicesa22
 
PPT
Compuertas Logicas
porwilmer
 
PPT
2 punteros y lenguaje c
porPedro Contreras Flores
 
PPTX
Laboratorio # 1 introducción a arduino
porCASERA
 
PDF
Apuntes scilab
porRicardo Gutierrez
 
PPTX
APLICACION DE ALGEBRA BOOLEANA
porDariangel Contreras
 
PPT
Etn 601
porDavid Marza Herrera
 
PPTX
Compuertas Logicas
porEnrique
 
DOC
Previo7- Dispos E/S
porBertha Vega
 
PPTX
Tipo de dato DOUBLE
porkenixxx
 
DOCX
Compuertas logicas
porsetidi
 
FUNCIONES LENGUAJE C
porGustavo Salazar Loor
 
Funcionamiento de un pila2
porjefer
 
Funciones en c++
porJose Eamirez
 
05 powerpoint daniel-ramirez
porDaniel Ramírez Salazar
 
Funciones C++ modificado
porcompumet sac
 
Definición de compuertas logicas
porlupicesa22
 
Compuertas Logicas
porwilmer
 
2 punteros y lenguaje c
porPedro Contreras Flores
 
Laboratorio # 1 introducción a arduino
porCASERA
 
Apuntes scilab
porRicardo Gutierrez
 
APLICACION DE ALGEBRA BOOLEANA
porDariangel Contreras
 
Etn 601
porDavid Marza Herrera
 
Compuertas Logicas
porEnrique
 
Previo7- Dispos E/S
porBertha Vega
 
Tipo de dato DOUBLE
porkenixxx
 
Compuertas logicas
porsetidi
 

Destacado

PDF
Alberto Perojo Multi Core
poralbertoperojoparas
 
PDF
G P Un Vidia
poralbertoperojoparas
 
PDF
G P Un Vidia
poralbertoperojoparas
 
PDF
Libro Matlab Web
poralbertoperojoparas
 
PDF
06 Voraces 3en1
poralbertoperojoparas
 
PDF
Supercomputadores
poralbertoperojoparas
 
PDF
Ejercicios modelos lineal
porJulio Pari
 
PDF
PROBLEMA DE LA MOCHILA
porEvelin Rodriguez Rodriguez
 
PPT
Tema 6 DiagnóStico VirolóGico
poralbertoperojoparas
 
Alberto Perojo Multi Core
poralbertoperojoparas
 
G P Un Vidia
poralbertoperojoparas
 
G P Un Vidia
poralbertoperojoparas
 
Libro Matlab Web
poralbertoperojoparas
 
06 Voraces 3en1
poralbertoperojoparas
 
Supercomputadores
poralbertoperojoparas
 
Ejercicios modelos lineal
porJulio Pari
 
PROBLEMA DE LA MOCHILA
porEvelin Rodriguez Rodriguez
 
Tema 6 DiagnóStico VirolóGico
poralbertoperojoparas
 

Similar a Transpar Tema1a

PDF
Verilog-Intro.pdf
porAlfredoVargasRoque
 
PPT
I S A
porStefano Salvatori
 
PPTX
DIGITALES EXPO lnes.pptxhh hh g gfdgh vbbvvguvgvhgvhg
porDiegoOjeda77
 
PDF
Tabla de instrucciones asembler
porEdwin David Toro Echeverria
 
PDF
Introduccion a Matlab
porOmar Yupanqui
 
PDF
TEMA 1.pdf
porBrianEstacio1
 
PDF
Matlab
porOmar Yupanqui
 
PPTX
Clase 2
porManuel Felipe Villalba Miranda
 
PDF
Vhdl2
porDochen Lizama Trancer
 
DOCX
Lista de raptor sus comandos y su función
porAna Ruth G H
 
PDF
Lenguajes máquina y ensamblador
porJose Bondia
 
PPT
Organizacion de la unidad central de procesamiento
porHarold Torres
 
PPT
MSX88 simulador assembly programación arquitectura de software.ppt
pormatias387621
 
ODP
Fundamentos de programación en scilab
porGabriel Romero
 
PPTX
Lab.270910.instrucciones basicas del pic 16 f84a
porlmendi
 
PPTX
Lab.270910.instrucciones basicas del pic 16 f84a
porlmendi
 
PDF
Abc algoritmos
porJuan Carlos Avalo Gómez
 
DOCX
COMANDOS
porKarla Estefania Villanueva Epigmenio
 
PPTX
Lenguaje ensamblador (assembler)
porCarlos Guillén
 
PPT
Organizacion-de-la-unidad-central-de-procesamiento
porJosé Luis Olivares
 
Verilog-Intro.pdf
porAlfredoVargasRoque
 
I S A
porStefano Salvatori
 
DIGITALES EXPO lnes.pptxhh hh g gfdgh vbbvvguvgvhgvhg
porDiegoOjeda77
 
Tabla de instrucciones asembler
porEdwin David Toro Echeverria
 
Introduccion a Matlab
porOmar Yupanqui
 
TEMA 1.pdf
porBrianEstacio1
 
Matlab
porOmar Yupanqui
 
Clase 2
porManuel Felipe Villalba Miranda
 
Vhdl2
porDochen Lizama Trancer
 
Lista de raptor sus comandos y su función
porAna Ruth G H
 
Lenguajes máquina y ensamblador
porJose Bondia
 
Organizacion de la unidad central de procesamiento
porHarold Torres
 
MSX88 simulador assembly programación arquitectura de software.ppt
pormatias387621
 
Fundamentos de programación en scilab
porGabriel Romero
 
Lab.270910.instrucciones basicas del pic 16 f84a
porlmendi
 
Lab.270910.instrucciones basicas del pic 16 f84a
porlmendi
 
Abc algoritmos
porJuan Carlos Avalo Gómez
 
COMANDOS
porKarla Estefania Villanueva Epigmenio
 
Lenguaje ensamblador (assembler)
porCarlos Guillén
 
Organizacion-de-la-unidad-central-de-procesamiento
porJosé Luis Olivares
 

Transpar Tema1a

  • 1.
    INTRODUCCIÓN A VERILOGObjetivos comprender el uso de un HDL en el diseño de sistemas digitales estudiar Verilog como Lenguaje de Descripción de Hardware (HDL)
  • 2.
    Bibliografía J. Bhasker:“Verilog HDL synthesis: A practical primer”, Star Galaxy Publishing, 1998. E. Villar y P. Sánchez: “Síntesis”, Capitulo 4 de L. Terés, Y. Torroja, S. Olcóz y E. Villar: “VHDL: Lenguaje estándar de diseño electrónico”, McGraw-Hill, 1998. INTRODUCCIÓN A VERILOG
  • 3.
    SÍNTESIS AL NIVELDE TRANSFERENCIA ENTRE REGISTROS Simulación Lógica Arquitectura RT Circuito Lógico Posicionamiento Interconexión Síntesis RT-Lógica Implementación Retroanotación Simulación RT Optimización aritmética Identificación de elementos de memoria Codificación de tipos Extracción de las funciones lógicas Minimización Lógica
  • 4.
    NIVELES DE ABSTRACCIÓNModelo de Computación: Tiempo discreto Señal  transición activa de la señal de reloj Señal t Simulación RT
  • 5.
    NIVELES DE ABSTRACCIÓNModelo de Computación: eventos discretos Simulación dirigida por eventos Simulación Lógica Señal t Señal t transición activa de la señal de reloj Simulación RT
  • 6.
    NIVELES DE ABSTRACCIÓNventana de comparación corrección del diseño valores compatibles Simulación Lógica Señal t Señal t transición activa de la señal de reloj Simulación RT Señal t Simulación Lógica retroanotada transición activa de la señal de reloj tiempo de ‘ set-up’ periodo de reloj - tiempo de ‘set-up’ camino crítico ‘ X’ ‘ 1’ ‘ 1’
  • 7.
    SISTEMA DIGITAL ANIVEL RT Entradas de Control Entradas de Datos Salidas de Control Señales de Control Señales de Estatus Salidas de Datos Unidad de Control Unidad de Datos
  • 8.
    SISTEMA DIGITAL ANIVEL RT Lógica Combinacional de Control Registro de Estado reloj reset set Estado de Control próximo Estado de Control actual Salidas de Control Entradas de Control Señales de Control Señales de Estatus Lógica Combinacional y Unidades Operacionales Registros de Datos reloj reset set Datos próximos Valores actuales en registros Salidas de Datos Entradas de Datos
  • 9.
    VALORES LÓGICOS Interpretaciónen modelado y síntesis ‘ don’t care’ desconocido x tri-estado (‘don’t care’ en sentencias ‘case’) tri-estado z (?) ‘ 1’ lógico ‘ 1’ lógico 1 ‘ 0’ lógico ‘ 0’ lógico 0 síntesis simulación
  • 10.
    MÓDULO Entidad dediseño module Ejemplo (BpW, Error, Wait, Valid, Clear); input Error, Wait, Valid, Clear; output BpW; . . . endmodule Error BpW Wait Valid Clear Ejemplo
  • 11.
    TIPOS DE DATOSNodos de red (‘net data types’) wire Ax; // línea de un ‘bit’ wire [4:0] Dak; // agrupación de 5 líneas wire línea tri idéntico a ‘wire’ (sólo informa de múltiples drivers) supply0 y supply1 ‘ 0’ ‘ 1’
  • 12.
    TIPOS DE DATOSNodos de red (‘net data types’) wire Error BpW Wait Valid Clear module Ejemplo (BpW, Error, Wait, Valid, Clear); input Error, Wait, Valid, Clear; output BpW; wire BpW; assign BpW = Error&Wait; endmodule Ejemplo
  • 13.
    TIPOS DE DATOSNodos de red (‘net data types’) múltiples ‘drivers’ Error BpW Wait Valid Clear module Ejemplo (BpW, Error, Wait, Valid, Clear); input Error, Wait, Valid, Clear; output BpW; wire BpW; assign BpW = Error&Wait; assign BpW = Valid | Clear; endmodule Error&Wait 0101 Valid | Clear 0011 BpW 0xx1
  • 14.
    TIPOS DE DATOSNodos de red (‘net data types’) wor Error BpW Wait Valid Clear module Ejemplo (BpW, Error, Wait, Valid, Clear); input Error, Wait, Valid, Clear; output BpW; wor BpW; assign BpW = Error&Wait; assign BpW = Valid | Clear; endmodule Error&Wait 0101 Valid | Clear 0011 BpW 0111
  • 15.
    TIPOS DE DATOSNodos de red (‘net data types’) wor Error BpW Wait Valid Clear module Ejemplo (BpW, Error, Wait, Valid, Clear); input Error, Wait, Valid, Clear; output BpW; wor BpW; assign BpW = Error&Wait; assign BpW = Valid | Clear; endmodule
  • 16.
    TIPOS DE DATOSNodos de red (‘net data types’) wand Error BpW Wait Valid Clear module Ejemplo (BpW, Error, Wait, Valid, Clear); input Error, Wait, Valid, Clear; output BpW; wand BpW; assign BpW = Error&Wait; assign BpW = Valid | Clear; endmodule Error&Wait 0101 Valid | Clear 0011 BpW 0001
  • 17.
    TIPOS DE DATOSNodos de red (‘net data types’) wand Error BpW Wait Valid Clear module Ejemplo (BpW, Error, Wait, Valid, Clear); input Error, Wait, Valid, Clear; output BpW; wand BpW; assign BpW = Error&Wait; assign BpW = Valid | Clear; endmodule
  • 18.
    TIPOS DE DATOSRegistros reg Ax; // registro de un ‘bit’ reg [4:0] Dak; // registro de 5 ‘bits’ reg integer registros de hasta 32 ‘bits’ en complemento-2 la herramienta de síntesis debe sintetizar el tamaño mínimo wire [1:5] Brq, Rbu; integer Arb; . . . Arb = Brq + Rbu; . . . 6 + Brq Rbu Arb 5 5
  • 19.
    TIPOS DE DATOSConstantes 30 -2 decimal simple 32 ‘bits’ en complemento-2 formato con base 2’b10 6’d-4 ’d-10 [size]’base value base=h,H,o,O,b,B,d,D
  • 20.
    TIPOS DE DATOSParámetros constantes nominales parameter RED = -1, GREEN = 2; // constantes decimales (32 bits en complemento-2) parameter READY = 2’b01, BUSY = 2’b11, EXIT = 2’b10; // constantes de 2 ‘bits’
  • 21.
  • 22.
  • 23.
  • 24.
    SENTENCIAS DE ASIGNACIÓNAsignación continua assign Error Stop Start Wait Valid Clear module Ejemplo (Stop, Start, Error, Wait, Valid, Clear); input Error, Wait, Valid, Clear; output Stop, Start; wire Stop, Start; assign Stop = Error&Wait; assign Start = Valid | Clear; endmodule sentencias concurrentes Ejemplo
  • 25.
    SENTENCIAS DE ASIGNACIÓNAsignación continua retraso Error Stop Start Wait Valid Clear module Ejemplo (Stop, Start, Error, Wait, Valid, Clear); input Error, Wait, Valid, Clear; output Stop, Start; wire Stop, Start; assign #5 Stop = Error&Wait; assign #6 Start = Valid | Clear; endmodule retrasos ignorados en síntesis
  • 26.
    SENTENCIAS DE ASIGNACIÓNAsignación procesal module Ejemplo (Preset, Count); input [0:2] Preset; output [3:0] Count; reg [3:0] Count; always @ (Preset) begin . . . end endmodule sentencias secuenciales
  • 27.
    SENTENCIAS DE ASIGNACIÓNAsignación procesal asignación bloqueante module Ejemplo (Preset, Count); input [0:2] Preset; output [3:0] Count; reg [3:0] Count; always @ (Preset) Count = Preset + 1; endmodule Preset[2] Preset[1] Preset[0] Count[0] Count[1] Count[3] Count[2]
  • 28.
    SENTENCIAS DE ASIGNACIÓNAsignación procesal asignación no-bloqueante module Ejemplo (Preset, Count); input [0:2] Preset; output [3:0] Count; reg [3:0] Count; always @ (Preset) Count <= Preset + 1; endmodule Preset[2] Preset[1] Preset[0] Count[0] Count[1] Count[3] Count[2]
  • 29.
    SENTENCIAS DE ASIGNACIÓNAsignación procesal las asignaciones dobles a un mismo objeto son un error Count <= Preset + 1; . . . Count = Mask; los retrasos se ignoran #5 Count <= Preset + 1; . . . Count = #5 Mask; retrasos ignorados en síntesis
  • 30.
    OPERADORES Operadores lógicosexpresiones de conmutación module FullAdder (A, B, Carryin, Sum, Carryout); input A, B, Carryin; output Sum, Carryout; assign Sum = (A ^ B) ^ Carryin; assign Carryout = (A & B) | (B & Carryin) | (A & Carryin); endmodule xor ^ or | and & complemento ~ A B Carryin Carryout Sum
  • 31.
    OPERADORES Operadores aritméticosmultiplicación * división / módulo % substracción - suma + signo +, -
  • 32.
    OPERADORES Operadores aritméticosnet, reg: operaciones sin signo module UnsignedAdder (Arb, Bet, Lot); input [2:0] Arb, Bet; output [2:0] Lot; assign Lot = Arb + Bet; endmodule + Arb Bet Lot 3 3 3
  • 33.
    OPERADORES Operadores aritméticosinteger: operaciones con signo module SignedAdder (Arb, Bet, Lot); input [1:0] Arb, Bet; output [2:0] Lot; reg [2:0] Lot; always @ (Arb or Bet) begin : addition integer Arbint, Betint; Arbint = - Arb; Betint = Bet; Lot = Arbint + Betint; end endmodule Bet ‘ 1’ Arb + Lot + 2 3 3 2 3
  • 34.
    OPERADORES Operadores aritméticos‘ carry’ y ‘borrow’ module carryborrow (Arb, Bet, Lot); input [3:0] CdoBus; output [3:0] Sum; output [4:0] OneUp; output [3:0] ShortOneUp; output Bore; assign OneUp = CdoBus + 1; assign ShortOneUp = CdoBus + 1; assign (Bore, Sum) = CdoBus – 2; endmodule // OneUp[4] lleva el ‘carry’ // se pierde el ‘carry’ // Bore lleva el ‘borrow’
  • 35.
    OPERADORES Operadores relacionalesmayor o igual >= menor o igual <= menor < mayor >
  • 36.
    OPERADORES Operadores relacionalesnet, reg: comparaciones sin signo module GreatherThan (A, B, Z); input [3:0] A, B; output Z; assign Z = A[1:0] > B[3:2]; endmodule B A > Z
  • 37.
    OPERADORES Operadores relacionalesinteger: comparaciones con signo module SignedGreatherThan (ArgA, ArgB, ResultZ); input [2:0] ArgA, ArgB; output ResultZ; reg ResultZ; integer ArgAInt, ArgBInt; always @ (ArgA or ArgB) begin ArgAInt = - ArgA; ArgBInt = - ArgB; ResultZ = ArgAInt > ArgBInt; end endmodule ‘ 1’ ArgB ‘ 1’ ArgA + > + ResultZ
  • 38.
    OPERADORES Operadores relacionalesigualdad y desigualdad module NotEquals (A, B, Z); input [0:3] A, B; output Z; reg Z; always @ (A or B) begin : comparison integer IntA, IntB; IntA = A; IntB = B; Z = IntA !=IntB; end endmodule distinto != igual = A[0] B[0] Z A[1] B[1] A[2] B[2] A[3] B[3]
  • 39.
    OPERADORES Operadores dedesplazamiento desplazamiento lógico constante module ConstantShift (DataMux, Address); input [0:3] DataMux; output [0:5] Address; assign Address = (~ DataMux) << 2; endmodule desplazamiento derecha >> desplazamiento izquierda << DataMux[0] Address[0] DataMux[1] Address[1] DataMux[2] Address[2] DataMux[3] Address[3] Address[4] Address[5]
  • 40.
    OPERADORES Operadores dedesplazamiento desplazamiento lógico variable module VariableShift (MemDataReg, Amount, InstrReg); input [0:2] MemDataReg; input [0:1] Amount; output [0:2] InstrReg; assign InstrReg = MemDataReg >> Amount; endmodule MemDataReg[0] MemDataReg[1] MemDataReg[2] InstrReg[0] InstrReg[1] InstrReg[2] Amount[0] Amount[1]
  • 41.
    OPERADORES Operaciones convectores operaciones lógicas module LogicalVectorOperations (A, B, C, Z); input [0:3] A, B, C; output [0:3] Z; assign Z = (A & B) | C; endmodule C[0] B[0] A[0] Z[0] C[1] B[1] A[1] Z[1] C[2] B[2] A[2] Z[2] C[3] B[3] A[3] Z[3]
  • 42.
    OPERADORES Operaciones convectores selección de partes module Selection (A, B, RegFile, ZCat); input [3:0] A, B, RegFile; output [3:0] ZCat; assign ZCat[3] = A[2]; assign ZCat[2:1] = B[3:2]; assign ZCat[0] = RegFile[3]; endmodule A[2] B[3] B[2] RegFile[3] ZCat[3] ZCat[2] ZCat[1] ZCat[0]
  • 43.
    OPERADORES Operaciones convectores concatenación module Concatenation (A, B, RegFile, ZCat); input [3:0] A, B, RegFile; output [3:0] ZCat; assign ZCat[3:0] = {A[2], B[3:2], RegFile[3]}; endmodule A[2] B[3] B[2] RegFile[3] ZCat[3] ZCat[2] ZCat[1] ZCat[0]
  • 44.
    OPERADORES Operaciones convectores selección de ‘bit’ variable en fuente module SourceVariableSelection (Data, Index, Dout); input [0:3] Data; input [1:2] Index; output Dout; assign Dout = Data[Index]; endmodule Data[0] Data[1] Data[2] Data[3] 00 01 10 11 Dout Index[0] Index[1]
  • 45.
    OPERADORES Operaciones convectores selección de ‘bit’ variable en destino (no soportado por ISE) module TargetVariable Selection (Mem, Store, Addr); input Store; input [1:3] Addr; output [7:0] Mem; assign Mem[Addr] = Store; endmodule Mem[0] Mem[1] Mem[2] Mem[3] Mem[4] Mem[5] Mem[6] Mem[7] 000 001 010 011 100 101 110 111 Store Addr[0] Addr[1] Addr[2]
  • 46.
    OPERADORES Expresión condicional<condición> ? <expresión 1> : <expresión 2> module ConditionalExpression (StartXM, ShiftVal, Reset, StopXM); input StartXM, ShiftVal, Reset; output StopXM; assign StopXM = (! Reset) ? StartXM ^ ShiftVal : StartXM | ShiftVal ; endmodule 1 0 StartXM ShiftVal Reset StopXM
  • 47.
    COMPORTAMIENTO COMBINACIONAL descripciónde comportamiento código secuencial Sentencia ‘always’ module EvenParity (A, B, C, D, Z); input A, B, C, D; output Z; reg Z, Temp1, Temp2; always @ (A or B or C or D) begin Temp1 = A ^ B; Temp2 = C ^ D; Z = Temp1 ^ Temp2; end endmodule Z A B C D
  • 48.
    lista de sensibilidadlógica combinacional Sentencia ‘always’ module EvenParity (A, B, C, D, Z); input A, B, C, D; output Z; reg Z; always @ (A or B) begin Z = A ^ B ^ C ^ D; end endmodule COMPORTAMIENTO COMBINACIONAL Z A B C D
  • 49.
    Condición COMPORTAMIENTO COMBINACIONALmodule Condition (StartXM, ShiftVal, Reset, StopXM); input StartXM, ShiftVal, Reset; output StopXM; reg StopXM; always @ (StartXM or ShiftVal or Reset) begin if (Reset) StopXM = StartXM | ShiftVal ; else StopXM = StartXM ^ ShiftVal ; end endmodule 1 0 StartXM ShiftVal Reset StopXM
  • 50.
    Selección COMPORTAMIENTO COMBINACIONALmodule ALU (Op, A, B, Z); input [1:2] Op; input [0:1] A, B; output [0:1] Z; reg [0:1] Z; parameter ADD = 'b00, SUB = 'b01, MUL = 'b10, AND = 'b11; always @ (Op or A or B) begin case (Op) ADD: Z = A + B; SUB: Z = A - B; MUL: Z = A * B; DIV: Z = A / B; endcase endmodule A Z B +/- * Op[1] Op[2] 00 01 10 11
  • 51.
    Selección COMPORTAMIENTO COMBINACIONALmodule CaseExample (DayOfWeek, SleepTime); input [1:3] DayOfWeek; output [1:4] SleepTime; reg [1:4] SleepTime; parameter MON = 0, TUE = 1, WED = 2, THU = 3, FRI = 4, SAT = 5, SUN = 6; always @ (DayOfWeek) begin case (DayOfWeek) MON, TUE, WED, THU: SleepTime = 6; FRI : SleepTime = 8; SAT : SleepTime = 9; SUN : SleepTime = 7; default SlepTime = 10; endcase end endmodule 000 001 010 011 100 101 110 111 DayOfWeek[1] DayOfWeek[2] DayOfWeek[3] SleepTime[1] SleepTime[2] SleepTime[3] SleepTime[4]
  • 52.
    Selección con ‘z’como ‘don´t care’ COMPORTAMIENTO COMBINACIONAL module CasezExample (ProgramCounter, DoCommand); input [0:3] ProgramCounter; output [0:1] DoCommand; reg [0:1] DoCommand; always @ (ProgramCounter) begin casez (ProgramCounter) 4’bzzz1: DoCommand = 0; 4’bzz10: DoCommand = 1; 4’bz100: DoCommand = 2; 4’b1000: DoCommand = 3; default DoCommand = 0; endcase end endmodule ProgramCounter[0] ProgramCounter[1] ProgramCounter[2] ProgramCounter[3] DoCommand[0] DoCommand[1]
  • 53.
    Selección con ‘z’y ‘x’ como ‘don´t care’ COMPORTAMIENTO COMBINACIONAL module CasexExample (ProgramCounter, DoCommand); input [0:3] ProgramCounter; output [0:1] DoCommand; reg [0:1] DoCommand; always @ (ProgramCounter) begin casex (ProgramCounter) 4’bxxx1: DoCommand = 0; 4’bzz10: DoCommand = 1; 4’bz100: DoCommand = 2; 4’b1000: DoCommand = 3; default DoCommand = 0; endcase end endmodule ProgramCounter[0] ProgramCounter[1] ProgramCounter[2] ProgramCounter[3] DoCommand[0] DoCommand[1]
  • 54.
    Orden de selecciónCOMPORTAMIENTO COMBINACIONAL codificador de prioridad module CasexExample (ProgramCounter, DoCommand); input [0:3] ProgramCounter; output [0:1] DoCommand; reg [0:1] DoCommand; always @ (ProgramCounter) begin casex (ProgramCounter) 4’bxxx1: DoCommand = 0; 4’bxx1x: DoCommand = 1; 4’bx1xx: DoCommand = 2; 4’b1xxx: DoCommand = 3; default DoCommand = 0; endcase end endmodule ProgramCounter[0] ProgramCounter[1] DoCommand[0] DoCommand[1] ProgramCounter[2] ProgramCounter[3]
  • 55.
    Orden de selecciónCOMPORTAMIENTO COMBINACIONAL codificador de prioridad module CasexExample (ProgramCounter, DoCommand); input [0:3] ProgramCounter; output [0:1] DoCommand; reg [0:1] DoCommand; always @ (ProgramCounter) begin if (ProgramCounter[3]) DoCommand = 0; else if (ProgramCounter[2]) DoCommand = 1; else if (ProgramCounter[1]) DoCommand = 2; else if (ProgramCounter[0]) DoCommand = 3; else DoCommand = 0; end endmodule ProgramCounter[0] ProgramCounter[1] DoCommand[0] DoCommand[1] ProgramCounter[2] ProgramCounter[3]
  • 56.
    Lazos COMPORTAMIENTO COMBINACIONAL‘ while’ ‘ forever’ ‘ repeat’ ‘ for’ no soportada en síntesis no soportada en síntesis no soportada en síntesis
  • 57.
    Lazos COMPORTAMIENTO COMBINACIONAL‘ for’ module DeMultiplexer (Address, Data, Line); input [1:0] Address; input Data; output [3:0] Line; reg [3:0] Line; integer J; always @ (Address) for (J = 3; J >= 0; J = J – 1) if (Address == J) Line[J] = Data; else Line[J] = 0; endmodule Address[1] Address[0] Line[3] Line[2] Line[1] Line[0] Data
  • 58.
    Lazos COMPORTAMIENTO COMBINACIONAL‘ for’ module DeMultiplexer (Address, Line); input [1:0] Address; output [3:0] Line; reg [3:0] Line; integer J; always @ (Address) if (Address == 3) Line[J] = Data; else Line[J] = 0; if (Address == 3) Line[J] = Data; else Line[J] = 0; if (Address == 3) Line[J] = Data; else Line[J] = 0; if (Address == 3) Line[J] = Data; else Line[J] = 0; endmodule Address[1] Address[0] Line[3] Line[2] Line[1] Line[0] Data
  • 59.
    Condición LÓGICA COMBINACIONALtoda señal o variable o es asignada bajo cualquier condición de ejecución del proceso, o es utilizada después de ser asignada module NonCombinationalLogic (A, B, C, Z); input A, B, C; output Z; reg Z; always @ (A or B or C) begin : VAR_LABEL reg D; if (! A) Z = D; else begin D = B & C; Z = 1; end end endmodule module NonCombinationalLogic (A, B, C, Z); input A, B, C; output Z; reg Z; always @ (A or B or C) begin : VAR_LABEL reg D; D = B & C; if (! A) Z = D; end endmodule
  • 60.
    COMPORTAMIENTO COMBINACIONAL module DeMultiplexer (Address, Data, Line); input [1:0] Address; input Data; output [3:0] Line; reg [3:0] Line; integer J; always @ (Address) for (J = 3; J >= 0; J = J – 1) if (Address == J) Line[J] = Data; endmodule Condición toda señal o variable o es asignada bajo cualquier condición de ejecución del proceso, o es utilizada después de ser asignada
  • 61.
    Condición LÓGICA COMBINACIONALtoda señal o variable o es asignada bajo cualquier condición de ejecución del proceso, o es utilizada después de ser asignada module CombinationalLogic (A, B, C, Z); input A, B, C; output Z; reg Z; always @ (A or B or C) begin : VAR_LABEL reg D; if (! A) Z = 1; else begin D = B & C; Z = D; end end endmodule B C A Z
  • 62.
    Condición LÓGICA COMBINACIONALtoda señal o variable o es asignada bajo cualquier condición de ejecución del proceso, o es utilizada después de ser asignada module CombinationalLogic (A, B, C); input A, B, C; output Z; reg Z; always @ (A or B or C) begin : VAR_LABEL reg D; D = B & C; if (! A) Z = D; else Z = 1; end endmodule B C A Z
  • 63.
    Tareas LÓGICA COMBINACIONALencapsulado de lógica combinacional module FunctionCall (XBC, DataIn); input [0:5] DataIn; output [0:2] XBC; reg [0:2] XBCTemp; task CountOnes; input [0:5] A; output [0:2] B; integer K; begin B = 0; for (K = 0; K <= 5; K = K+1) if (A[K]) B = B + 1; end ; endtask always @ (DataIn) CountOnes(DataIn, XBCTemp); assign XBC = XBCTemp; endmodule + + + DataIn[0] DataIn[1] DataIn[2] DataIn[3] DataIn[4] DataIn[5] XBC

Notas del editor

  • #2 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #3 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #4 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #5 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #6 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #7 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #8 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #9 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #10 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #11 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #12 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #13 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #14 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #15 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #16 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #17 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #18 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #19 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #20 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #21 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #25 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #26 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #27 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #28 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #29 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #30 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #31 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #32 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #33 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #34 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #35 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #36 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #37 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #38 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #39 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #40 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #41 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #42 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #43 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #44 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #45 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #46 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #47 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #48 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #49 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #50 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #51 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #52 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #53 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #54 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #55 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #56 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #57 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #58 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #59 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #60 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #61 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #62 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #63 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages
  • #64 [This slide can only be viewed in slide show mode and to control the image please right click over the image. You can then rewind, play or loop the image]. As a starting point I just want to provide a general context for our discussions, managed design evolution…not revolution . In this slide I’m showing the natural stages of design evolution, not design revolution but the next logical step in EDA. In the 80s we designed electronics using Schematic Capture. We dealt with 10,000s of gates and then at the end of the 80s and moving into the 90s, devices grew in size to 100,000s of gates and design complexity increased. So HDLs were developed to deal with this complexity and increase in silicon real estate. Now as we move into the new millennium, just as HDLs were developed to deal with increasing complexity and size, so HLLs have been developed to deal with multi-million gate designs and increasing design complexity. Moreover the integration of logic with off-chip or off chip CPU has increased complexity and it now makes more sense to deal with these types of design using a methodology that shares a common language base for the hardware and software. BUT Just as HDLs did not make Schematic Capture redundant, neither will HLLs make HDLs redundant. They are another design alternative for the designer, to be deployed where it makes sense. It’s also important that the next wave of design complements and has a neat fit with current design flows, tools and languages