This document summarizes research on 3D network-on-chip architectures. It begins by introducing the benefits of 3D integrated circuits for reducing wire lengths and improving performance. It then surveys several existing 3D NoC architectures: 1) Symmetric NoC which treats intra-layer and inter-layer hops identically, incurring high overhead. 2) NoC-Bus Hybrid which uses a bus for single-hop vertical links to reduce hops. 3) Ciliated 3D Mesh which restricts switches to layers and adds cores per switch, lowering bandwidth. 4) True 3D NoC Router which embeds vertical links directly in crossbars for seamless routing. The

1. Research and Practices on 3D Networks-on-Chip Architectures
Amir-Mohammad Rahmani1,2, Khalid Latif1,2, Pasi Liljeberg1, Juha Plosila1, Hannu Tenhunen 1,2
University of Turku, Finland1. Turku Centre for Computer Science (TUCS), Finland2.
{amir.rahmani, khalid.latif, pasi.liljeberg, juha.plosila, hannu.tenhunen}@utu.fi
Abstract-To continue the growth of the number of needed. In the last few years, there have been many efforts in
transistors on a chip, the 3D IC practice, where multiple interconnection network designs for 3D stacked CMPs. The
silicon layers are stacked vertically, is emerging as a purpose of this survey is to clarify the 3D NoC concept and to
revolutionary technology. Partitioning a larger die into map the scientific efforts made into the area of architectural and
smaller segments and then stacking them in a 3D topological optimizations in NoC research. We will identify
integration can significantly reduce latency and energy general trends and explain a range of issues which are important
consumption. Such benefits emanate from the notion that for designing efficient 3D NoC architectures. Moreover, this
inter-wafer distances are negligible compared to intra-wafer survey highlights the significance of difference network
distances which substantially reduce global wiring length in characteristics (e.g. power dissipation, thermal issues, etc) in
3D chips. This progress has introduced novel architectures on-chip networks, and brings valuable insights and comparisons
and new challenges for high-performance power-aware of different existing architectures in the area of 3D on-chip
design exploration. In this paper, we outline the network designs.
opportunities and challenges associated with three- The rest of this paper is organized as follows: Section II
dimensional networks-on-chip architectures, under covers basics and developments pertinent to 3D integrated
consideration for different design metrics. In this context, circuits technologies. Section III provides details of the existing
we categorize and present several alternatives for 3D NoC research and practices on 3D Networks-on-Chip designs and
architectures and we investigate and summarize the impact presents the impact of existing architecture on different system
of these architectures on various system characteristics. characteristics, while Section IV summarizes the survey.
I. I NTRODUCTION II. T HREE - DIMENSIONAL N ETWORKS - ON -C HIP
Communication plays a crucial role in the design and In the last few years, there have been many efforts to design
performance of multi-core systems-on-chip (SoCs). Recently and fabricate 3D ICs for different applications. The designs
on-chip transistor density has been considerably increased and include a NAND Flash using double stack S3 technology [17]
this enables the integration of dozens of components on a single form Samsung [18], 3D-OTP memory from Matrix [19], the
die. One outcome of greater integration is that interconnection DARPA 3D IC project [20] from MIT Lincoln Laboratories,
networks have started to replace shared buses. Networks-on- and also IBM [21] and Tezzaron [22] recent projects. These 3D
chip (NoCs) [1][2] are proposed to be used in complex SoCs for integrated circuits have emerged to overcome the limitations of
communication between cores because they scale better than interconnect scaling [23] by stacking active silicon layers
traditional forms of on-chip interconnections, and have better [24][25]. Compared with traditional 2D design, 3D ICs offer a
performance and power consumption characteristics [2]. The number of advantages: such as shorter global interconnects,
design of 2D NoCs has been examined from various aspects, higher performance, lower interconnect power consumption due
such as performance, power and reliability [3][4][5][6][7][8] to wire-length reduction, higher packing density and smaller
and some commercial products already deploy such networks footprint, and support for the implementation of mixed-
[9][10]. The advent of three-dimensional (3D) stacked technology chips [29][30]. In this context, several 3D designs
technologies provides a new horizon for on-chip interconnect have appeared recently. This section gives a brief introduction
design. 3D ICs, which contain multiple layers of active devices, on the exploration of possible technologies
have the potential for enhancing system power/performance Several vertical interconnect technologies have been
characteristics [11][12][13][14][15]. 3D ICs allow for explored, including wire bonding, microbump, contactless
performance enhancements even in the absence of scaling (capacitive or inductive), and through-silicon-via (TSV) vertical
[12][16]. This is because of the reduced length of interconnects. interconnect [13]. Among several 3D integration technologies,
Besides this clear benefit, package density is increased TSV is the most promising one, hence the majority of 3D
significantly, power is reduced due to shorter wires, and integration R&D activities concentrate on this approach [23].
circuitry is more immune to noise [12]. The power/performance Utilizing 3D design offers increased bandwidth [33] and
improvement arising from the architectural advantages of NoCs reduced length of average interconnection wire [34], which
will be significantly enhanced if 3D ICs are adopted as the basic results in a considerable saving in overall power consumption.
fabrication methodology. The amalgamation of two emerging It has been also demonstrated that a 3D design can be utilized to
paradigms, NoC and 3D IC, allows for the creation of new improve reliability [35]. However, the adoption of a 3D
structures that enable significant performance enhancements integration technology faces the challenges of increasing chip
over more traditional solutions. With freedom in the third temperature due to increasing power density compared to a
dimension, architectures that were prohibitive due to wiring planar 2D design [36]. In this context, several techniques have
constraints in 2D ICs are now possible, and many 3D been proposed in 3D architectures such as physical design
implementations can outperform their 2D counterparts [11]. optimization through intelligent placement [37], increasing
Even though both 3D integrated circuits and NoCs are thermal conductivity of the stack through insertion of thermal
proposed as alternatives for the interconnect scaling demands, vias [36], and use of novel cooling structures [38]. In addition, a
there are several challenges of combining both approaches to recent work reveals that in placement of the processing cores in
design three-dimensional NoCs such as only a few a 3D chip, the areal power density is the more significant design
commercially available EDA tools and lack of design constraint [39]. Consequently, thermal concern can be managed
methodologies, high peak temperatures, increased power as long as components with high power density are not stacked
densities and large area footprints of vertical interconnects. To on top of each other. To prevent severe thermal problems,
address these issues new architectures and design methods are architectures that stack memory on top of processor cores, or
978-1-4244-8971-8/10$26.00 c 2010 IEEE

2. those that rely on low-power processor cores have been However, despite this encouraging result, there is an
developed [40]. It should be noted at this point that increased opposite side of the coin which paints a rather bleak picture,
temperatures increase wire resistances, and consequently the because the bus approach also suffers from a following
interconnect delays [41]. drawback. Since the bus is a shared medium, it does not allow
concurrent communication in the third dimension. Therefore, in
III. 3D A RCHITECTURES high network loads, probability of contention and blocking
Recently, various architectures were proposed for 3D NoCs critically increases. As result of this, there is a considerable
which have different impacts on design metrics. This part is degradation in inter-layer bandwidth despite single-hop vertical
concerned with the existing architectures for 3D NoC design communication does improve performance in terms of overall
and reviews their influences on different system characteristics. latency.
i. S YMMETRIC N OC A RCHITECTURE iii. C ILIATED 3D M ESH A RCHITECTURE
In order to integrate many nodes into a 3D chip, simplest Another proposed method of constructing a 3D NoC is by
approach is to group the nodes into multiple layers and basically adding layers of functional IP blocks and restricting the
stack them on top of each other as shown in Figure 1(a), which switches to one layer or a small number of layers. In this
shows 3 layers stacked together, each with 9 nodes, totaling 27 context, Feero et al. [11], introduce new architecture called
nodes. We call this architecture a 3D Symmetric NoC, since ciliated 3D Mesh. This structure is essentially a 3D Mesh
both intra- and inter-layer movement bear identical network with multiple IP blocks per switch. For the ciliated 3D
characteristics: hop-by-hop traversal. Despite of simplicity, this Mesh, a 3 × 3 × 3 3D Mesh network with three IPs per switch,
architecture has two major inherent drawbacks. Firstly, it does is shown in Figure 1(c). In a ciliated 3D Mesh network, each
not exploit the beneficial attribute of a negligible inter-wafer switch contains at most 5+k ports (one for each cardinal
distance (around 50 μm per layer) in 3D chips [42]. Since direction, two for up and down (one either up or down in two-
traveling in the vertical dimension is multi-hop, it takes the layer 3D mesh), and one to each of the k IP blocks. In
same time as moving within the layer. In this architecture, inter- consequence of multiple IP cores per switch and diminished
layer and intra-layer hops are indistinguishable, in spite of the connectivity this architecture presents lower overall bandwidth
average number of hops between a source and a destination compared to a symmetric 3D Mesh. Nonetheless, it was shown
does decrease as a result of folding a 2D design into multiple that this type of network offers an advantage in terms of energy
stacked layers. In addition, buffering and arbitration delay of dissipation, especially in the presence of specific traffic
each flit at every hop, add to the overall delay for routing within patterns.
the layer. Secondly, a larger 7×7 crossbar is obligated as a result
of two extra ports. According to [42], crossbars scale upward iv. T RUE 3D N OC ROUTER
very inefficiently and it can be seen from their reported results Concerning with drawbacks of the preceding architectures,
that compared with 5×5 crossbar, a 6×6 crossbar consumes the implementation of a true 3D crossbar with the target of
about 21% more power, and the power consumption of a 7×7 seamless integration of the vertical links in the overall router
crossbar is approximately 2.24 times more than the 5×5 operation, can be desirable. Based upon this envision, in [42] an
counterpart. Thus, 3D Symmetric NoC implementation is a efficient router structure was offered, the illustration of such a
somewhat naive extension to the baseline 2D network because 3D crossbar layout can be seen from Figure 1(d). It should be
of its excessive area and power overhead. noted that the traditional definition of a crossbar - in the context
of a 2D physical layout - is a switch in which each input is
ii. 3D N OC-B US H YBRID ARCHITECTURE connected to each output through a single connection point.
One of the main characteristics of a 3D IC is the short However, extending this definition to a physical 3D structure
interlayer distances [13]. In order to take advantage of this would imply a switch of enormous complexity and size (given
applicable attribute, 3D NoC-Bus Hybrid architecture was the increased numbers of input- and output port pairs associated
proposed that is a hybrid between packet-switched network and with the various layers). In this architecture a simpler structure
a bus. Accordingly, with the potential of utilizing this benefit, a was chosen which can accommodate the connection of an input
symmetric NoC architecture with multi-hop communication in to an output port through more than one connection points.
the inter-layer dimension is not efficient. In this architecture, The vertical links are embedded in the crossbar and extend
given the very small inter-layer distance, single-hop to all layers. This implies the use of a 5×5 crossbar, since no
communication is, in fact, feasible. As can be seen from Figure additional physical channels need to be dedicated for interlayer
1(b), the NoC router can be hybridized with a bus link in the communication. Interconnection between the various links in a
vertical dimension to create a 3D NoC-Bus Hybrid structure. 3D crossbar would have to be provided by dedicated connection
This approach was first used in a 3D NUCA L2 Cache for boxes at each layer. These connecting points can facilitate
CMPs [43]. This hybrid system provides both performance and linkage between vertical and horizontal channels, allowing
area benefits. It requires a 6×6 crossbar, since the bus adds a flexible flit traversal within the 3D crossbar. The improved
single additional port to the generic 2D 5×5 crossbar and architecture (particularly on crossbar structure) of the True 3D
compared to 7×7 crossbar in symmetric architecture, it is less NoC router called DimDe has been proposed which reveals the
power-hungry and occupies less area. The additional link forms rather enhanced energy-delay product characteristic [42].
the interface between the NoC domain and the bus domain. The Despite this encouraging result, there are some important
bus link has its own dedicated queue, which is controlled by a drawbacks. Adding a large number of vertical links in a 3D
central arbiter. Flits from different layers wishing to move crossbar to increase NoC connectivity leads to increased path
up/down should arbitrate for access to the shared medium. diversity and means multiple possible paths between source and
Furthermore, each bus has only a small number of nodes, destination pairs, and actually leads to a dramatic increase in the
keeping overall capacitance on the bus small and considerably complexity and power consumption of the central arbiter.
simplifying bus arbitration.

3. Figure 1. NoC architectures. (a) Three-Dimensional mesh. (b) NoC-Bus Hybrid mesh (c) Ciliated 3D mesh (d) NoC routers with true 3D crossbars
v. T REE -B ASED 3D N OC S viii. D E-BRUIJN G RAPH -B ASED 3D N OC
Butterfly fat tree (BFT) [44], [45] and the generic fat tree, or Architectures like typical 3D mesh, ciliated 3D mesh or tree
SPIN [46] are the two types of tree-based interconnection based 3D NoC have a common disadvantage: the large network
networks that have been considered for NoC applications. latency because of large network diameter of mesh topology. In
According to [11], considerable enhancements can be achieved [49], Chen et al. propose a novel 3D NoC architecture based on
when these networks are instantiated in a 3D IC environment. De-Bruijn graph. The De-Bruijn topology is an efficient
Unlike the work with mesh-based NoCs, any new topologies for topology for parallel processing purposes. The advantages of
tree-based systems were not proposed. Instead, they present the De-Bruijn graph network topology are small diameter, high
achievable performance benefits by instantiating already- connectivity and high reliability [50]. The degree of NoC based
existing tree-based NoC topologies in a 3D environment. on De-Bruijn graph does not change with an increase in the size
It can be concluded from their reported results that when the of network.
2D BFT network is mapped onto a multi-layer 3D SoC, wire This architecture benefits from a simple routing algorithm.
routing becomes simpler, and the longest interswitch wire The De-Bruijn architecture provides better throughput
length is reduced by at least a factor of two, in comparison with performance as compared to the 3D mesh NoC because of
the one-layer 2D implementation. This will lead to reduced shorter diameter. On other hand, the solution is not power
energy dissipation as well as smaller area overhead. They argue efficient as compared to the 3D mesh NoC because shorter
that the fat tree topology will have the same advantages when route cannot be achieved in most cases. The proposed topology
mapped onto a 3D IC as the BFT. is shown in Figure 2(a).
vi. XN O TS 3D N OC ix. S ERIALIZED V ERTICAL C HANNEL 3D N OC
To make the best utilization of the short delay and high In 3D ICs, vertical TSVs take significant chip area because
density of inter-wafer links, Xbar-connected Network-on-Tiers of their typically spread-out distribution. Pasricha [51]
(XNoTs), which consist of multiple network layers tightly proposes the serialization of vertical TSV interconnects to
connected via crossbar switches, is proposed by Matsutani et al. reduce their area footprint and avoid the routing congestion of
[47]. XNoTs-based architectures have crossbar switches that interconnects. Such serialization can lead to a better thermal
connect different layers and their cores, in such a way that the TSV distribution resulting in lower peak temperatures. The
2D topology on every layer can be independently customized so extra space made available on each layer due to serialization
as to meet the cost-performance requirements, as far as network can be used for efficient core layout across multiple layers and
connectivity is at least guaranteed with the bottom layer. The routing, as well as more efficient thermal TSV insertion for
architecture is not power-efficient, because it requires large temperature management. Such area savings and other benefits
vertical switches. come at the cost of nominal power and performance overhead.
Author has presented the impact on performance with
vii. MIRA 3D N OC varying degrees of serialization. The performance degradation
Park et al. [48] propose a Multi-layered on-chip Interconnect is about 1.7% on average for various applications for 4:1
Router Architecture (MIRA), which is based on implementing a serialization (64 à 16 wires) but reaches around 16.1% for 64:1
2D mesh chip-multiprocessor in three dimensions. Unlike the serialization (64 à 1 wire). Performance degradation depends
explained 3D routers, MIRA is a 3D stacked NoC router on the frequency of vertical transfers as well. The lower degrees
architecture which is stacked into multiple layers and optimized of serialization like 4:1 or 2:1 are more practical because of
to reduce the overall area requirements and power consumption. smaller degradations in performance and lower power
The major drawback of the architecture is that it assumes the consumption overhead but significantly reducing the footprint
processor cores are designed in 3D. This makes it difficult to area.
reuse existing highly optimized 2D processor core designs.

4. congested and other layers have very light load, the system is
x. H ONEYCOMB 3D N OC not power and performance efficient.
For a topology design, there is always a tradeoff between Ramanujam et al. [54] present an efficient Layer-
degree and diameter. The degree refers to the hardware cost. Multiplexed (LM) 3D architecture for vertical communication
Mesh and torus are the main stream topologies because of their with the consideration of load balancing. More precisely, the
high regularity, symmetry and scalability but with extra layer-multiplexed architecture replaces the one-layer-per-hop
hardware cost (degree). Yin et al. [52] propose the honeycomb routing in a conventional 3D mesh with simpler vertical de-
interconnect topology as an alternative for NoC based designs. multiplexing and multiplexing stages. There are two major
Honeycomb topology reduces the network cost significantly, drawbacks for the proposed architecture. First is to traverse
while maintaining the positive characteristics of typical mesh packets through two stage crossbar, which makes it less
and torus topologies. power and area efficient. Second is to use two hops per
For regular mesh and torus topologies in two dimensional packet for vertical communication, which makes the
domains, the honeycomb mesh and torus provide an architecture less throughput efficient. On the other hand,
approximate 40% reduction in terms of network cost. Smaller reduced degree of router and layer load balancing compensates
network degree for honeycomb topology makes the router the power degradation.
architecture simpler, reliable and power efficient. The 3D
honeycomb mesh topology with network degree ‘5’ is shown in xiii. BBVC-3D-N OC
Figure 2(b). To further reduce the network cost, vertical links In 3D NoCs, as the number of cores increases in each layer
can be removed by systematically bi-partitioning of the routers to support increasing application complexity, the amount of
into odd and even groups. The authors present the deadlock free communication between layers is also expected to grow, and
routing algorithm for 3D honeycomb topology as well. consequently the number of interconnect TSVs will get higher.
Since each TSV requires a pad for bonding to a wafer layer, the
xi. L OW-R ADIX 3D N OC area footprint of TSVs in each layer is no longer negligible. As
The key problem faced by current 3D stacking technology is discussed before, serialization of vertical TSV interconnects is
that only vertical inter-layer links are allowed. Due to which, proposed as a way to reduces the interconnect TSV footprint.
the direct connection between arbitrary nodes located at However, it degrades the performance due to serialization
different layers is not allowed. In case of 3D NoC architectures, overhead and low bandwidth utilization.
the system design is highly constrained by the complexity and In [55], Rahmani et al. explore a mechanism to reduce TSV
power of routers and links. Thus, the low radix routers are area footprint, and thus improving 3D IC cost, routability,
preferred due to lower power consumption and better heat thermal efficiency, and power consumption. Specifically, they
dissipation. This makes the latency value higher due to high hop propose a novel technique to replace the pair of unidirectional
counts in network paths. vertical channels between layers by a bidirectional channel that
Xu et al. [53] present an efficient network topology for 3D is dynamically self-reconfigurable to be used in either out-going
NoCs by using the long range links. As shown in Figure 2(c), or incoming direction. To compensate the bandwidth
utilization of long-range links makes the topology low diameter degradation, they exploit the low-latency nature of vertical
but requires only low-radix routers to implement. The long TSVs by establishing high-speed inter-layer communication
range links show significant reduction in latency even for the using mixed-clock FIFOs. Figure 2(d) shows the schematic
higher operating frequency and pipelined wires. The increase in representation of their proposed Bidirectional Bisynchronous
power consumption is sub-linear to the increase in length. The Vertical Channels (BBVC) -based NoC. The main idea of the
authors present an optimal operating frequency of 1GHz for 3D proposed 3D NoC system is to exploit a bidirectional channel
NoCs because higher clock frequency for 3D chip brings the for inter-layer communication operating at a higher frequency
concern of high heat dissipation. compared to intra-layer communication (f 2>f1) and being
xii. L AYER -M ULTIPLEXED 3D N OC capable of dynamically changing the channel direction between
As discussed above, architectures like 3D NoC-Bus hybrid routers in neighboring layers based on the real time need of
can reduce the network cost, but there are some other bandwidth. The BBVC-3D-NoC can cope with the major
performance bottlenecks like bus bandwidth limitations. inherent drawbacks of the 3D symmetric NoC architecture by
Another issue is the layer load-balancing. If one layer is exploiting the beneficial attribute of a negligible inter-wafer

5. distance in 3D chips. In addition, BBVCs are only responsible IV. SUMM ARY
for inter-layer communication. In other words, the proposed
inter-layer communication scheme is independent of the intra- Recently, Networks-on-Chip architectures have gained
layer topology. The main disadvantage of the BBVC-3D-NoC popularity to address the interconnect delay problem for
is that it does not support bus-based vertical communication, designing on-chip multi-core systems in deep sub-micron
technology. However, almost all prior studies have focused on
thus communication on vertical dimension is not single hop.
2D NoC designs. Since three dimensional (3D) integration has
xiv. S PECIAL PURPOSE 3D N OC S emerged to mitigate the interconnect delay and power problem,
Design of 3D SoCs satisfying the application performance exploring the NoC design space in 3D can provide ample
requirements with minimum power consumption, while opportunities to design high performance and energy-efficient
satisfying the 3D technology constraints is a big challenge. A NoC architectures. In this survey, we have given an overview of
synthesis based power-performance efficient design approach the existing architecture for 3D NoC and highlighted their
for 3D NoCs can deal with such issues. impact on network characteristics. We have first stated the
Seiculescu et al. [56] present a tool for NoC topology motivation for 3D NoC and given an introduction of the basic
synthesis for 3D ICs named SunFloor 3D. Path computation, concepts. Furthermore, we investigate various architectural
assignment and placement of network elements in 3D layers are alternatives for designing a high-performance and energy-
also the tasks for the tool. The separate algorithms for core to efficient 3D NoC system. We have demonstrated that besides
switch connectivity and path computation are presented with the reducing the footprint in a fabricated design, 3D network
corresponding constraints. The comprehensive comparison structures provide better power consumption and performance
between 2D and 3D NoCs is also presented, which shows that characteristics compared to traditional, 2D NoC architectures.
3D integration can significantly reduce the latency and power We have demonstrated that most NoC architectures are capable
consumption as compared to the 2D interconnects. The of achieving better power/performance when instantiated in a
topologies produced by SunFloor tool show significant power 3D IC environment compared to more traditional 2D
and latency savings as compared to the standard topologies. implementations. The pros and cons of the analyzed structures
Similar approach has been adopted by [57]. are concisely summarized and reported in Table 1.

6. V. REFERENCES [30] G. De Micheli and L. Benini. Networks on Chips. Morgan Kaufmann, San
Francisco, CA, 2006.
[1] L. Benini, and G. D. Micheli, “Networks on chips: a new SOC paradigm,” [31] D. Shamik et al., "Technology, performance, and computer-aided design of
IEEE Computer, Vol. 35, No. 1, 2002, pp. 70–78. three-dimensional integrated circuits," in Proc. of the International
[2] W. J. Dally, and B. Towles, “Route Packets, Not Wires: On-Chip Symposium on Physical design, 2004, pp. 108-115.
Interconnection Networks,” in Proc. of Design Automation Conference, [32] P. Morrowet al., "Wafer-Level 3D Interconnects Via Cu Bonding," in Proc.
2001, pp. 684–689. of the 21st Advanced metallization Conference, 2004, pp. 125-130.
[3] J. Kim et al., “A Gracefully Degrading and Energy-Efficient Modular Router [33] C. C. Liu et al., "Bridging the processor-memory performance gap with 3D
Architecture for On-Chip Networks,” in Proc. of 33rd International IC technology," Design & Test of Computers, Vol. 22, No. 6, 2005, pp. 556-
Symposium on Computer Architecture, 2006, pp. 4–15. 564.
[4] R. Mullins et al., “Low-Latency Virtual-Channel Routers for On-Chip [34] J. W. Joyner et al., "A stochastic global netlength distribution for a three-
Networks,” in Proc. of 31st International Symposium on Computer dimensional system-on-a-chip (3D-SoC)," in Proc. of the International
Architecture, 2004, pp. 188-198. ASIC/SOC Conference, 2001, pp. 147-151.
[5] S. Heo and K. Asanovic, “Replacing global wires with an on-chip network: a [35] N. Madan and R. Balasubramonian, "Leveraging 3D Technology for
power analysis,” in Proc. of the International Symposium on Low power Improved Reliability," In Proc. of International Symposium on
electronics and design, 2005, pp. 369–374. Microarchitecture, 2007, pp. 223-235.
[6] R. Kumar et al., “Interconnections in multi-core architectures: [36] J. Cong and Y. Zhang, “Thermal via planning for 3-D ICs,” in Proc. of the
Understanding mechanisms, overheads and scaling,” in Proc. of the 32nd 2005 IEEE/ACM International Conference on Computer-aided design, 2005,
International Symposium on Computer Architecture, 2005, pp. 408–419. pp. 745–752.
[7] L. Shang et al., “Thermal Modeling, Characterization and Management of [37] B. Goplen and S. Sapatnekar, “Efficient thermal placement of standard cells
On-Chip Networks,” in Proc. of the 37th International Symposium on in 3D ICs using a force directed approach,” in Proc. of International
Microarchitecture, 2004, pp. 67-78. Conference on Computer Aided Design, 2003, pp. 86–89.
[8] R. Marculescu, “Networks-On-Chip: The Quest for On-Chip Fault-Tolerant [38] B. Dang et al., “Wafer-level microfluidic cooling interconnects for GSI,” in
Communication,” in Proc. of the IEEE Computer Society Annual Symposium Proc. of the IEEE International Interconnect Technology Conference, 2005,
on VLSI, 2003, pp. 8-12. pp 180–182.
[9] Arteris, http://www.arteris.com/. [39] W.-L. Hung et al., “Interconnect and Thermal-aware Floorplanning for 3D
[10] STMicroelectronics Spidergon, http://www.st.com/stonline/. Microprocessors,” in Proc. of International Symposium on Quality
[11] B. S. Feero and P. P. Pande, “Networks-on-Chip in a Three-Dimensional Electronic Design, 2006, pp. 98–104.
Environment: A Performance Evaluation,” IEEE Transactions on [40] B. Black et al., “Die stacking (3d) microarchitecture,” in Proc. of the
Computers, 2009, pp. 32-45. International Symposium on Microarchitecture, 2006, pp. 469-479.
[12] A. W. Topol et al., “Three-Dimensional Integrated Circuits,” IBM J. [41] L. P. Carloni et al., "Networks-on-Chip in Emerging Interconnect
Research and Development, Vol. 50, No. 4/5, 2006, pp. 491. Paradigms: Advantages and Challenges", in Proc. of the IEEE International
[13] W. R. Davis et al., “Demystifying 3D ICS: The Pros and Cons of Going Symposium on Networks-On-Chip, 2009, pp. 10-13.
Vertical,” IEEE Design and Test of Computers, Vol. 22, No. 6, 2005, pp. [42] J. Kim et al., “A novel dimensionally-decomposed router for on-chip
498-510. communication in 3D architectures,” in Proc. of International Symposium on
[14] Y. Deng et al., “2.5D System Integration: A Design Driven System Computer Architecture, 2007, pp. 138-149.
Implementation Schema,” in Proc. of Asia and South Pacific Design [43] F. Li et al., “Design and management of 3D chip multiprocessors using
Automation Conference, 2004, pp. 450-455. network-in-memory,” In Proc. of Int. Symp. on Computer Architecture, pp.
[15] M. Ieong et al., “Three Dimensional CMOS Devices and Integrated 130–141, 2006.
Circuits,” in Proc. IEEE Custom Integrated Circuits Conference, 2003, pp. [44] R. I. Greenberg and L. Guan, “An Improved Analytical Model for
207-213. Wormhole Routed Networks with Application to Butterfly Fat Trees,” in
[16] V. F. Pavlidis and E. G. Friedman, “3-D Topologies for Networks-on-Chip,” Proc. of International Conference on Parallel Processing, 1997, pp. 44-48.
IEEE Transactions on VLSI Systems., Vol. 15, No. 10, 2007, pp. 1081-1090. [45] C. Grecu et al., “A Scalable Communication-Centric SoC Interconnect
[17] S. M. Jung et al., "High area efficient and cost effective double stacked S3 Architecture,” in Proc. of International Symposium on Quality Electronic
(stacked single-crystal Si) peripheral CMOS SSTFT and SRAM cell Design, 2004, pp. 343-348.
technology for 512M bit density SRAM," IEEE International Electron [46] P. Guerrier and A. Greiner, “A Generic Architecture for On-Chip Packet-
Devices Meeting Technical Digest, 2004, pp. 265-268. Switched Interconnections,” in Proc. of Design, Automation and Test in
[18] S. M. Jung et al., "Three dimensionally stacked NAND flash memory Europe Conference, 2000, pp. 250-256.
technology using stacking single crystal Si layers on ILD and TANOS [47] H. Matsutani et al., “Tightly-coupled multi-layer topologies for 3-D NOCs,”
structure for beyond 30nm node," IEEE International Electron Devices in Proc. of International Conference on Parallel Processing, 2007, pp. 75-
Meeting Technical Digest, 2006, pp. 1-4. 84.
[19] F. Li et al., "Evaluation of Si02 antifuse in a 3D-OTP memory," IEEE [48] D. Park et al., “MIRA: A multi-layered on-chip interconnect router
Transactions on Device and Materials Reliability, Vol. 4, No.3, 2004, pp. architecture,” in Proc. of International Symposium on Computer
416-421. Architecture, 2008, pp. 251-261.
[20] T. W. Chen et al., "Thermal modeling and device noise properties of three- [49] Y. Chen et al., "De Bruijn graph based 3D Network on Chip architecture
dimensional-SOI technology," IEEE Transactions on Electron Devices, Vol. design," in Proc. of International Conference on Communications, Circuits
56, No.4, 2009, pp. 656-664. and Systems, 2009, pp. 986-990.
[21] K. Bernstein et al., "Interconnects in the Third Dimension: Design [50] M. Hosseinabady et al., “Reliable network-on-chip based on generalized de
Challenges for 3D ICs," in Proc. of Design Automation Conference, 2007, Bruijn graph,” in Proc. of International High Level Design Validation and
pp.562-567. Test Workshop, 2007, pp. 3-10.
[22] R. S. Patti, “Three-Dimensional Integrated Circuits and the Future of [51] S. Pasricha, "Exploring serial vertical interconnects for 3D ICs," in Proc. of
System-on-Chip Designs”, in Proc of IEEE, Vol. 94, No. 6, 2006, pp. 1214- Design Automation Conference, 2009, pp. 581-586.
1224. [52] A. W. Yin et al., "Explorations of Honeycomb Topologies for Network-on-
[23] G. Philip et al., Handbook of 3D Integration. Wiley-VCH, 2008. Chip," in Proc. of International Conference on Network and Parallel
[24] B. Black et al., "3D processing technology and its impact on iA32 Computing, 2009, pp.73-79.
microprocessors," in Proc. of the International Conference on Computer [53] Y. Xu et al., "A low-radix and low-diameter 3D interconnection network
Design, 2004, pp. 316-318. design," in Proc. of International Conference on High Performance
[25] T. Kgil et al., "PICOSERVER: Using 3D Stacking Technology to Enable a Computer Architecture, 2009, pp.30-42.
Compact Energy Efficient Chip Multiprocessor," in Proc. Conf. [54] R. S. Ramanujam and B. Lin, “A Layer-Multiplexed 3D On-Chip Network
Architectural Support for Programming Languages and Operating Systems, Architecture,” IEEE Embedded Systems Letters, Vol. 1, No.2, 2009, pp. 50-
ACM Press, 2006, pp. 117-128. 55.
[26] Y. -F. Tsai et al., "Three-dimensional cache design exploration using [55] A. –M. Rahmani et al., “An Efficient 3D NoC Architecture Using
3DCacti," in Proc. of the International Conference on Computer Design, Bidirectional Bisynchronous Vertical Channels,” in Proc. of 2010 IEEE
2005, pp. 519-524. Computer Society Annual Symposium on VLSI, 2010, pp. 452-453.
[27] K. Puttaswamy and G. H. Loh, "Thermal Herding: Microarchitecture [56] C. Seiculescu et al., "SunFloor 3D: A tool for Networks on Chip topology
Techniques for Controlling Hotspots in High-Performance 3D-Integrated synthesis for 3D systems on chips," in Proc. of Design, Automation & Test
Processors," in Proc. of the 13th High Performance Computer Architecture, in Europe Conference & Exhibition, 2009, pp. 9-14.
2007, pp. 193-204. [57] S. Murali et al., “Synthesis of networks on chips for 3D systems on chips,”
[28] C. Ababei et al., "Placement and Routing in 3D Integrated Circuits," IEEE in Proc. of Asia and South Pacific Design Automation Conference, 2009, pp.
Design & Test, Vol. 22, No. 6, 2005, pp. 520-531. 242-247.
[29] A. Jantsch and H. Tenhunen. Networks on Chip. Kluwer Academic
Publishers, 2003.