base paper

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 2, FEBRUARY 2013

625

A Generalized Cascaded Multilevel Inverter Using
Series Connection of Submultilevel Inverters
Mohammad Farhadi Kangarlu, Student Member, IEEE, and Ebrahim Babaei, Member, IEEE

Abstract—Application of multilevel inverters for higher power
purposes in industries has become more popular. This is partly
because of high-quality output waveform of multilevel inverters in
comparison with two-level inverters. In this paper, initially a new
topology for submultilevel inverter is proposed and then series connection of the submultilevel inverters is proposed as a generalized
multilevel inverter. The proposed multilevel inverter uses reduced
number of switching devices. Special attention has been paid to obtain optimal structures regarding different criteria such as number
of switches, standing voltage on the switches, number of dc voltage
sources, etc. The proposed multilevel inverter has been analyzed
in both symmetric and asymmetric conditions. The validity of the
proposed multilevel inverter is verified with both computer simulations using PSCAD/EMTDC software and laboratory prototype
implementation.
Index Terms—Generalized topology, multilevel inverter, optimal
structure, submultilevel inverter.

I. INTRODUCTION
ULTILEVEL inverters include an array of power semiconductors and dc voltage sources, the output of which
generate voltages with stepped waveforms [1]. In comparison
with a two-level voltage-source inverter (VSI), the multilevel
VSI enables to synthesize output voltages with reduced harmonic distortion and lower electromagnetic interference [2].
By increasing the number of levels in the multilevel inverters,
the output voltages have more steps in generating a staircase
waveform, which has a reduced harmonic distortion. However,
a larger number of levels increase the number of devices that
must be controlled and the control complexity [3].
There are three well-known types of multilevel inverters [4],
[5]: the neutral point clamped (NPC) multilevel inverter, the
flying capacitor (FC) multilevel inverter, and the cascaded
H-bridge (CHB) multilevel inverter. The NPC multilevel inverter, also called diode-clamped, can be considered the first
generation of multilevel inverter introduced by Nabae et al. [6]
which was a three-level inverter. The three-level case of the NPC
multilevel inverters has been widely applied in different industries. Unlike the NPC type, the FC multilevel inverter offers

M

Manuscript received July 30, 2011; revised November 16, 2011 and February
4, 2012; accepted May 24, 2012. Date of current version September 27, 2012.
Recommended for publication by Associate Editor J. R. Rodriguez.
The authors are with the Faculty of Electrical and Computer Engineering, University of Tabriz, 51664 Tabriz, Iran (e-mail: m.farhadi@tabrizu.ac.ir;
e-babaei@tabrizu.ac.ir).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2012.2203339

some redundant switching states that can be used to regulate
the capacitors voltage. However, the control scheme becomes
complicated. Moreover, the number of capacitors increases by
increasing the number of voltage levels.
The CHB multilevel inverters use series-connected H-bridge
cells with an isolated dc voltage sources connected to each
cell. The CHB multilevel inverters can be divided into two
groups from the viewpoint of values of the dc voltage sources:
the symmetric and the asymmetric topology. In the symmetric
topology, the values of all of the dc voltage sources are equal.
This characteristic gives the topology good modularity. However, the number of the switching devices rapidly increases by
increasing the number of output voltage level. In order to increase the number of output voltage level, the values of the dc
voltage sources are selected to be different, these topologies
are called asymmetric [7], [8]. The CHB multilevel inverters
have been industrially employed in several applications fields
such as pump, fans, compressors, etc. In addition, they have
recently been proposed for other applications like photovoltaic
power-conversion system and wind power conversion [9]. The
topologies discussed previously are the conventional topologies.
Many other multilevel inverter topologies have been introduced
in recent years. One of the topologies is the modular multilevel inverter [10]. This topology is simpler than the cascaded
four-switch H-bridge-based inverter and has several advantages,
such as modular extension to any number of levels and redundancy [11]. However, the topology does not consider reduction
in the number of components used. Other multilevel inverter
topologies have been introduced in [12]–[15]. The multilevel
inverter presented in [15] is based on symmetric topology and
uses series/parallel connection of the dc voltage sources. This
topology uses lower number of switches in comparison with the
symmetric CHB multilevel inverter. The topologies presented
in [12] and [13] consider reduction in the components. These
topologies are basically based on asymmetric topologies; hence,
the used dc voltage sources have different values. However, the
number of switching devices still remains high in these topologies. A nine-level active NPC inverter has been presented in [16]
which is the modification of the standard active NPC converter.
Nami et al. [17] present a hybrid multilevel inverter using the
CHB and the diode-clamped topology.
This paper proposes a new multilevel inverter topology using
series-connected submultilevel inverters. The proposed multilevel inverter uses reduced number of switches. Initially, the
proposed submultilevel inverter is described and then the series
connection of them to form a multilevel inverter is discussed.
The optimal structures of the proposed multilevel inverter regarding several factors (e.g., number of switches, number of dc

0885-8993/$31.00 © 2012 IEEE

626


TABLE I
OUTPUT VOLTAGES FOR STATES OF SWITCHES

Fig. 1.

Proposed generalized submultilevel inverter.

voltage sources, standing voltage on the switches, etc.) are also
obtained. The power loss of the proposed topology is calculated. Afterward, the proposed multilevel inverter is compared
with other multilevel inverter topologies considering the number of switches. A design example is then given which is used
for simulation and experimental studies.
II. PROPOSED GENERALIZED MULTILEVEL INVERTER

Considering Fig. 1, for each value of the output voltage of submultilevel inverter, two switches must be turned ON, one from
the upper switches and the other from the lower switches. For
example, to get output voltage of Vdc , the switches S1 and S2 are
turned ON. In order to obtain the output voltage of (n − 1)Vdc ,
the switches Sn /2 and S(n +2)/2 should be turned ON.
Considering Fig. 1, the following equations can be written:
Nswitch,sub =

2,

for n = 1

(n + 2),

for n ≥ 2

(1)

A. Proposed Submultilevel Inverter

Ndriver,sub = Nswitch,sub

(2)

Fig. 1 shows the proposed submultilevel inverter. As depicted
in Fig. 1, the topology consists of n dc voltage sources. In general, the dc voltage sources can have different values. However,
in order to have equal voltage steps, they are considered to be
the same and equal to Vdc . Each submultilevel inverter consists
of n + 2 switches. Some of the switches are unidirectional and
the others are bidirectional. The unidirectional switches consist
of an insulated gate bipolar transistor (IGBT) with an antiparallel diode. The switches S1 , S1 , S(n +2)/2 , and S(n +2)/2 are
unidirectional and the other switches are bidirectional; hence,
they have to withstand both positive and negative voltages. For
instance, when S(n +2)/2 is turned ON, the voltage Vdc is on the
switch Sn /2 , and if the switch S(n −2)/2 is turned ON, the voltage equal to −Vdc is on the switch Sn /2 . The same conditions
are valid for the other switches. Therefore, the switches have to
withstand both positive and negative voltages. In addition, the
switches have to conduct backward current that is as a result of
inductive characteristic of the load. It can be concluded that the
switches must be bidirectional. There are several circuit conﬁgurations for bidirectional switches. In this study, the common
emitter topology is used as it needs one gate driver for a switch.
Considering the types of the switches, 2n IGBTs are required in
the proposed submultilevel inverter. It is worth mentioning that
the number of the antiparallel diodes is equal to the number of
IGBTs.
The proposed submultilevel inverter can only generate zero
and positive voltage levels. The zero output voltage is obtained
when the switches S1 and S1 are turned ON simultaneously.
The other voltage levels are generated by proper switching between the switches. Table I shows the states of the switches for
each output voltage value. In this table, 1 means that the corresponding switch is turned ON and 0 indicates the OFF state.

NIGBT,sub = 2n

(3)

Nsource,sub = n

(4)

where, Nswitch,sub , Ndriver,sub , NIGBT,sub , and Nsource,sub are
the number of switches, number of switches drivers in one submultilevel inverter, number of IGBTs in one submultilevel inverter, and number of dc sources in one submultilevel inverter,
respectively.
For the proposed typical submultilevel inverter (see Fig. 1),
the standing voltage on the switches is calculated. A switch experiences different off-state voltages in different switching combinations. Among these off-state voltages, the highest voltage is
considered to be the standing voltage of the switch. This can be a
criterion for voltage rating of the switch. For example, in Fig. 1,
the switch S1 experiences the maximum off-state voltage when
the switch S(n +2)/2 is turned ON that is equal to (n/2)Vdc . For
the switch S2 , the standing voltage is (n/2 − 1)Vdc . For the
switches S1 and S2 , the standing voltage is equal to (n/2)Vdc
and (n/2 − 1)Vdc , respectively. This calculation can be done
for any switch in the submultilevel inverter. The standing voltage for the submultilevel inverter is sum of all standing voltage
on the switches in their off state [12]. For a submultilevel inverter including n dc voltage sources, the standing voltage on
the switches depends on n and whether it is odd or even. For
different n, the standing voltage on the switches of ith submultilevel inverter (Vstand,i ) can be obtained by (5), shown at the
bottom of the next page.
B. Proposed Generalized Multilevel Inverter
The proposed submultilevel inverters can be connected in
series to achieve the desired voltage and number of voltage

KANGARLU AND BABAEI: GENERALIZED CASCADED MULTILEVEL INVERTER

Fig. 2. Proposed general multilevel inverter using series connection of m
proposed submultilevel inverters, each one has n dc voltage sources.

levels. Fig. 2 shows m submultilevel inverters in series. Each
submultilevel inverter has n dc voltage source. The dc voltage
sources in each submultilevel inverter are equal.
The output voltage of the submultilevel inverters (and series
connection of them) is always positive or zero. To operate as an
inverter, it is necessary to change the voltage polarity in every
half cycle. For this purpose, an H-bridge inverter is added to the
output of the series connected submultilevel inverters.
It is important to note that the switches of the H-bridge must
withstand higher voltage. This should be considered in the design of the inverter. However, these switches are turned ON and
OFF once during a fundamental cycle. So, these switches would
be high-voltage low-frequency switches.
Considering that the multilevel inverter shown in Fig. 2 includes m submultilevel inverter (using (1)–(4) and considering
the H-bridge part), the following equations can be written:

Nswitch =

2m + 4,

for n = 1

m · (n + 2) + 4,

for n ≥ 2

(6)

Ndriver = Nswitch

(7)

NIGBT = 2mn + 4

(8)

Nsource = mn

(9)

Vstand,i =

627

where Nswitch , Ndriver , NIGBT , and Nsource are the number of
switches, number of switches drivers (which is equal to number
of switches), number of IGBTs, and total number of dc sources,
respectively.
Considering (6) and (8), in general, the number of IGBTs is
not equal to the number of switches in the proposed multilevel
inverter; hence, some of the switches are bidirectional (which
is considered as one switch) and consist of two IGBTs. The
proposed topology can be extended to three-phase systems using
three single-phase units. Like the other multilevel converters, the
switches cannot be shared between the phases, and therefore,
three single-phase structures should be used. In the extension
of the proposed topology to the three-phase systems without
using transformer, attention should be paid that the dc voltage
sources in the different phases must be independent (isolated)
so that the load can be star/delta connected. It is very important
to note that also in the well-known CHB topology (extended to
three-phase), independent dc voltage sources are required for
different phases [18]. Therefore, from this point of view, the
proposed topology acts as like as the CHB topology.
Two conditions can be considered regarding the value of the
dc voltage sources used in the proposed multilevel inverter; all
of them can be equal leading to a symmetric topology or their
values can be different leading to asymmetric topology. These
two conditions are discussed as follows.
1) Proposed Symmetric Multilevel Inverter: For the symmetric multilevel inverter, all of the dc voltage sources are considered to be equal. Therefore, the following equations can be
written for the symmetric topology:
Vdc,1 = Vdc,2 = · · · = Vdc,m
Nlevel = 2mn + 1

(11)

where Nlevel is the number of output voltage levels.
Since in the case of the symmetric topology the cascaded
submultilevel inverters have the same condition, the following

⎧ ( n −1 )
−1
⎪
( n + 1 −1 )/2
4
2
⎪
⎪
3n2
n−1
n+1
5
n−1
⎪
⎪2
− k Vdc,i + 2
− k Vdc,i +
Vdc,i =
+n+
Vdc,i
⎪
⎪
⎪
2
2
4
8
8
⎪
k =0
k =0
⎪
⎪
⎪
⎪
⎪
⎪
n−1
⎪
⎪
is even
if n is odd and
⎪
⎪
2
⎪
⎪
⎪
⎪ n −1
⎪
⎪ ( 2 −1 )/2
( n + 1 −1 )
⎪
4
⎪
⎪
3n2
n−1
n+1
5
n+1
⎪2
⎪
− k Vdc,i + 2
− k Vdc,i +
Vdc,i =
+n+
Vdc,i
⎪
⎪
2
2
4
8
8
⎨
k =0
k =0
⎪
n−1
⎪
⎪
⎪
is odd
if n is odd and
⎪
⎪
2
⎪
⎪
⎪
⎪ n
⎪ ( −1 )/2
⎪ 2
⎪
⎪
3n2
n
1
n
⎪
⎪
⎪4
− k Vdc,i =
+n+
Vdc,i , if n is even and is odd
⎪
⎪
2
8
2
2
⎪
⎪
k =0
⎪
⎪
⎪
⎪ n
⎪ ( −1 )
⎪ 4
⎪
⎪
3n2
n
n
n
⎪
⎪4
− k Vdc,i + Vdc,i =
+ n Vdc,i if n is even and is even
⎪
⎩
2
2
8
2
k =0

(10)

(5)

628


relations can be expressed regarding the standing voltage on the
switches:
Vstand,1 = Vstand,2 = · · · = Vstand,m

(12)

Vstand,total = m · Vstand,1 + 4mnVdc,1

Nlevel − 1
2n

Nlevel − 1
2

Vstand,1
+ 4Vdc,1
n

·

(15)

2) Proposed Asymmetric Multilevel Inverter: For the asymmetric topology, the value of the dc voltage sources is different
from a submultilevel inverter to another. In other words, if the dc
sources of the first submultilevel inverter is Vdc,1 , the dc sources
of the second submultilevel inverter is Vdc,2 . To get maximum
number of level for the output voltage, there must be no redundancy. This is achieved when the value of the dc voltage sources
in submultilevel inverters have the following relation:
Vdc,2 = (n + 1) · Vdc,1
Vdc,3 = (n + 1)Vdc,1 + nVdc,2 = (n + 1)Vdc,1 + n(n + 1)Vdc,1
= (n + 1)(n + 1)Vdc,1 = (n + 1)2 Vdc,1 .

(16)

Therefore, in general, the following relation should be valid
for the dc sources of the submultilevel inverters:
Vdc,i = (n + 1)i−1 · Vdc,1 ,

i = 1, 2, 3, . . . , m

(17)

where Vdc,i is the value of the dc sources in the ith submultilevel
inverter.
The maximum value of the output voltage (sum of all dc
voltage sources) for the proposed asymmetric topology can be
obtained as follows:
m

Vo,m ax = n

Vdc,i .

(18)

i=1

Using (17) and (18), the maximum value of the output voltage
can be written as
Vo,m ax = [(n + 1)m − 1]Vdc,1 .

(19)

With the aforementioned arrangement of the dc voltage
sources, the number of voltage levels will be equal to
Nlevel = 2(n + 1)m − 1.

(20)

For the asymmetric topology, the total standing voltage of
the switches (Vstand,total ) is sum of standing voltages on the
switches of the submultilevel inverters ( m Vstand,i ) and
i=1
also the standing voltage on the switches of the H-bridge part
(4Vo,m ax ). Therefore, it can be written as follows:
m

Vstand,total =

Vstand,i + 4Vo,m ax .
i=1

Using (20) and (22), the total standing voltage in terms of
number of output voltage level and n can be expressed as
follows:
Vstand,total =

.

(21)

(n + 1)m − 1
n
· Vstand,1 + 4[(n + 1)m − 1] · Vdc,1 . (22)

(14)

From (13) and (14), the following equation is obtained:
Vstand,total =

Vstand,total =

(13)

where Vstand,total is the total standing voltage on the switches
of the multilevel inverter.
Using (11), m is obtained as follows:
m=

Using (5), (17), (19), and (21), the total standing voltage of
the switches can be written as follows:

Nlevel − 1
2

·

Vstand,1
+ 4Vdc,1
n

.

(23)

C. Optimal Structures
In this section, the aim is to determine the optimal structures
considering different aspects. For the proposed multilevel inverter, there are two design parameters. The first parameter is
the number of dc sources in each submultilevel inverter n and
the other is the number of series connected submultilevel inverters, m. Both m and n affect maximum value of the output
voltage. However, one of them can be used as a parameter for
topology optimization and the other should be left to meet the
desired maximum value of the output voltage (output voltage
rating of the multilevel inverter). Here, m is used to meet the
required nominal voltage. Therefore, n is used as a variable
to determine the optimal structures. In the following, the optimal structures are discussed for the proposed symmetric and
asymmetric multilevel inverters.
1) Optimal Structures of the Symmetric Topology: The aim
is to determine the parameter n in order to use minimum number
of IGBTs for a specific number of levels. Using (8) and (11),
NIGBT can be written as follows:
NIGBT = Nlevel + 3.

(24)

The aforementioned equation shows that for a specific value
of the number of levels, the number of IGBTs is independent of
n and it is constant. Therefore, variation of the parameter n does
not affect the number of IGBTs. The same result is obtained for
the case in which the aim is to have maximum number of voltage
levels for a given number of IGBTs.
Another aspect for optimization of the topology can be using
the minimum number of gate driver circuits for a constant number of voltage levels. Using (6), (7), and (11), the number of the
gate drivers (and its normalization) can be written as follows:
⎧
for n = 1
⎨ (Nlevel − 1) + 4,
Ndriver = n + 2
⎩
(Nlevel − 1) + 4, for n ≥ 2
2n
⎧
1,
for n = 1
Ndriver − 4 ⎨
= n+2
Normalized Ndriver =
⎩
Nlevel − 1
, for n ≥ 2.
2n
(25)
Fig. 3 shows variation of the normalized value of the number
of drivers versus n for a given number of voltage levels. The
figure indicates that as n increases, the number of required


629

Fig. 3. Normalized N d rive r and normalized total standing voltage on the
switches versus n for the symmetric topology.

gate driver circuits decreases. Therefore, higher n gives better
topology from the viewpoint of number of gate drivers.
Standing voltage on the switches is the other factor which
is considered for optimization of the topology. The aim is to
determine n in a way that the total standing voltage is minimized
for a given number of voltage levels. Using (15), the following
equation is obtained:
Vstand,total
Vstand,1
−2=
.
(Nlevel − 1) · Vdc,1
2nVdc,1
(26)
Fig. 3 also shows the variation of the normalized total standing
voltage on the switches versus n. It is clear from the figure that
the standing voltage on the switches is minimum for both n = 1
and n = 2. The higher values of n lead to a topology with higher
standing voltage. In other words, the topology with n = 1 and
n = 2 give the best topology from the viewpoint of standing
voltage.
From the previous discussion, it can be concluded that the
value of n does not affect the number of IGBTs. However, as
n goes up (higher than 2), the number of gate drivers decreases
and, on the contrary, the standing voltage increases. This implies
that a tradeoff may be considered between the number of gate
drivers and standing voltage. For instance, n = 3 can be a
candidate for the better topology in the symmetric condition.
2) Optimal Structures of the Asymmetric Topology: The first
optimal structure is to determine n to obtain the maximum voltage level for a constant number of switches (or driver circuits).
Using (6) and (20), the number of voltage levels in terms of
number of switches is as follows:
⎧
N s w i t c h −4
2
⎨ 2(2)
− 1,
for n = 1
Nlevel =
N s w i t c h −4
⎩
2(n + 1) ( n + 2 ) − 1, for n ≥ 2
⎧
1
⎨ 2(2 2 )N s w i t c h −4 − 1,
for n = 1
=
1
(N s w i t c h −4)
⎩
2 (n + 1) ( n + 2 )
− 1, for n ≥ 2.

Normalized Vstand,total =

(27)
In (27), the number of switches is considered as a constant.
Therefore, the number of voltage levels is maximized for such
an n that maximizes the following term:
1

22 ,
D=
(n + 1)

for n = 1
1
(n + 2)

, for n ≥ 2.

(28)

Fig. 4 shows the variation of D versus n. As the figure indicates, n = 1 gives the optimal structure from the viewpoint of
number of switches.

Fig. 4.

Variation of D, (29), 2(n + 1)1 / 2 n , and n/ ln(n + 1) versus n.

Similarly, another optimal structure can be obtained for minimizing the number of switches for a constant number of voltage
levels. In this case, using (27), the following equation can be
written:
⎧ 2
⎪
for n = 1
⎪
⎨ ln 2 ,
Nswitch − 4
(29)
=
⎪ (n + 2)
ln N l e v2e l −4
⎪
⎩
, for n ≥ 2.
ln(n + 1)
The variation of (29) versus n is also depicted in Fig. 4. It is
clear that n = 1 gives again the optimal structure.
Considering (7), the number of gate drivers is equal to the
number of switches. Therefore, n = 1 also gives the optimal
structure from the viewpoint of minimum gate drivers.
In the previous analysis, the number of switches was considered as a criterion for determining the optimal structures. As
mentioned before, the number of switches is not equal to the
number of IGBTs. If the number of IGBTs is used as a criterion,
the results will be the same.
Considering (8) and (20), the number of voltage levels as a
function of n for a constant number of IGBTs is as follows:
Nlevel = 2(n + 1)

N I G B T −4
2n

= 2 (n + 1)

1
2n

−1

(N I G B T −4)

− 1.

(30)

Taking into account that the number of IGBTs has been considered to be constant, in (30), the number of voltage levels will
be maximum if the term 2(n + 1)1/2n is maximum.
Fig. 4 also shows the variation of 2(n + 1)1/2n versus n. As
this figure shows, the number of levels decreases as n increases.
Therefore, the maximum number of voltage level for a constant
number of IGBTs is obtained when n is equal to 1. The same
result can be obtained for the minimum number of IGBTs for a
constant number of voltage levels.
The number of the dc voltage sources Nsource is the other
variable which is used to obtain optimal topology. The aim is
to minimize the number of required dc voltage sources for a
specific number of voltage levels. Using (9) and (20), Nsource
can be written as follows in terms of the number of output
voltage levels and the number of dc voltage sources in each
submultilevel inverter:
Nsource =

n
· ln
ln(n + 1)

Nlevel + 1
2

.

(31)

630


The aforementioned equation gets its minimum value when
the term n/ ln(n + 1) is minimum. Variation of this term versus
n is also shown in Fig. 4. It is clear that the minimum value is
achieved when n = 1.
To obtain the optimal structure from viewpoint of standing
voltage on the switches, using (23), the normalized total standing
voltage is obtained as follows:
Vstand,total
Vstand,1
−2=
.
(Nlevel − 1) · Vdc,1
2nVdc,1
(32)
This equation is same as (26). Therefore, for the asymmetric
topology (like the symmetric topology), the optimal structure
considering the total standing voltage on the switches is achieved
for n = 1 and n = 2. It is important to note that the standing
voltage on the switches is the same for these two values of n.
This is clear from Fig. 1 for n = 1 and n = 2.
It can be concluded from the previous analysis that the optimal
structure (for the asymmetric topology) from the viewpoint of
the number of used switches, IGBTs, dc voltage sources, and
the value of the standing voltage on the switches is obtained
when n is 1.
Normalized Vstand,total =

III. CALCULATION OF LOSSES
Typically, two kinds of losses are associated with power electronic converters. The conduction losses are caused by equivalent resistance and the on-state voltage drop of the semiconductor devices. The switching losses are caused by nonideal
operation of switches. Calculation of the losses of the proposed
multilevel inverter is discussed as follows.

proposed submultilevel inverter can be calculated as follows:
Pc,sub,j =

1
π

π

x(t)VT ,j + y(t)VD ,j
+x(t)RT ,j iβ (t) + y(t)RD ,j i(t)

0

i(t)

× d(ωt).

(35)

The specifications of the switches used in different submultilevel inverters may be different. Therefore, the index j in the
aforementioned equation is used in order to refer to the jth submultilevel inverter. As the losses are calculated for the typical
jth submultilevel inverter, it can be extended to other cascaded
submultilevel inverters.
As the conduction power loss of the cascaded submultilevel
inverters are calculated one by one, they are added together to
obtain the total conduction power loss Pc, sub of the cascaded
submultilevel inverters:
m

Pc,sub =

Pc,sub,j .

(36)

j =1

In the power loss calculated previously, the H-bridge part of
the proposed multilevel inverter has not been considered. If the
power factor angle is ϕ, then in every half cycle, the diodes and
transistors of the H-bridge part conduct for time interval corresponding to ϕ and π−ϕ, respectively. If the output current is
considered to be sinusoidal as i(t) = Im sin(ωt), the conduction
power loss of the H-bridge can be obtained as follows:
Pc,H =
=

A. Conduction Losses

1
π

φ

π

2pc,D (t)d(ωt) +
0

2pc,T (t)d(ωt)
φ

2
2
RD ,H Im
(2φ − sin(2φ))
VD ,H Im (1 − cos φ) +
π
4

+ VT ,H Im (1 + cos φ)

In order to calculate the conduction losses, first conduction
losses of a typical power transistor and diode are calculated; then
they are developed to the multilevel inverter. The instantaneous
conduction losses of a transistor (pc,T (t)) and diode (pc,D (t))
can be written as follows:

π
β
+ RT ,H Im+1

sinβ +1 (ωt)d(ωt) .

(37)

φ

pc,T (t) = [VT + RT iβ (t)] i(t)

(33)

In the aforementioned equation, the index H indicates the
parameters related to the H-bridge.
The total conduction loss of the proposed multilevel inverter
is obtained as follows:

pc,D (t) = [VD + RD i(t)] i(t)

(34)

Pc = Pc,sub + Pc,H .

where VT and VD are the on-state voltage of the transistor and
diode, respectively. RT and RD are the equivalent resistance of
the transistor and diode, respectively, and β is a constant related
to the specification of the transistor.
In the proposed submultilevel inverter, consider that there are
x(t) transistors and y(t) diodes in the current path in any instant
of time. The value of x(t) and y(t) depends on the output voltage
level and operating conditions (mainly direction of the current).
Considering Fig. 1, depending on the voltage level and current
direction, in the proposed submultilevel inverter there might be
two diodes, two transistors, one transistor and one diode, two
diodes and one transistor, two transistors and one diode, and
two transistors and two diodes in the current path. Therefore,
using (33) and (34), the average conduction power loss of the

(38)

B. Switching Losses
The switching losses are calculated for a typical switch, and
then, the results are extended for the proposed multilevel inverter. For this calculation, the linear approximation of the voltage and current during switching period is used. Using this approximation, energy loss during the turn-off period of a switch
can be obtained as follows:
Eoff ,k
to f f

=

to f f

v(t)i(t)dt =
0

=

1
Vsw ,k I toff
6

0

Vsw ,k
t
toff

−

I
toff

(t − toff )

dt
(39)


Fig. 5. (a) Number of IGBTs and (b) number of driver circuits versus number
of levels for the symmetric topologies.

631

Fig. 6. Standing voltage on the switches versus number of levels for the
symmetric topologies.

where Eoff ,k is the turn-off loss of the switch k, toff is the turnoff time of the switch, I is the current through the switch before
turning OFF, and Vsw ,k is the off-state voltage on the switch.
The turn-on loss of the switch can be calculated as follows:
to n

Eon,k =

v(t)i(t)dt
0
to n

Vsw ,k
t
ton

=
0

−

I
(t − ton )
ton

Fig. 7. (a) Per-unit conduction power loss and (b) per-unit switching power
loss versus number of levels for the symmetric topologies (R T = 0.15 Ω, V T =
2.5 V, R D = 0.1 Ω, V D = 1.5 V, n = 3, to n = to ff = 2 μs).

dt

1
= Vsw ,k I ton
(40)
6
where Eon,k is the turn-on loss of the switch k, ton is the turn-on
time of the switch, and I is the current through the switch after
turning ON.
The switching losses depend on the number of switching
transitions. Therefore, it depends on the modulation method.
Generally, the average switching power loss can be written as
follows:
⎛
⎞⎤
⎡
Nsw itch

Psw

= 2f ⎣

⎝

Non ,k

Eon,k i +
i=1

k =1

No ff , k

Eoff ,k i ⎠⎦

(41)

i=1

where f is the fundamental frequency, Non,k and Noff ,k are
the number of turning ON and OFF the switch k during a half
fundamental cycle. Also, Eon,k i is the energy loss of the switch
k during the ith turning ON and Eoff ,k i is the energy loss of the
switch k during the ith turning OFF.
Using (38) and (41), the total losses of the multilevel inverter
will be
PLoss = Pc + Psw .

(42)

IV. COMPARISON OF THE PROPOSED TOPOLOGY
WITH THE OTHER TOPOLOGIES
A. Symmetric Topology
Fig. 5(a) shows the number of IGBTs versus the number
of voltage levels in different topologies. As the figure shows,
for any specific value of Nlevel , the proposed topology uses
lower number of IGBTs in comparison with [15] and CHB. The
required number of gate driver circuits in the aforementioned
topologies versus Nlevel is shown in Fig. 5(b). The figure clearly
shows that the proposed topology uses the least Ndriver . Standing voltage on the switches of the topologies is presented in
Fig. 6. The figure shows that the CHB has the best characteristic
from the viewpoint of standing voltage on the switches and the

proposed topology is better than [15] in terms of standing voltage
on the switches. Fig. 7(a) and (b) shows the calculated per-unit
conduction and switching power loss of the topologies, respectively. To draw the figures, n is considered to be 3 (n = 3) and
m varies as the number of levels varies. Also, for all of the transistors, the on-state resistance and voltage drop are considered
to be 0.15 Ω (RT = 0.15 Ω) and 2.5 V (VT = 2.5 V), respectively. The on-state resistance and voltage drop of the diodes
are assumed to be 0.1 Ω (RD = 0.1 Ω) and 1.5 (VD = 1.5 V),
respectively. The on-time ton and off-time toff of the switches
is assumed 2 μs. Each dc voltage source has the value of 100 V.
The resistance of the load is 45 Ω and its inductance is 55 mH so
that ϕ = 21◦ . It is important to note that the base value for the
per-unit losses is the converter rated output power. As Fig. 7(a)
shows, the proposed topology and that of [15] have lower conduction loss than the CHB. Also, the conduction power loss of
the proposed topology is lower than that of [15]. This result was
predictable since the number of semiconductor devices in the
current path in any instant of time for the proposed topology
is lower than that of the other two topologies. However, this
number is close for the proposed topology and [15]. According
to Fig. 7(b), switching power loss of the proposed topology is
lower than that of [15]. However, the switching power loss of
the proposed topology is higher than that of CHB. It is worth
mentioning that the conduction losses are the major part of the
losses.
Despite the number of IGBTs, in the proposed symmetric
topology, variety of the switches in terms of the voltage ratings is higher than the symmetric CHB topology. This can be
considered a disadvantage for the proposed symmetric topology when comparing with the symmetric CHB topology. In the
proposed symmetric topology with n = 3, three different kinds
of switches in terms of voltage ratings are required. However,
the proposed topology considerable reduces the total number of
switches.

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Fig. 11.

Sum of the standing voltage on the switches for different topologies.

Fig. 8. Number of IGBTs versus the number of output voltage level in the
submultilevel inverters.

Fig. 9. Standing voltage on the switches versus the number of output voltage
level in the submultilevel inverters.

Fig. 10.

Number of IGBTs versus the number of output voltage levels.

B. Asymmetric Topology
The proposed topology in this paper is compared with the
topologies presented in [12] and [13] and the asymmetric CHB
topology. Initially, the proposed submultilevel inverter (see
Fig. 1) is compared with the submultilevel inverters proposed
in [12] and [13]. It is noticeable that the submultilevel inverter
is called as basic unit in [12] and [13]. The number of IGBTs
versus the number of voltage levels is shown in Fig. 8 for the
proposed submultilevel inverter and the basic units presented
in [12] and [13]. As shown in Fig. 8, the proposed submultilevel inverter uses lower number of IGBTs in comparison with
the others. Fig. 9 shows the sum of the standing voltage on the
switches for the submultilevel inverters. As shown in the figure,
the proposed submultilevel inverter has a better condition from
the viewpoint of standing voltage on the switches.
In the previous comparison, the submultilevel inverters have
been compared together. Here, the aim is to compare the multilevel inverters resulted from series connection of the submultilevel inverters. For the comparison purpose, the required number
of IGBTs for each number of output voltage levels is depicted
in Fig. 10. It can be seen from this figure that the proposed
topology uses a considerable lower number of IGBTs for any
specific number of output voltage level in comparison with the
topologies presented in [12] and [13] and the asymmetric CHB
topology. For the topology presented in [13], the optimal topology derived in [19] is used for comparison.

Fig. 12. (a) Per-unit conduction losses and (b) per-unit switching losses for
the proposed asymmetric topology and the asymmetric CHB topology (R T =
0.15 Ω, V T = 2.5 V, R D = 0.1 Ω, V D = 1.5 V, n = 1, to n = to ff = 2 μs).

The other aspect of comparison is the standing voltage on
the switches. Fig. 11 shows the sum of standing voltage on the
switches for different topologies. The standing voltage is stated
in per unit where the base value is the value of the dc voltage
source in the first submultilevel inverter (i.e., Vdc,1 = 1 p.u.). As
shown in the figure, the standing voltage on the switches of the
proposed topology is lower than the topology presented in [12]
and [13]. However, the standing voltage of the CHB topology
is lower than all of the topologies.
Fig. 12(a) and (b), respectively, shows the per-unit conduction
and switching losses of the proposed topology and that of the
asymmetric CHB topology. The characteristic of the switches
and the load data is the same as the symmetric one given in
the previous section. The base value for per unit is the rated
converter output power. In this case, the value of n is considered to be 1. Fig. 12(a) shows that the proposed topology has
lower conduction losses due to lower number of semiconductor
devices that are in the current path in any instant of time. Also,
according to Fig. 12(b), the switching power loss of the proposed
topology is slightly lower than that of the asymmetric CHB. The
topologies in [12] and [13] are not considered in this comparison
since they need snubber circuits for their bidirectional switches,
which makes the calculation of their losses different. Also, the
snubber circuit will increase the losses of [12] and [13].
The variety of the switches in the proposed asymmetric topology (with n = 1) and the asymmetric CHB topology is shown
in Fig. 13. The variety of the switches indicates requirement
for switches with different voltage ratings. As shown in the
figure, both of the topologies need switches with different voltage ratings. However, for any number of levels, the proposed
asymmetric topology needs one more different switch than the
asymmetric topology. Therefore, the requirement for different
switches is almost equal for both of the topologies.


633

TABLE II
TYPICAL IGBTS IN DIFFERENT VOLTAGE RATINGS

Fig. 13.

Variety of the switches versus the number of output voltage levels.

V. MEDIUM-VOLTAGE APPLICATION CONSIDERATIONS
Theoretically, the proposed topologies can be designed for
any voltage level. However, practically there are limitations
when applying the topologies in medium- and high-voltage applications. Considering the switches used in the H-bridge part
of the proposed topologies (T1 − T4 ), these switches must be
able to tolerate a voltage equal to the rated output voltage of
the multilevel inverter. These switches turn ON and OFF once
during a fundamental cycle. Also, they are switched in zero voltage condition; hence, the switches of the submultilevel inverters
provide zero voltage level when the switches operate. Besides
these facts, the four mentioned switches restrict the application
of the proposed topologies for high voltage. It is very important
to note that this problem is not just for the proposed topology.
The topologies in which a high-voltage H-bridge is used (e.g.,
the topologies presented in [12], [15], and [20]) have the same
problem. In these topologies, the switches of the high-voltage
H-bridge have to tolerate a voltage equal to sum of all dc voltage
sources. In other words, in the proposed topology and that of,
e.g., [12], [15], and [20], there are four switches that must be
able to operate in the rated voltage of the inverter. As a result, it is
necessary to determine the voltage level in which the application
of the proposed topology is advantageous. One main criterion is
to avoid series connection of the switches to form a high-voltage
switch, otherwise the proposed topology will not show its advantages. Assume that the highest voltage common commercial
IGBT has a voltage rating equal to VIGBT,m ax . Then, the maximum operating voltage (three-phase line–line rms voltage) of
the proposed topology can be written as follows:
Vrated =

3 VIGBT,m ax
·
2
α

(43)

where Vrated is the rated three-phase line–line rms voltage of
the proposed multilevel inverter and α (safety factor) is a factor
to ensure the safe operation of the IGBT in practice. It may be
considered about α = 1.7.
If (43) is satisfied, then the series connection of the switches
will not be required. In other words, (43) can be used to determine the voltage rating of the proposed topology based on
the availability of the IGBT or it can be used to determine the
voltage rating of the highest voltage IGBT required for a specific rated voltage of the multilevel inverter. Two examples of
medium-voltage design are given as follows.
For the first example, suppose that the highest voltage commercially available IGBT voltage rating is 3300 V
(VIGBT,m ax = 3300 V). Using (43), the rated three-phase line–
line voltage will be equal to about 2.3 kV. If the proposed

31-level asymmetric topology (with n = 1 as shown in Fig. 16)
is considered, to produce such a voltage, the values of the dc
sources will be 125.2, 250.4, 500.8, and 1001.6 V. Table II
shows an example of commercially common IGBT voltage ratings. Considering the commercial IGBTs and taking into account Fig. 16, two 250-V IGBTs for switches S1 and S1 , two
600-V IGBTs for switches S2 and S2 , two 1200-V IGBTs for
switches S3 and S3 , two 1700-V IGBTs for switches S4 and
S4 , and four 3300-V IGBTs for switches T1 − T4 are required
in the proposed topology. It is very important to note that although these switches are high-voltage switches, they operate
in fundamental frequency and zero voltage condition. On the
other hand, if the asymmetric CHB topology is considered, four
250-V, four 600-V, four 1200-V, and four 1700-V IGBTs will
be required.
As another example of high-voltage, another design is considered for three-phase 6-kV rms line–line voltage. So, the peak
voltage will be about 4.9 kV. Considering the 31-level inverter
(see Fig. 16), the value of the dc voltage sources will be about
327, 654, 1307, and 2612 V. Therefore, considering the voltage
rating of the commercial IGBTs, the IGBTs with the voltage ratings of 600 V (for S1 and S1 ), 1200 V (for S2 and S2 ), 2500 V
(for S3 and S3 ), and 4500 V (for S4 and S4 ) can be used which
are available. For high-voltage operation, the switches may be
connected in series [21], [22], and for high-current application
they may be connected in parallel [21], [23]. However, special
attention should be paid to distribute the voltage on them equally
and synchronous operation of them. In order to equally distribute
voltage on the switches, balancing resistors should be used [21],
[24]. For the mentioned example, the switches T1 − T4 of the
proposed topology will need series-connected IGBTs (each of
the switches may require two 3300-V or two 4500-V IGBTs).
Therefore, application of the proposed multilevel inverter in this
voltage level is challenging (although it is possible). As a result, it is recommended that (43) to be satisfied when using the
proposed topology in medium-voltage applications.
Form the two examples discussed previously, it can be concluded that with today’s semiconductor technology, the proposed topology and the topologies presented in [12], [15],
and [20] are not well suited for higher voltages since they use
an H-bridge, the switches of which have to withstand a voltage
equal to rated voltage of the multilevel inverter. Therefore, with
the existing IGBTs, they are recommended for low-voltage applications. However, the semiconductor technology is progressing with a considerable rate. Some years back, IGBTs even with
voltage ratings presented in Table II (e.g., 3300 V, 4500 V) did
not exist. Considering the progressing trend of the semiconductor technology, in future higher voltage IGBTs will be produced

634


Fig. 14. Thirteen-level inverter based on the proposed symmetric topology
with n = 3 and m = 2.

Fig. 16. Thirty-one-level inverter based on the proposed optimal structure
with n = 1 and m = 4 (used for simulations and experimentation).

operates as a low-pass filter for the current. The load current has
also phase difference with the load voltage because of inductive
characteristic of the load.
Fig. 15.

Simulation results for the 13-level symmetric topology.

B. Asymmetric Topology
commercially. This will make the mentioned topologies suitable
for medium-voltage applications.
VI. SIMULATION AND EXPERIMENTAL RESULTS
This section deals with the simulation and experimental validation of the proposed multilevel inverter topology. For the proposed symmetric multilevel inverter, only the simulation results
are presented, but, for the asymmetric topology both simulation
and experimental results are given.
For all of the studies, the load is an RL load with the value
of 45 Ω and 55 mH. The output voltage frequency is assumed
50 Hz.
There are many control methods for multilevel inverter. It is
noticeable that the staircase control method is used in this paper [1]. The term staircase control method is used to state that in
this method, transition from one level of voltage to the next level
happens once as shown in Fig. 15 (for example). This control
method tends to generate a staircase voltage which minimizes
the error with respect to the reference voltage. It is worth noting
that the calculation of optimal switching angles for different
goals, such as elimination of the selected harmonics and minimizing total harmonic distortion (THD), is not the objective of
this paper.
A. Symmetric Topology
Fig. 14 shows the 13-level inverter based on the proposed
symmetric multilevel inverter with n = 3. Six dc voltage sources
each of them 100 V have been used so that the maximum output
voltage will be 600 V. The number of IGBTs for a 13-level
inverter in the proposed topology is 16. For the same number
of voltage levels, the topology of [15] and CHB use 19 and 24
IGBTs, respectively, which are higher than that of the proposed
topology.
Fig. 15 shows the load voltage and scaled load current of
the 13-level inverter. As the figure shows, all of the expected
voltage levels are generated at the output voltage. The load
voltage is sine-waved current as a result of the RL load which

For the asymmetric topology, first a design example of the
proposed multilevel inverter is given and then it is used for
simulation and experimental studies.
1) Design Example: The aim is to design a peak 150-V multilevel inverter with minimum 30 levels of output voltage. As
discussed before, the proposed multilevel inverter is optimal for
n = 1 from different points of view. In order the number of
output voltage level to be higher than its minimum (i.e., 30), the
number of cascaded submultilevel inverters should be 4 (m =
4). Therefore, a 31-level 150-V inverter based on the proposed
generalized multilevel inverter regarding the optimal structures
will be as shown in Fig. 16 in which the values of the dc voltage
sources are shown in the figure. The proposed 31-level inverter
in Fig. 16 uses 12 IGBTs. The number of the dc sources is 4 with
binary increment. On the other hand, a 21-level inverter based
on the topology presented in [13] uses 20 IGBTs which is much
more than the number of IGBTs in the proposed topology, and at
the same time, the number of output voltage level is lower than
that of the proposed topology. A 17-level inverter based on [12]
uses 16 IGBTs and 4 dc voltage sources. In comparison with
the proposed topology, shown in Fig. 16, the topology presented
in [12] uses more IGBTs, and at the same time, the number of
output voltage levels is considerably lower.
2) Simulation and Experimental Results: The validity of the
proposed multilevel inverter is demonstrated with both simulation and experimental results. For the simulation and experimentation, the 31-level inverter shown in Fig. 16 is used. The
BUP306D-type IGBTs are used. Also the AT89C52 microcontroller is used to prepare gate signals for the switches. Tektronix
TDS 2024B four-channel digital storage oscilloscope is used for
measurements in laboratory. Each switch has a driver circuit.
The driver circuit used in this paper consists of an optoisolator,
a Schmit trigger, and a buffer. For a switch in the inverter, an
isolated driver circuit is required. The isolation is achieved using optoisolators. The states of the switches in different voltage
levels have been stored in the microcontroller as a lookup table. The microcontroller provides the switching signals for the
driver circuits and the driver circuits drive the switches. In the


635

Fig. 19. Experimental results. From top to bottom, the traces are output voltage
of cascaded submultilevel inverters, load voltage, and load current.

Fig. 17. Output voltage of each submultilevel inverter: from top to bottom
traces are first, second, third, and fourth submultilevel inverter output voltage,
respectively.

Fig. 18. (Upper trace) Output voltage of cascaded submultilevel inverters.
(Lower trace) Load voltage and scaled load current.

experimental prototype, the constant dc supplies existing in the
laboratory have been used as the dc voltage sources.
In order to generate the triggering signals for the switches
used in the inverter, the reference output voltage is compared
with the available voltage levels. These levels are determined
by the available dc voltage sources and operation modes of the
inverter. Then, the switches that generate the nearest voltage
level to the reference output voltage are turned on. As an example, when the voltage level of 30 V (in Fig. 16) is nearest to
the reference output voltage, the switches S1 , S2 , S3 , and S4 are
turned ON and the other switches are turned OFF.
Fig. 17 shows the output voltage of each submultilevel inverter shown in Fig. 16. Clearly, the output voltage of each
submultilevel inverter corresponds to its dc voltage sources.
Considering the figure, the first submultilevel inverter operates
with the lowest voltage, but in return its operating frequency
is highest among the submultilevel inverters. Inversely, the last
submultilevel inverter operates with highest voltage and lowest
frequency. The switching frequency of the switches S1 –S4 is
1500, 720, 300, and 100 Hz, respectively.
Fig. 18 shows the output voltage of the cascaded submultilevel
inverters, load voltage, and scaled load current. As shown in the

figure, the output voltage of the cascaded submultilevel inverters
is always nonnegative. The polarity of the voltage is changed
using the H-bridge connected to the output of the submultilevel
inverters. The load current is scaled to become visible in the
same frame with the load voltage.
In the test condition (R = 45 Ω, L = 55 mH, Vo,m ax =
150 V), the power loss of the proposed multilevel inverter,
shown in Fig. 16, is about 12 W. However, the power loss of the
asymmetric CHB topology with the same conditions (with the
same value of voltage and load) is about 15.5 W. This can be as
a result of the fact that in the proposed topology, less semiconductor devices are in the current path in any instant of time in
comparison with the asymmetric CHB topology. In this condition, output active power of the inverter is about 217 W. Also,
the specification of the switches (their resistance and on-state
voltage) is as given in Section IV.
Fig. 19 shows the experimental results. The upper trace of the
figure shows the total output voltage of the cascaded submultilevel inverters. The middle trace shows the load voltage and
the lower trace shows the load current. The load voltage and
current THD is %1.44 and %0.2, respectively. The figures show
a good correspondence with the simulation results. In practice,
the switches are not ideal and they have voltage drop in their
on-state due to resistance and reverse on-state voltage of them.
Therefore, the peak of the output voltage may not reach 150 V
because of some voltage drop on the switches.
VII. CONCLUSION
In this paper, initially, a submultilevel inverter has been proposed and then the cascaded submultilevel inverters have been
considered as a generalized multilevel inverter in both symmetric and asymmetric conditions. The number of the dc voltage
sources in each submultilevel inverter is equal, but their values are different from one submultilevel inverter to another.
Therefore, the proposed multilevel inverter can be categorized
in asymmetric group. The optimal structures for the proposed
multilevel inverter were obtained considering several factors
such as the number of switching devices, number of dc voltage
sources, number of output voltage levels, standing voltage on
the switches etc. For the asymmetric topology, almost all of the

636


factors dictate that the number of dc voltage sources per submultilevel inverter should be 1. The comparison between the
proposed topology and the topologies presented in [12], [13],
and [15] and the CHB topologies has been presented considering
several factors. The simulation results of a 13-level symmetric
topology based on the proposed multilevel inverter have been
presented. In the case of asymmetric topology, the simulation
and experimental results have been presented for a 31-level inverter based on the proposed optimal structure to validate the
ability of the proposed topology in generating of desired output
voltage.
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Mohammad Farhadi Kangarlu (S’09) was born in
Kangarlu, East Azerbaijan, Iran, in 1987. He received
the B.S. and M.S. degrees (first class Hons.) both in
electrical power engineering from the University of
Tabriz, Tabriz, Iran, in 2008 and 2010, respectively,
where he is currently working toward the Ph.D. degree in electrical power engineering (power electronics and systems).
He is the author or coauthor of more than 25 journal and conference papers and one book. He also
holds seven patents in the area of power electronics.
His research interests include power electronic converters analysis and design,
power quality, and custom power devices.
Dr. Farhadi Kangarlu received the Best Researcher Award of the East Azerbaijan Province in 2011. He also received the Distinguished Student Award of
the University of Tabriz in 2007 and 2011.

Ebrahim Babaei (M’10) was born in Ahar, Iran,
in 1970. He received the B.S. and M.S. degrees
(first class Hons.) in electrical engineering from the
Department of Engineering, University of Tabriz,
Tabriz, Iran, in 1992 and 2001, respectively, where he
also received the Ph.D. degree in electrical engineering from the Department of Electrical and Computer
Engineering, in 2007.
In 2004, he joined the Faculty of Electrical and
Computer Engineering, University of Tabriz. He was
an Assistant Professor from 2007 to 2011 and has
been an Associate Professor since 2011. He is the author of more than 140
journal and conference papers. His current research interests include the analysis and control of power electronic converters, matrix converters, multilevel
converters, flexible ac transmission systems devices, power system transients,
and power system dynamics.

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