Course: BEng (Hons) in Electrical and Electronic Engineering

1. EEEC6420307
Digital Circuits and SystemDesign
Faculty of Engineering and Computer Technology
Laboratory Manual
Lecturer: Ravandran Muttiah BEng (Hons) MSc MIET
Year/Semester: Year 1 / Semester 2
Academic Session: 2021/2022
The information in this documentis important and should be noted by all students undertaking the
Bachelor of Engineering (Honours) in Electrical and Electronic Engineering
Approved by Coordinator: Endorsed By Dean:
------------------------------------------ __________________

2. AIMST University Faculty of Engineering and Computer Technology
BEng (Hons) in Electrical and Electronic Engineering Digital Circuits and System Design 1
Mini Project 2 - 4-to-1 Multiplexer And 1-to-4 Demultiplexer With
Enable
Multiplexers
In general, a multiplexer is a modular device that selects one of many input lines to
appear on a single output line. A demultiplexer performs the inverse operation; it takes a
single input line and routes it to one of several output lines. A simplified diagram
illustrating the general concept of multiplexing and demultiplexing is shown in figure 1.
The rotary switch 𝑆𝑊1moves from input line 𝐴 to 𝐵 to 𝐶, and so on. The rotary switch
𝑆𝑊
2 at the output of the channel is synchronised to 𝑆𝑊1 and it too moves from output
line 𝐴 to 𝐵 to 𝐶, and so on. This multiplex/demultiplex configuration illustrates one
manner in which data are selected and routed. The logic configuration is shown in figure
2. Here the signal, 𝑎, 𝑏, … 𝑘 are control signals that select which set of inputs/outputs will
be using the “single channel”. The channel in this configuration could be contained
within a computer system or could be a mechanism with which the computer
communicates with the outside world.
Figure 1: K-channel multiplex/demultiplex operation.
Figure 2: Simple logic diagram of K-channel multiplex/demultiplex.
𝐴in
𝐾in
𝐵in
Single
channel
𝐴out
𝐾out
𝐵out
Multiplexer Demultiplexer
⋮ ⋮
𝑆𝑊1 𝑆𝑊2
𝐴out
𝐵out
𝐾out
𝐴in
𝐵in
𝐾in
⋮
𝑎
𝑏
𝑘
𝑎
𝑏
𝑘
⋮

3. AIMST University Faculty of Engineering and Computer Technology
BEng (Hons) in Electrical and Electronic Engineering Digital Circuits and System Design 2
Multiplexer Circuit Structures
In an 𝑛 − to − 1 line multiplexer, one of the 𝑛 input data lines (𝐷𝑛−1 ,𝐷𝑛−2, …, 𝐷0) is
designated for connection to the single output line (𝑌) by a selection code (𝑆𝑘−1, … , 𝑆0),
where 𝑛 = 2𝑘
. Examine figure 3, which depicts a 4 − to − 1 line multiplexer, with 𝐵 =
𝑆1 and 𝐵 = 𝑆0. The circuit will connect data line 𝐷𝑖 to the output 𝑌 when the code,
𝑖 = (𝐵𝐴) (1)
is applied to the selection terminals. Table 1 displays the truth table of the multiplexer.
From the truth table we may write,
𝑌 = (𝐵
̅𝐴̅)𝐷0 + (𝐵
̅𝐴)𝐷1 + (𝐵𝐴̅)𝐷2 + (𝐵𝐴)𝐷3 (2)
The selection code forms the min-terms of two variables, 𝐵 and 𝐴. Hence, we may write,
𝑌 = ∑ 𝑚𝑖𝐷𝑖
3
𝑖=0 (3)
Figure 3: Functional diagram of 4 − to − 1 multiplexer.
Table 1: Truth table
𝐷0
𝐷3
𝐷1
𝐷2
𝑌
4 − to − 1
Multiplexer
𝐵 𝐴
Selection code
𝐵 𝐴 𝑌
0 0 𝐷0
0 1 𝐷1
1 0 𝐷2
1 1 𝐷3

4. AIMST University Faculty of Engineering and Computer Technology
BEng (Hons) in Electrical and Electronic Engineering Digital Circuits and System Design 3
Figure 4: Logic diagram of 4 − to − 1 multiplexer.
where the 𝑚𝑖 are the min-terms of the selection code. The logic diagram for the 4 − to −
1 multiplexer is shown in figure 4.
Demultiplexers
In the last section we examined a combinational logic circuit that multiplexed 𝑛 lines to
one line by using a selection code to specify which input line to connect to the output
line. In this section we will examine the inverse circuit, a demultiplexer. A demultiplexer
connects a single input line to one of 𝑛 output lines, the specific output line being
determined by an 𝑠 −bit selection code, where,
2𝑠
≥ 𝑛 (4)
A functional diagram for a 1 − to − 𝑛 demultiplexer is shown in figure 5. The selection
code is used to generate a min-term of 𝑠 variables; that min-term then gates the input data
to the proper output terminal. See figure 6 for a specific example. This 1 − to − 4
demultiplexer has an enable signal (𝐸) that controls the operation of the circuit. When 𝐸
is 1, the circuit is operational. We may thus describe the operation of the device by,
𝑌𝑖 = (𝑚𝑖𝐷)𝐸 (5)
𝐷0
𝐷1
𝐷2
𝐵
𝐷3
𝐴
2-to-4
Decoder
𝑌
0 1 2 3

5. AIMST University Faculty of Engineering and Computer Technology
BEng (Hons) in Electrical and Electronic Engineering Digital Circuits and System Design 4
where 𝐷 is the input signal to be distributed to the 𝑛 output line. Compare equation 5 to
equation 4.
Figure 5: Functional diagram of demultiplexer.
Figure 6: 1 − to − 4 demultiplexer with enable.
𝑌0
𝑌3
𝑌1
Outputs
Input 1 − to − 𝑛
Demultiplexer
1
Selection code
⋮
2 𝑆
⋯
𝑌0
𝑌1
𝑌2
𝐵
𝑌3
𝐴
2-to-4
Decoder
𝑚0 𝑚1 𝑚2 𝑚3
𝐷
𝐸
Input
Enable
Selection code

6. AIMST University Faculty of Engineering and Computer Technology
BEng (Hons) in Electrical and Electronic Engineering Digital Circuits and System Design 5
Objectives
The objective of this experimental project is to become acquainted with the design of
multiplexer and demultiplexer. Demonstrate your ability to design and construct the
multiplexer and demultiplexer, and to view the function of the inputs and outputs
respectively.
Specification
Design a 4 − to − 1 multiplexer, and a 1 − to − 4 demultiplexer with Enable.
Report
Write a laboratory report on this project:
(1) Explain in detail about the theory of 4 − to − 1 multiplexer, and the 1 − to − 4
demultiplexer with Enable.
(2) Discuss the method of productions and fabrications of multiplexer and
demultiplexer, and comment on the test results.
(3) Prepare slides for presentation and demonstration of this project.