1. Curriculum Vitae
Vibha. S
C/o Gunashekhar
#54, 2nd
main, 2nd
cross,
Muneshwar Nagar, E-mail :vibha9sheshadrigsss@gmail.com
Bengaluru - 560061. Contact No : +91- 8792492076
CAREER OBJECTIVE:
To secure a responsible position that offers opportunity where I can maximize my professional
interest, adopt innovations, which provide group culture and creative environment.
Very keen to work in Layout Design and Automation Domain. Waiting for a good opportunity to
learn.
EDUCATION QUALIFICATION:
Course Name School/College Name
Board/University
Name
Percentage/Aggregate
(Till 6th
sem)
B.E in
Electrical &
Electronics
Engineering
GSSS Institute of
Technology for
Women, Mysore.
Visvesvaraya
Technological
University, Belgam.
74.75%
PUC
Raghavendra
Gurukula Vidya
Peetha, Mysore.
Karnataka Pre
University Board,
Bengaluru.
84.33%
SSLC
Pragathi Vidya
Kendra, Mysore.
Karnataka State
Secondary Education
board, Bengaluru.
91.04%
Profile:
2 year 7 months of experience in Automation and Analog layout domain at Sankalp and KPIT
Semiconductors.
Professional Details:
l Experience in Automation and Layout Design of Analog Blocks.
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2. Projects:
 PLL Layout design:
Description: Layout design from scratch.
Challenges:
l Reduction of area along with following the constraints.
l Routing the signal and power flow.
l Routing matching patterns.
Tools Used: Virtuoso Layout XL and schematic XL.
Duration of Project: ongoing
Responsibilities:- To do all the blocks from scratch with meeting all constraints.
 Automating whole QA flow of Helix:
Description: Writing scripts for all possible checklists to automate testing Helix flow
manually. And integrate to megatest. Scripts are written using skill.
Challenges:
l To find all possible test cases.
l Minimum bugs in scripts.
l Learning megatest flow and implementing it to my scripts.
Tools Used: Helix placement Tool.
Duration of Project: ongoing
Responsibilities:-To think in all angles of QA engineer and implement all cases in script.
 QUALITY ASSURANCE on Synopsys Placement Tool(Helix) and Cadence
Placement Tool- Qbert and Writing Scripts for Automating QA
Description: Checking all the checklists to assure Helix is working fine on particular
Technology. And writing skill scripts to automating each checklist. Working on bug
detection CDNS placement enhancer from cadence(Qbert).
Challenges:
2

3. l To find the bugs as much as possible, learning tool in deep.
l Covering all cases while writing scripts. Debugging.
Tools Used: Helix placement Tool, CDNS placement tool.
Duration of Project: 4 months
Responsibilities:-To understand tool perfectly. And Understand flow of QA to write
scripts.
 TECHNOLOGY MIGRATION:
Description: Porting of 12 IPs and a Test Chip from tsmc65nm to gf40nm.
Challenges:
l Design rules for ESD-FETs were explored and accordingly fixed in the layouts.
l All vias were found flattened and put in cells, which were used in layout. These vias
were restored to standard viaDefs.
l Flattened Pcells in form of cells were found in the source database. These flattened
Pcells were restored to pcells form tech lib.
l Corner cases and generalization of flow for all the cases (IPs).
l Incorporating different small scripts to accomplish big task.
l Identifying base layer related extraction errors.
Tools Used: Virtuoso Layout Editor, Virtuoso Schematic editor, PVS.
Duration of Project: 4 months
Responsibilities:-
l To write the codes to reduce repetitive and manul work while porting and while
cleaning DRC and LVS.
l Adjusting & fixing DRC and DFM issues without changing much the overall placement
and size of the block and cleaning LVS.
.
 CHECKLIST AUTOMATION:
Description: Writing codes for different DRC rule checks like ploycut rules, width checks,
spacing checks, via checks, etc.
Challenges:
3

4. l To find the logic which gives correct output and highlights correct part of shape.
Tools Used: Assura, Virtuoso Layout suit.
Duration of Project: 2 and half months
Responsibilities:-To write codes, understanding problem definition correctly.
 4-bit FIFO:
Description: Custom design of 8-deep 4-bit word FIFO with read & write pointers
incrementing on all edges of the corresponding clock.Upon reset, the contents are cleared
and the pointers are spaced 4 locations apart.Write clk period is 2X read clk period and
two locations are written on every write clock cycle.FIFO full and FIFO empty conditions
are implemented.
Challenges:
Sizing of gates involved to get equal rise and fall time. Avoiding glitches. Standard cell with
proper grid and contact spacing. Top level Routing.
Tools Used: Assura, Virtuoso Layout Editor, Virtuoso Schematic Editor.
Duration of Project: 20 days.
Responsibilities:-Schematic design and Layout of Decoder. Design and Layout of 3 bit
counter used for implementing the constraint and Logic Design involved in it. And top
level routing.
Other Details:
l Automations
 Area estimation of Top-block given the schematic. And Creating a layout view for all the
blocks Hierarchically which has boundary of area. (User can give % of routing area
required).
 To calculate width, length, fringe width of fringe cap and replace it by apmom of same
size.
 To resize selected vias to the current technology DFM.
 To extract devices, layers, and vias used in the whole block eliminating redundancy. etc...
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5. ● CAD Tools :
Cadence Layout and schematic Editor – L and xl .
ICV(DRC/LVS)
● Programming Languages known :
 SKILL
 Shell (basics) and make file creation
 Perl Basics
 Assura Rule Writing.
PERSONAL PROFILE:
Name : Vibha. S
Father’s Name : Sheshadri. H. S
Mother’s Name : Sreelakshmi
Nationality : Indian
Date of Birth : 9th
September 1991
Hobbies :Cooking, making craft, Keychain collection and Pencil
sketching.
Languages known : English, Hindi and Kannada.
Place : Bengaluru
Date : (Vibha. S)
5

6. ● CAD Tools :
Cadence Layout and schematic Editor – L and xl .
ICV(DRC/LVS)
● Programming Languages known :
 SKILL
 Shell (basics) and make file creation
 Perl Basics
 Assura Rule Writing.
PERSONAL PROFILE:
Name : Vibha. S
Father’s Name : Sheshadri. H. S
Mother’s Name : Sreelakshmi
Nationality : Indian
Date of Birth : 9th
September 1991
Hobbies :Cooking, making craft, Keychain collection and Pencil
sketching.
Languages known : English, Hindi and Kannada.
Place : Bengaluru
Date : (Vibha. S)
5