1. A 175μW 100MHz-2GHz inductorless receiver front-
end in 65nm CMOS
Carl Bryant, Henrik Sjöland
Department of Electrical and Information Technology, Lund University, Box 118, 221 00 Lund
Abstract—This paper presents an inductorless ultra-low power of current consumption, has a limited usefulness due to the
frontend for applications such as sensor networks and medical resulting noise [2].
implants. By using a completely inductorless topology the chip Providing the input impedance using a feedback structure
area is just 0.017mm2, excluding pads. A real input impedance of such as a common gate or shunt feedback stage requires gain,
300Ω is achieved with current feedback. Manufactured in 65nm
and thus power to provide the match. If we assume that the
CMOS, it measures more than 17dB gain from 100MHz to
2000MHz while consuming only 175μW from a 0.9V supply (The resistance is provided by feedback of current from a
LNA consumes 115μW). The measured noise figure and IIP 3 is transconductance stage as illustrated by Fig. 1 the input
11dB and -16.8dBm respectively. impedance becomes
Rin  1 g m . (1)
Index Terms—CMOS, Low Noise Amplifier, LNA, Mixer, The resulting input impedance is inversely proportional to
Front-end, ultra low power, impedance matching, inductorless
the gain, which is proportional to the power consumption. By
designing for a higher than normal termination impedance we
I. INTRODUCTION should thus be able to reduce the power consumption. High
With the advances in communications technology we are impedances are, however, more sensitive to parasitic
regularly finding new applications that benefit from being capacitance from the pad, package and ESD-protection. As a
attached to wireless data networks. For a range of these compromise we have chosen an impedance of 300Ω.
applications, such as sensor networks, medical implants,
active RFID, etcetera. Devices should be cheap, compact and
have very long battery life. Suitable radio circuits should thus
have the same properties of being low cost, small, and Rin - gm
consuming a minimum amount of power. Circuits to be v i
manufactured in quantity should preferably be designed in
Figure 1. Impedance from current feedback
CMOS for cheapness and the possibility of integration
together with digital blocks. As CMOS is made smaller and An impedance of 300Ω requires a total gm of 3.33mS.
smaller it is today not just suitable for RF applications in Although this is a significant improvement over an equivalent
general; the performance offered by the latest process nodes 50Ω circuit requiring 20mS, even this is tricky to achieve at
means that it is now also suitable for ultra-low power radio. the current consumption we are aiming for. Apart from biasing
Really pushing the power consumption is a challenge in the devices in moderate to weak inversion we can also trade
itself, requiring any current consumed to be used efficiently. speed for gain by using complementary devices. Without
With MOS devices it is possible to achieve more gain for the inductors we can’t practically use very low supply voltages
same power consumption by biasing them in the medium or anyway without losing too much linearity. Even with
low inversion regions [1]. Unfortunately the speed quickly complementary stages, however, a single stage struggles to
falls off at low bias currents, but with modern CMOS achieve the sought matching impedance.
processes we have fast devices to begin with, and so we can In [2] cross coupling techniques are used to increase the
hope to trade some of this speed for improved gain. gain from each stage. A differential input LNA however
To minimize external components the receiver should be requires some form of balun, which means an additional
able to provide acceptable matching on chip. Though an external component as well as a limitation on the available
inductorless design is the most compact, providing a real bandwidth. Since we want to avoid unnecessary external
impedance without excessive noise or power consumption is a components the input should therefore be single ended.
challenge. To achieve negative feedback with two stages (more are
II. CIRCUIT DESIGN impractical when pushing the current consumption this low)
one stage should be inverting and the other non-inverting. A
To provide a real input impedance with an inductorless common way of constructing an inductorless LNA is with a
MOS based LNA design, we require either a resistive common source stage to provide voltage gain, and a common
termination, i.e. a resistor shunted to ground, or some form of drain stage to provide the feedback current such as in [3].
feedback structure to provide the correct current to voltage This paper suggests instead using a common gate stage as
ratio. Resistive termination, although practically free in terms the non-inverting stage, see Fig. 2. The input is the point of the
978-1-4244-8971-8/10$26.00 c 2010 IEEE

2. circuit with the lowest impedance. Because of this a common Although the circuit is intended for use with a 300Ω
gate stage at the input can provide voltage gain as well as the source, it is quite possible to use it with a 50Ω source with an
common source output stage, but non-inverting. Furthermore external matching network. The wide bandwidth and small
the signal current through the input stage will also contribute size makes this circuit quite flexible. The impedance
to the input matching. The output stage has been split to transformation will then provide an additional voltage gain of
provide high isolation and voltage gain. All devices are biased roughly 8dB.
close to their threshold voltage. A single balanced mixer, Fig. 4, completes the front-end.
The devices are small to reduce the load of the LNA and LO
drivers.
Figure 2. LNA schematic (biasing details not shown)
Figure 4. Mixer (biasing not shown)
As the parasitic extraction tool wasn’t working during
layout, the pad capacitance was assumed to be about 50fF, The relatively high LNA gain suppresses the mixer noise well.
based on [4, 5], both of which are based on 65nm processes, The simulated LNA noise figure is 8dB, and the total frontend
one from ST Microelectronics, the same as this circuit. Since noise figure 9.5dB.
very recently it has been possible to make parasitic
III. RESULTS
extractions, and as it turns out the pad capacitance is around
100fF, leading to worse than expected input impedance. Since The circuits were mounted in QFN40 packages, and
no RF pads were available in the design kit, an analog pad was soldered to PCBs. To measure S11 a TRL (Through-Reflect-
modified by reducing the size of the pad and ESD diodes as Match) kit was constructed using the same type of circuit
well as some rerouting of metal conductors. The reduced ESD board as the chip was attached to. This kit allows calibration
devices still dominate the input capacitance with just over to the end of the PCB input conductor.
100fF in total. With all that parasitic capacitance, the LNA As can be seen in Fig. 5 (normalized to 300Ω) the
input devices have to be quite small so as not to hurt the measured input impedance differs notably from simulations.
matching any more. This unfortunately limits the design The squares mark 470MHz and the rings 2GHz, to help
freedom, with a high noise figure as a result. compare the two traces. The grey ring around the centre marks
The circuit operates to some extent as an active inductor the boundary where S11 is better than -10dB.
which helps cancel some of the input capacitance. The gates of
the second stage load the first stage, see Fig. 3. The impedance
contribution of the feedback loop ignoring the first stage input
impedance becomes
g ds1  jC gs2
Z in,loop  . (2)
g m1  g m 2
As we can see the negative reactance at the intermediate
node translates to a positive reactance (i.e. inductance) at the
input. Measured
Simulated
Figure 5. Input impedance. Z0 = 300Ω
It looks much like there is some additional capacitance
somewhere. Some of it is explained by the package, but there
still appears to be notably more than expected.
Figure 3. Input matching of circuit

3. There are several possible explanations to this error. The close to simulations, it appears that the circuit itself is
first is that the renormalization to 300Ω amplifies any functioning.
measurement error (The TRL kit has a reference impedance of Fig. 8 shows the noise figure versus source impedance at
100Ω). It is also possible that the extensive modification of the 1GHz. A Maury MT982EU32 automatic impedance tuner
pad frame has caused some unexpected problem. The design system was used to perform this source pull measurement. The
kit pads have their active layers added prior to manufacture measurement is made on a packaged chip and is not
and it is conceivable that the modified pad was mistaken for compensated.
the original pad, and had its ESD assembly modified.
Another explanation is that there is a large uncertainty of
the components or their models, however a later circuit that is
not dissimilar to this one has come back from manufacturing,
and initial measurements show little or no extra capacitance.
The main difference is that the RF pad used for this circuit
was modified from a non-RF pad in the design kit, while the
newer circuit has a fully custom made pad frame. The pad and
diode dimensions should be approximately the same.
To find out how well the circuit itself is functioning we’ll
attempt to remove the effect of the package and the additional
capacitance from the measurements. The package impedance
is estimated using [6] (50fF self capacitance and 2nH bond
wire inductance). After that we have to remove another 75fF
before the measured S11 is similar to simulations. The Figure 8. Source pull noise measurement, Z0 = 50Ω
compensated impedance can be seen in Fig. 6.
The lowest noise figure is achieved close to the conjugate
match (gain not shown) and is 11.1dB. This corresponds well
with measurements taken with a 50Ω matching network.
Two tone linearity measurements were performed at 1GHz
with an LC matching network at the input to provide a 50Ω
match. The result can be seen in Fig. 9. The 1dB compression
Measured point is measured to -27.5dBm and the third order intercept
(compensated)
point to -16.8dBm.
Simulated
Figure 6. Input impedance after compensation, Z0 = 300Ω
Figure 9. Linearity measurements
Table 1 compares the circuit performance to that of other
publications with ultra-low power consumption. The second
column shows how the performance is affected when
including an external 50Ω matching net.
The areas have been estimated from chip photographs to
not include pads or unused space. A photograph of the
Figure 7. Input matching manufactured circuit is included as Fig. 11. The area shown is
approximately 0.5x0.5mm. The active area of the front-end is
Fig. 7 shows S11 before and after compensation, with
comparison to simulation. Though there is still some about 0.017mm2.
uncertainty as to what should and shouldn’t be there, the
compensated input impedance is similar to simulations.
Combined with the fact that the DC operating points are very

4. Design This Work W/ 50Ω matching [7] [8] [9] [11] [10]1 [2]1
Technology 65nm CMOS 0.13μm 0.13μm 0.18μm 0.18μm 0.18μm 0.13μm
CMOS CMOS CMOS CMOS CMOS CMOS
Inductorless Yes - No No No No No Yes
Single ended Yes Yes Yes Yes No Yes No
f (MHz) 100-2000 - 2400 2450 2400 400 820-1070 100-930
Gain (dB) >17 >25 15.7 20 30.5 25 15.6 13
NF (dB) 11 (101) 18.3 7.5 10.2 3 4.9 4
Pcons (μW) 175 (1151) 500 600 500 500 100 720
CP1dB (dBm) -27.5 -28 -19 -31 -21.8 -18
IIP3 (dBm) -16.8 -9 -10 -13.7 -10
Area (mm2) 0.017 0.09 0.5 2.1 0.22 0.27
Z0 (Ω) 300 50 50 50 50 8000 50 50
Table 1. Summary of measurement results, and comparisons to other published receivers and LNAs
1
LNA only
Fig. 10 shows the voltage gain of the receiver. A circuit
with a matching network to operate with 50Ω input impedance ACKNOWLEDGMENT
would have 8dB additional voltage gain. The measurements Thanks to Fredrik Ahlberg for sorting out the software for
are close to expected. the source pull measurement.
This circuit has been manufactured within the project for
Wireless Communication for Ultra Portable Devices, funded by
SSF – Swedish Foundation for Strategic Research.
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